From a43425e8835983e7c93a15a2d6a42fdb292c1676 Mon Sep 17 00:00:00 2001 From: yongari Date: Fri, 30 Apr 2010 00:34:00 +0000 Subject: Both RX_GMF_LP_THR and RX_GMF_UP_THR must be 16 bits register. If it is 8bits register then RX FIFO size can't exceed 2KB which is not true for almost all Yukon II controller. --- sys/dev/msk/if_mskreg.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sys/dev/msk/if_mskreg.h') diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 34cac67..293ca29 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -621,8 +621,8 @@ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ -#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ -#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ -- cgit v1.1