From bedce823534f9510ef9c65764069f927d359aeb8 Mon Sep 17 00:00:00 2001 From: marius Date: Sun, 30 Dec 2007 01:32:03 +0000 Subject: o In preparation for basing a new driver on this one: - ANSIfy - try to bring closer to style(9) - remove banal comments. o Add my copyright for having done lots of fixes and improvements. --- sys/dev/gem/if_gemvar.h | 104 +++++++++++++++++++++--------------------------- 1 file changed, 46 insertions(+), 58 deletions(-) (limited to 'sys/dev/gem/if_gemvar.h') diff --git a/sys/dev/gem/if_gemvar.h b/sys/dev/gem/if_gemvar.h index 08b2105..5a2952f 100644 --- a/sys/dev/gem/if_gemvar.h +++ b/sys/dev/gem/if_gemvar.h @@ -31,20 +31,15 @@ #ifndef _IF_GEMVAR_H #define _IF_GEMVAR_H - #include #include /* - * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. - */ - -/* * Transmit descriptor list size. This is arbitrary, but allocate * enough descriptors for 64 pending transmissions and 16 segments - * per packet. This limit is not actually enforced (packets with more segments - * can be sent, depending on the busdma backend); it is however used as an - * estimate for the tx window size. + * per packet. This limit is not actually enforced (packets with + * more segments can be sent, depending on the busdma backend); it + * is however used as an estimate for the TX window size. */ #define GEM_NTXSEGS 16 @@ -55,7 +50,7 @@ #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) /* - * Receive descriptor list size. We have one Rx buffer per incoming + * Receive descriptor list size. We have one RX buffer per incoming * packet, so this logic is a little simpler. */ #define GEM_NRXDESC 256 @@ -63,26 +58,19 @@ #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) /* - * How many ticks to wait until to retry on a RX descriptor that is still owned - * by the hardware. + * How many ticks to wait until to retry on a RX descriptor that is + * still owned by the hardware. */ #define GEM_RXOWN_TICKS (hz / 50) /* - * Control structures are DMA'd to the GEM chip. We allocate them in - * a single clump that maps to a single DMA segment to make several things - * easier. + * Control structures are DMA'd to the GEM chip. We allocate them + * in a single clump that maps to a single DMA segment to make + * several things easier. */ struct gem_control_data { - /* - * The transmit descriptors. - */ - struct gem_desc gcd_txdescs[GEM_NTXDESC]; - - /* - * The receive descriptors. - */ - struct gem_desc gcd_rxdescs[GEM_NRXDESC]; + struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */ + struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */ }; #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) @@ -90,7 +78,7 @@ struct gem_control_data { #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) /* - * Software state for transmit job mbufs (may be elements of mbuf chains). + * software state for transmit job mbufs (may be elements of mbuf chains) */ struct gem_txsoft { struct mbuf *txs_mbuf; /* head of our mbuf chain */ @@ -104,7 +92,7 @@ struct gem_txsoft { STAILQ_HEAD(gem_txsq, gem_txsoft); /* - * Software state for receive jobs. + * software state for receive jobs */ struct gem_rxsoft { struct mbuf *rxs_mbuf; /* head of our mbuf chain */ @@ -113,7 +101,7 @@ struct gem_rxsoft { }; /* - * Software state per device. + * software state per device */ struct gem_softc { struct ifnet *sc_ifp; @@ -123,20 +111,20 @@ struct gem_softc { device_t sc_dev; /* generic device information */ u_char sc_enaddr[ETHER_ADDR_LEN]; struct callout sc_tick_ch; /* tick callout */ - struct callout sc_rx_ch; /* delayed rx callout */ + struct callout sc_rx_ch; /* delayed RX callout */ int sc_wdog_timer; /* watchdog timer */ void *sc_ih; struct resource *sc_res[2]; - bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */ - bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */ - bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */ - bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */ - bus_dmamap_t sc_dmamap; /* bus dma handle */ + bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */ + bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */ + bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */ + bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */ + bus_dmamap_t sc_dmamap; /* bus DMA handle */ - int sc_phyad; /* addr. of PHY to use or -1 for any */ + int sc_phyad; /* PHY to use or -1 for any */ - u_int sc_variant; /* which GEM are we dealing with? */ + u_int sc_variant; #define GEM_UNKNOWN 0 /* don't know */ #define GEM_SUN_GEM 1 /* Sun GEM */ #define GEM_SUN_ERI 2 /* Sun ERI */ @@ -147,14 +135,14 @@ struct gem_softc { ((sc)->sc_variant == GEM_APPLE_GMAC || \ (sc)->sc_variant == GEM_APPLE_K2_GMAC) - u_int sc_flags; /* */ -#define GEM_INITED (1 << 0) /* reset persistent regs initialized */ + u_int sc_flags; +#define GEM_INITED (1 << 0) /* reset persistent regs init'ed */ #define GEM_LINK (1 << 1) /* link is up */ -#define GEM_PCI (1 << 2) /* XXX PCI busses are little-endian */ +#define GEM_PCI (1 << 2) /* PCI busses are little-endian */ #define GEM_SERDES (1 << 3) /* use the SERDES */ /* - * Ring buffer DMA stuff. + * ring buffer DMA stuff */ bus_dma_segment_t sc_cdseg; /* control data memory */ int sc_cdnseg; /* number of segments */ @@ -162,33 +150,33 @@ struct gem_softc { bus_addr_t sc_cddma; /* - * Software state for transmit and receive descriptors. + * software state for transmit and receive descriptors */ struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; /* - * Control data structures. + * control data structures */ struct gem_control_data *sc_control_data; #define sc_txdescs sc_control_data->gcd_txdescs #define sc_rxdescs sc_control_data->gcd_rxdescs - int sc_txfree; /* number of free Tx descriptors */ - int sc_txnext; /* next ready Tx descriptor */ - int sc_txwin; /* Tx descriptors since last Tx int */ + int sc_txfree; /* number of free TX descriptors */ + int sc_txnext; /* next ready TX descriptor */ + int sc_txwin; /* TX desc. since last TX intr. */ - struct gem_txsq sc_txfreeq; /* free Tx descsofts */ - struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ + struct gem_txsq sc_txfreeq; /* free TX descsofts */ + struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */ - int sc_rxptr; /* next ready RX descriptor/descsoft */ - int sc_rxfifosize; /* Rx FIFO size (bytes) */ + int sc_rxptr; /* next ready RX desc./descsoft */ + int sc_rxfifosize; /* RX FIFO size (bytes) */ - /* ========== */ int sc_ifflags; int sc_csum_features; }; +/* XXX this should be handled by bus_dma(9). */ #define GEM_DMA_READ(sc, v) \ ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v)) #define GEM_DMA_WRITE(sc, v) \ @@ -237,19 +225,19 @@ do { \ #ifdef _KERNEL extern devclass_t gem_devclass; -int gem_attach(struct gem_softc *); -void gem_detach(struct gem_softc *); -void gem_suspend(struct gem_softc *); -void gem_resume(struct gem_softc *); -void gem_intr(void *); +int gem_attach(struct gem_softc *sc); +void gem_detach(struct gem_softc *sc); +void gem_intr(void *v); +void gem_resume(struct gem_softc *sc); +void gem_suspend(struct gem_softc *sc); -int gem_mediachange(struct ifnet *); -void gem_mediastatus(struct ifnet *, struct ifmediareq *); +int gem_mediachange(struct ifnet *ifp); +void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); /* MII methods & callbacks */ -int gem_mii_readreg(device_t, int, int); -int gem_mii_writereg(device_t, int, int, int); -void gem_mii_statchg(device_t); +int gem_mii_readreg(device_t dev, int phy, int reg); +void gem_mii_statchg(device_t dev); +int gem_mii_writereg(device_t dev, int phy, int reg, int val); #endif /* _KERNEL */ -- cgit v1.1