From 51974d427a3dddb6697b8ee76c62c5b05215bfd9 Mon Sep 17 00:00:00 2001 From: jkim Date: Mon, 21 Aug 2006 19:10:58 +0000 Subject: Use aperture base address from north bridge. Some BIOS does not encode misc. control registers correctly and it is inconsistent with north bridge. In fact, there are too many broken BIOS implementations out there and we cannot fix every possible combination but at least it is consistent with what we advertise with ioctl(2). --- sys/dev/agp/agp_amd64.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'sys/dev/agp') diff --git a/sys/dev/agp/agp_amd64.c b/sys/dev/agp/agp_amd64.c index 2e949e5..9a4ccdb 100644 --- a/sys/dev/agp/agp_amd64.c +++ b/sys/dev/agp/agp_amd64.c @@ -182,14 +182,9 @@ agp_amd64_attach(device_t dev) sc->n_mctrl = n; - if (bootverbose) { + if (bootverbose) device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", sc->n_mctrl); - for (i = 0; i < sc->n_mctrl; i++) - device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i, - pci_cfgregread(0, sc->mctrl[i], 3, - AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK); - } if ((error = agp_generic_attach(dev))) return error; @@ -380,11 +375,11 @@ agp_amd64_apbase_fixup(device_t dev) uint32_t apbase; int i; - apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4); + sc->apbase = rman_get_start(sc->agp.as_aperture); + apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK; for (i = 0; i < sc->n_mctrl; i++) - pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE, - apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4); - sc->apbase = apbase << 25; + pci_cfgregwrite(0, sc->mctrl[i], 3, + AGP_AMD64_APBASE, apbase, 4); } static void -- cgit v1.1