From eece70b41c85532ab7fff01d9abbb753b9c5a271 Mon Sep 17 00:00:00 2001 From: raj Date: Thu, 16 Oct 2008 19:06:24 +0000 Subject: Eliminate flushing of L2 cache in ARM context switch routines. With VIPT L2 cache such syncing not only is redundant, but also a performance penalty. Pointed out by: cognet --- sys/arm/arm/swtch.S | 8 -------- 1 file changed, 8 deletions(-) (limited to 'sys/arm') diff --git a/sys/arm/arm/swtch.S b/sys/arm/arm/swtch.S index 59c2b63..8f0f9b2 100644 --- a/sys/arm/arm/swtch.S +++ b/sys/arm/arm/swtch.S @@ -143,8 +143,6 @@ ENTRY(cpu_throw) ldr r9, .Lcpufuncs mov lr, pc ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] - mov lr, pc - ldr pc, [r9, #CF_L2CACHE_WBINV_ALL] ldr r0, [r7, #(PCB_PL1VEC)] ldr r1, [r7, #(PCB_DACR)] /* @@ -174,8 +172,6 @@ ENTRY(cpu_throw) movne r1, #4 movne lr, pc ldrne pc, [r9, #CF_DCACHE_WB_RANGE] - movne lr, pc - ldrne pc, [r9, #CF_L2CACHE_WB_RANGE] #endif /* PMAP_INCLUDE_PTE_SYNC */ /* @@ -332,8 +328,6 @@ ENTRY(cpu_switch) ldr r1, .Lcpufuncs mov lr, pc ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] - mov lr, pc - ldr pc, [r1, #CF_L2CACHE_WBINV_ALL] .Lcs_cache_purge_skipped: /* rem: r6 = lock */ /* rem: r9 = new PCB */ @@ -366,8 +360,6 @@ ENTRY(cpu_switch) mov r1, #4 mov lr, pc ldr pc, [r2, #CF_DCACHE_WB_RANGE] - mov lr, pc - ldr pc, [r2, #CF_L2CACHE_WB_RANGE] .Lcs_same_vector: #endif /* PMAP_INCLUDE_PTE_SYNC */ -- cgit v1.1