From d7e5c47a911bedfa32eef87e105eb0302c3ca452 Mon Sep 17 00:00:00 2001 From: imp Date: Wed, 25 Oct 2006 07:58:18 +0000 Subject: MFp4: Status register bits --- sys/arm/at91/at91_sscreg.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'sys/arm') diff --git a/sys/arm/at91/at91_sscreg.h b/sys/arm/at91/at91_sscreg.h index fafa6ab..7ed95ca 100644 --- a/sys/arm/at91/at91_sscreg.h +++ b/sys/arm/at91/at91_sscreg.h @@ -132,4 +132,18 @@ #define SSC_TFMR_DATDEF (1u << 5) /* DATDEF: Data Default Value */ #define SSC_TFMR_DATLEN (0x1fu << 0) /* DATLEN: Data Length */ +/* SSC_SR */ +#define SSC_SR_TXRDY (1u << 0) +#define SSC_SR_TXEMPTY (1u << 1) +#define SSC_SR_ENDTX (1u << 2) +#define SSC_SR_TXBUFE (1u << 3) +#define SSC_SR_RXRDY (1u << 4) +#define SSC_SR_OVRUN (1u << 5) +#define SSC_SR_ENDRX (1u << 6) +#define SSC_SR_RXBUFF (1u << 7) +#define SSC_SR_TXSYN (1u << 10) +#define SSC_SR_RSSYN (1u << 11) +#define SSC_SR_TXEN (1u << 16) +#define SSC_SR_RXEN (1u << 17) + #endif /* ARM_AT91_AT91_SSCREG_H */ -- cgit v1.1