From 5b5d402e310bfeb84d4bc66d726e9ec45b26b6dd Mon Sep 17 00:00:00 2001 From: cognet Date: Thu, 11 Sep 2008 20:43:38 +0000 Subject: Bandaid: disable interrupts to make sure intr_enabled and the IER register are in sync. I'm not sure why it is needed, and why it wouldn't be on other arm platforms, but it prevents a lockup under heavy I/O. --- sys/arm/xscale/ixp425/ixp425.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'sys/arm') diff --git a/sys/arm/xscale/ixp425/ixp425.c b/sys/arm/xscale/ixp425/ixp425.c index b1a7a56..af87503 100644 --- a/sys/arm/xscale/ixp425/ixp425.c +++ b/sys/arm/xscale/ixp425/ixp425.c @@ -143,22 +143,27 @@ ixp425_irq2gpio_bit(int irq) void arm_mask_irq(uintptr_t nb) { + int i; + + i = disable_interrupts(I32_bit); intr_enabled &= ~(1 << nb); ixp425_set_intrmask(); + restore_interrupts(i); /*XXX; If it's a GPIO interrupt, ACK it know. Can it be a problem ?*/ if ((1 << nb) & IXP425_INT_GPIOMASK) IXPREG(IXP425_GPIO_VBASE + IXP425_GPIO_GPISR) = ixp425_irq2gpio_bit(nb); - - } void arm_unmask_irq(uintptr_t nb) { - + int i; + + i = disable_interrupts(I32_bit); intr_enabled |= (1 << nb); ixp425_set_intrmask(); + restore_interrupts(i); } static __inline uint32_t -- cgit v1.1