From 13afdc288fd9e982249ab19116c195578ff90fa1 Mon Sep 17 00:00:00 2001 From: ian Date: Wed, 14 May 2014 16:32:27 +0000 Subject: MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281, r257282, r257332 Wait for DesignWare UART transfers completion before accessing line control Enable UART busy detection handling for Armada XP - based board Enable SATA interface on Armada XP Run mvs SATA driver on Armada XP instead of old mv_sata Retire arm_remap_nocache() and the data and constants associated with it. Remove hard-coded mappings related to Armada XP support Fix-up DTB for Armada XP registers' base according to the actual settings Change Armada XP kernel load address to the u-boot's end address Remove not working and deprecated PJ4Bv6 support Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU Add missing ARMv6 CPU functions to ARM Makefile --- sys/arm/include/armreg.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'sys/arm/include/armreg.h') diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index d47f743..35d2e9f 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -172,14 +172,10 @@ #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ #endif -#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ /* Marvell's CPUIDs with ARM ID in implementor field */ -#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ -#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */ #define CPU_ID_FA526 0x66015260 #define CPU_ID_FA626TE 0x66056260 -- cgit v1.1