From f3c6b45c01969eefad06f216c13f6e4d35951527 Mon Sep 17 00:00:00 2001 From: br Date: Thu, 4 Sep 2014 12:44:40 +0000 Subject: Add initial support for Altera SOCFPGA (heterogeneous ARM/FPGA) SoC family. Include board configuration for Terasic SoCKit (Altera Cyclone V). Sponsored by: DARPA, AFRL --- sys/arm/altera/socfpga/files.socfpga | 17 +++++ sys/arm/altera/socfpga/socfpga_common.c | 83 ++++++++++++++++++++++++ sys/arm/altera/socfpga/socfpga_machdep.c | 107 +++++++++++++++++++++++++++++++ sys/arm/altera/socfpga/std.socfpga | 21 ++++++ 4 files changed, 228 insertions(+) create mode 100644 sys/arm/altera/socfpga/files.socfpga create mode 100644 sys/arm/altera/socfpga/socfpga_common.c create mode 100644 sys/arm/altera/socfpga/socfpga_machdep.c create mode 100644 sys/arm/altera/socfpga/std.socfpga (limited to 'sys/arm/altera') diff --git a/sys/arm/altera/socfpga/files.socfpga b/sys/arm/altera/socfpga/files.socfpga new file mode 100644 index 0000000..654462d --- /dev/null +++ b/sys/arm/altera/socfpga/files.socfpga @@ -0,0 +1,17 @@ +# $FreeBSD$ + +kern/kern_clocksource.c standard + +arm/arm/bus_space_generic.c standard +arm/arm/bus_space_asm_generic.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/arm/cpufunc_asm_arm10.S standard +arm/arm/cpufunc_asm_arm11.S standard +arm/arm/cpufunc_asm_armv7.S standard + +arm/arm/bus_space-v6.c standard +arm/arm/gic.c standard +arm/arm/mpcore_timer.c standard + +arm/altera/socfpga/socfpga_common.c standard +arm/altera/socfpga/socfpga_machdep.c standard diff --git a/sys/arm/altera/socfpga/socfpga_common.c b/sys/arm/altera/socfpga/socfpga_common.c new file mode 100644 index 0000000..86d46e3 --- /dev/null +++ b/sys/arm/altera/socfpga/socfpga_common.c @@ -0,0 +1,83 @@ +/*- + * Copyright (c) 2014 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#define RESMAN_BASE 0xFFD05000 +#define RESMAN_CTRL 0x4 +#define SWWARMRSTREQ (1 << 1) + +void +cpu_reset(void) +{ + bus_addr_t vaddr; + + if (bus_space_map(fdtbus_bs_tag, RESMAN_BASE, 0x10, 0, &vaddr) == 0) { + bus_space_write_4(fdtbus_bs_tag, vaddr, + RESMAN_CTRL, SWWARMRSTREQ); + } + + while (1); +} + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + + if (!fdt_is_compatible(node, "arm,gic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + return (0); +} + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_pic_decode_ic, + NULL +}; diff --git a/sys/arm/altera/socfpga/socfpga_machdep.c b/sys/arm/altera/socfpga/socfpga_machdep.c new file mode 100644 index 0000000..b098663 --- /dev/null +++ b/sys/arm/altera/socfpga/socfpga_machdep.c @@ -0,0 +1,107 @@ +/*- + * Copyright (c) 2014 Ruslan Bukin + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +vm_offset_t +platform_lastaddr(void) +{ + + return (arm_devmap_lastaddr()); +} + +void +platform_probe_and_attach(void) +{ + +} + +void +platform_gpio_init(void) +{ + +} + +void +platform_late_init(void) +{ + +} + +int +platform_devmap_init(void) +{ + + /* UART */ + arm_devmap_add_entry(0xffc00000, 0x100000); + + /* + * USB OTG + * + * We use static device map for USB due to some bug in the Altera + * which throws Translation Fault (P) exception on high load. + * It might be caused due to some power save options being turned + * on or something else. + */ + arm_devmap_add_entry(0xffb00000, 0x100000); + + return (0); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} diff --git a/sys/arm/altera/socfpga/std.socfpga b/sys/arm/altera/socfpga/std.socfpga new file mode 100644 index 0000000..c6607a5 --- /dev/null +++ b/sys/arm/altera/socfpga/std.socfpga @@ -0,0 +1,21 @@ +# $FreeBSD$ + +makeoption ARM_LITTLE_ENDIAN + +cpu CPU_CORTEXA +machine arm armv6 + +options PHYSADDR=0x00000000 + +makeoptions KERNPHYSADDR=0x00f00000 +options KERNPHYSADDR=0x00f00000 + +makeoptions KERNVIRTADDR=0xc0f00000 +options KERNVIRTADDR=0xc0f00000 + +options ARM_L2_PIPT + +options IPI_IRQ_START=0 +options IPI_IRQ_END=15 + +files "../altera/socfpga/files.socfpga" -- cgit v1.1