From 03e0206d84485a74106dd8900455d6656c09a6f2 Mon Sep 17 00:00:00 2001 From: jkim Date: Thu, 13 Jul 2006 16:09:40 +0000 Subject: Sync specialreg.h changes between amd64 and i386 with few fixes. --- sys/amd64/include/specialreg.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'sys/amd64') diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 7adc83d..770535e 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -109,16 +109,18 @@ #define CPUID_SS 0x08000000 #define CPUID_HTT 0x10000000 #define CPUID_TM 0x20000000 -#define CPUID_B30 0x40000000 +#define CPUID_IA64 0x40000000 #define CPUID_PBE 0x80000000 #define CPUID2_SSE3 0x00000001 #define CPUID2_MON 0x00000008 #define CPUID2_DS_CPL 0x00000010 +#define CPUID2_VMX 0x00000020 #define CPUID2_EST 0x00000080 #define CPUID2_TM2 0x00000100 #define CPUID2_CNTXID 0x00000400 #define CPUID2_CX16 0x00002000 +#define CPUID2_XTPR 0x00004000 /* * Important bits in the AMD extended cpuid flags @@ -190,6 +192,7 @@ #define MSR_THERM_CONTROL 0x19a #define MSR_THERM_INTERRUPT 0x19b #define MSR_THERM_STATUS 0x19c +#define MSR_IA32_MISC_ENABLE 0x1a0 #define MSR_DEBUGCTLMSR 0x1d9 #define MSR_LASTBRANCHFROMIP 0x1db #define MSR_LASTBRANCHTOIP 0x1dc @@ -358,7 +361,7 @@ #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ -/* X86-64 MSR's */ +/* AMD64 MSR's */ #define MSR_EFER 0xc0000080 /* extended features */ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ -- cgit v1.1