From bdae65463ea82ed7b759b8281c6380f93c274157 Mon Sep 17 00:00:00 2001 From: neel Date: Tue, 16 Dec 2014 06:33:57 +0000 Subject: For level triggered interrupts clear the PIC IRR bit when the interrupt pin is deasserted. Prior to this change each assertion on a level triggered irq pin resulted in two interrupts being delivered to the CPU. Differential Revision: https://reviews.freebsd.org/D1310 Reviewed by: tychon MFC after: 1 week --- sys/amd64/vmm/io/vatpic.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sys/amd64/vmm') diff --git a/sys/amd64/vmm/io/vatpic.c b/sys/amd64/vmm/io/vatpic.c index 54d8155..deef5a2 100644 --- a/sys/amd64/vmm/io/vatpic.c +++ b/sys/amd64/vmm/io/vatpic.c @@ -388,6 +388,8 @@ vatpic_set_pinstate(struct vatpic *vatpic, int pin, bool newstate) } else if (oldcnt == 1 && newcnt == 0) { /* falling edge */ VATPIC_CTR1(vatpic, "atpic pin%d: deasserted", pin); + if (level) + atpic->request &= ~(1 << (pin & 0x7)); } else { VATPIC_CTR3(vatpic, "atpic pin%d: %s, ignored, acnt %d", pin, newstate ? "asserted" : "deasserted", newcnt); -- cgit v1.1