From 99f1b222339d6eee1c65e04ad1def3c866f155b0 Mon Sep 17 00:00:00 2001 From: nyan Date: Sat, 14 May 2005 09:10:02 +0000 Subject: - Move timerreg.h to /include and split i8253 specific defines into i8253reg.h, and add some defines to control a speaker. - Move PPI related defines from i386/isa/spkr.c into ppireg.h and use them. - Move IO_{PPI,TIMER} defines into ppireg.h and timerreg.h respectively. - Use isa/isareg.h rather than /isa/isa.h. Tested on: i386, pc98 --- sys/amd64/isa/clock.c | 16 ++++----- sys/amd64/isa/isa.h | 3 -- sys/amd64/isa/timerreg.h | 90 ------------------------------------------------ 3 files changed, 8 insertions(+), 101 deletions(-) delete mode 100644 sys/amd64/isa/timerreg.h (limited to 'sys/amd64/isa') diff --git a/sys/amd64/isa/clock.c b/sys/amd64/isa/clock.c index f1f3e942..7e3fd78 100644 --- a/sys/amd64/isa/clock.c +++ b/sys/amd64/isa/clock.c @@ -72,13 +72,14 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include +#include -#include #include #ifdef DEV_ISA +#include #include #endif -#include /* * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we @@ -365,8 +366,8 @@ DELAY(int n) static void sysbeepstop(void *chan) { - outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ - release_timer2(); + ppi_spkr_off(); /* disable counter2 output to speaker */ + timer_spkr_release(); beeping = 0; } @@ -375,19 +376,18 @@ sysbeep(int pitch, int period) { int x = splclock(); - if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) + if (timer_spkr_acquire()) if (!beeping) { /* Something else owns it. */ splx(x); return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ } mtx_lock_spin(&clock_lock); - outb(TIMER_CNTR2, pitch); - outb(TIMER_CNTR2, (pitch>>8)); + spkr_set_pitch(pitch); mtx_unlock_spin(&clock_lock); if (!beeping) { /* enable counter2 output to speaker */ - outb(IO_PPI, inb(IO_PPI) | 3); + ppi_spkr_on(); beeping = period; timeout(sysbeepstop, (void *)NULL, period); } diff --git a/sys/amd64/isa/isa.h b/sys/amd64/isa/isa.h index 4aa42d6..ad6b176 100644 --- a/sys/amd64/isa/isa.h +++ b/sys/amd64/isa/isa.h @@ -52,10 +52,7 @@ #define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ #define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ #define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ -#define IO_TIMER1 0x040 /* 8253 Timer #1 */ -#define IO_TIMER2 0x048 /* 8253 Timer #2 */ #define IO_KBD 0x060 /* 8042 Keyboard */ -#define IO_PPI 0x061 /* Programmable Peripheral Interface */ #define IO_RTC 0x070 /* RTC */ #define IO_NMI IO_RTC /* NMI Control */ #define IO_DMAPG 0x080 /* DMA Page Registers */ diff --git a/sys/amd64/isa/timerreg.h b/sys/amd64/isa/timerreg.h deleted file mode 100644 index b706bd8..0000000 --- a/sys/amd64/isa/timerreg.h +++ /dev/null @@ -1,90 +0,0 @@ -/*- - * Copyright (c) 1993 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp - * $FreeBSD$ - */ - -/* - * - * Register definitions for the Intel 8253 Programmable Interval Timer. - * - * This chip has three independent 16-bit down counters that can be - * read on the fly. There are three mode registers and three countdown - * registers. The countdown registers are addressed directly, via the - * first three I/O ports. The three mode registers are accessed via - * the fourth I/O port, with two bits in the mode byte indicating the - * register. (Why are hardware interfaces always so braindead?). - * - * To write a value into the countdown register, the mode register - * is first programmed with a command indicating the which byte of - * the two byte register is to be modified. The three possibilities - * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then - * msb (TMR_MR_BOTH). - * - * To read the current value ("on the fly") from the countdown register, - * you write a "latch" command into the mode register, then read the stable - * value from the corresponding I/O port. For example, you write - * TMR_MR_LATCH into the corresponding mode register. Presumably, - * after doing this, a write operation to the I/O port would result - * in undefined behavior (but hopefully not fry the chip). - * Reading in this manner has no side effects. - * - * [AMD64] - * The outputs of the three timers are connected as follows: - * - * timer 0 -> irq 0 - * timer 1 -> dma chan 0 (for dram refresh) - * timer 2 -> speaker (via keyboard controller) - * - * Timer 0 is used to call hardclock. - * Timer 2 is used to generate console beeps. - */ - -/* - * Macros for specifying values to be written into a mode register. - */ -#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */ -#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */ -#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */ -#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */ -#define TIMER_SEL0 0x00 /* select counter 0 */ -#define TIMER_SEL1 0x40 /* select counter 1 */ -#define TIMER_SEL2 0x80 /* select counter 2 */ -#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ -#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ -#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ -#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ -#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ -#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ -#define TIMER_LATCH 0x00 /* latch counter for reading */ -#define TIMER_LSB 0x10 /* r/w counter LSB */ -#define TIMER_MSB 0x20 /* r/w counter MSB */ -#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ -#define TIMER_BCD 0x01 /* count in BCD */ - -- cgit v1.1