From 6633d0628b91a64a71e56407ac9accf998056bd2 Mon Sep 17 00:00:00 2001 From: kib Date: Tue, 17 Jan 2012 07:21:23 +0000 Subject: Add macro IS_BSP() to check whether the current CPU is BSP. MFC after: 1 week --- sys/amd64/include/pcpu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/pcpu.h b/sys/amd64/include/pcpu.h index c4b0c44..d07dbac 100644 --- a/sys/amd64/include/pcpu.h +++ b/sys/amd64/include/pcpu.h @@ -226,6 +226,8 @@ __curthread(void) } #define curthread (__curthread()) +#define IS_BSP() (PCPU_GET(cpuid) == 0) + #else /* !lint || defined(__GNUCLIKE_ASM) && defined(__GNUCLIKE___TYPEOF) */ #error "this file needs to be ported to your compiler" -- cgit v1.1 From e94bd75cc576b894958cd5eedcf1d25919af0fd4 Mon Sep 17 00:00:00 2001 From: kib Date: Tue, 17 Jan 2012 07:23:43 +0000 Subject: Add definitions related to XCR0. MFC after: 1 week --- sys/amd64/include/specialreg.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 4c50166..7ba5f9f 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -66,6 +66,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. @@ -76,6 +77,18 @@ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ /* + * Intel Extended Features registers + */ +#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ + +#define XFEATURE_ENABLED_X87 0x00000001 +#define XFEATURE_ENABLED_SSE 0x00000002 +#define XFEATURE_ENABLED_AVX 0x00000004 + +#define XFEATURE_AVX \ + (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) + +/* * CPUID instruction features register */ #define CPUID_FPU 0x00000001 -- cgit v1.1 From 6a34de7c5a0e59d6349ce628792e19d793eeb2b4 Mon Sep 17 00:00:00 2001 From: kib Date: Tue, 17 Jan 2012 07:30:36 +0000 Subject: Implement xsetbv(), xsave() and xrstor() providing C access to the similarly named CPU instructions. Since our in-tree binutils gas is not aware of the instructions, and I have to use the byte-sequence to encode them, hardcode the r/m operand as (%rdi). This way, first argument of the pseudo-function is already placed into proper register. MFC after: 1 week --- sys/amd64/include/cpufunc.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h index c07e09b..9b147c7 100644 --- a/sys/amd64/include/cpufunc.h +++ b/sys/amd64/include/cpufunc.h @@ -669,6 +669,41 @@ intr_restore(register_t rflags) write_rflags(rflags); } +static __inline void +xsetbv(uint32_t reg, uint64_t val) +{ + uint32_t low, hi; + + low = val; + hi = val >> 32; + __asm __volatile(".byte 0x0f,0x01,0xd1" : : + "c" (reg), "a" (low), "d" (hi)); +} + +static __inline void +xsave(char *addr, uint64_t mask) +{ + uint32_t low, hi; + + low = mask; + hi = mask >> 32; + /* xsave (%rdi) */ + __asm __volatile(".byte 0x0f,0xae,0x27" : : + "a" (low), "d" (hi), "D" (addr) : "memory"); +} + +static __inline void +xrstor(char *addr, uint64_t mask) +{ + uint32_t low, hi; + + low = mask; + hi = mask >> 32; + /* xrstor (%rdi) */ + __asm __volatile(".byte 0x0f,0xae,0x2f" : : + "a" (low), "d" (hi), "D" (addr)); +} + #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ int breakpoint(void); @@ -733,6 +768,9 @@ u_int rgs(void); void wbinvd(void); void write_rflags(u_int rf); void wrmsr(u_int msr, uint64_t newval); +void xsetbv(uint32_t reg, uint64_t val); +void xsave(char *addr, uint64_t mask); +void xrstor(char *addr, uint64_t mask); #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ -- cgit v1.1 From 8999bd2861cb515c00c0dd3f8273f7e761e0bce4 Mon Sep 17 00:00:00 2001 From: kib Date: Tue, 17 Jan 2012 16:53:41 +0000 Subject: Modernize the fpusave structures definitions by using uint*_t types. MFC after: 1 week --- sys/amd64/include/fpu.h | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/fpu.h b/sys/amd64/include/fpu.h index 50b3819..cef2108 100644 --- a/sys/amd64/include/fpu.h +++ b/sys/amd64/include/fpu.h @@ -43,34 +43,39 @@ /* Contents of each x87 floating point accumulator */ struct fpacc87 { - u_char fp_bytes[10]; + uint8_t fp_bytes[10]; }; /* Contents of each SSE extended accumulator */ struct xmmacc { - u_char xmm_bytes[16]; + uint8_t xmm_bytes[16]; +}; + +/* Contents of the upper 16 bytes of each AVX extended accumulator */ +struct ymmacc { + uint8_t ymm_bytes[16]; }; struct envxmm { - u_int16_t en_cw; /* control word (16bits) */ - u_int16_t en_sw; /* status word (16bits) */ - u_int8_t en_tw; /* tag word (8bits) */ - u_int8_t en_zero; - u_int16_t en_opcode; /* opcode last executed (11 bits ) */ - u_int64_t en_rip; /* floating point instruction pointer */ - u_int64_t en_rdp; /* floating operand pointer */ - u_int32_t en_mxcsr; /* SSE sontorol/status register */ - u_int32_t en_mxcsr_mask; /* valid bits in mxcsr */ + uint16_t en_cw; /* control word (16bits) */ + uint16_t en_sw; /* status word (16bits) */ + uint8_t en_tw; /* tag word (8bits) */ + uint8_t en_zero; + uint16_t en_opcode; /* opcode last executed (11 bits ) */ + uint64_t en_rip; /* floating point instruction pointer */ + uint64_t en_rdp; /* floating operand pointer */ + uint32_t en_mxcsr; /* SSE sontorol/status register */ + uint32_t en_mxcsr_mask; /* valid bits in mxcsr */ }; struct savefpu { struct envxmm sv_env; struct { struct fpacc87 fp_acc; - u_char fp_pad[6]; /* padding */ + uint8_t fp_pad[6]; /* padding */ } sv_fp[8]; struct xmmacc sv_xmm[16]; - u_char sv_pad[96]; + uint8_t sv_pad[96]; } __aligned(16); #ifdef _KERNEL -- cgit v1.1 From 69f3e63a09d0bf9cf5040a94480ab69a27962f72 Mon Sep 17 00:00:00 2001 From: kib Date: Tue, 17 Jan 2012 17:07:13 +0000 Subject: Add definitions for the FPU extended state header, legacy extended state and AVX state. MFC after: 1 week --- sys/amd64/include/fpu.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/fpu.h b/sys/amd64/include/fpu.h index cef2108..1e7103e 100644 --- a/sys/amd64/include/fpu.h +++ b/sys/amd64/include/fpu.h @@ -78,6 +78,28 @@ struct savefpu { uint8_t sv_pad[96]; } __aligned(16); +struct xstate_hdr { + uint64_t xstate_bv; + uint8_t xstate_rsrv0[16]; + uint8_t xstate_rsrv[40]; +}; + +struct savefpu_xstate { + struct xstate_hdr sx_hd; + struct ymmacc sx_ymm[16]; +}; + +struct savefpu_ymm { + struct envxmm sv_env; + struct { + struct fpacc87 fp_acc; + int8_t fp_pad[6]; /* padding */ + } sv_fp[8]; + struct xmmacc sv_xmm[16]; + uint8_t sv_pad[96]; + struct savefpu_xstate sv_xstate; +} __aligned(64); + #ifdef _KERNEL struct fpu_kern_ctx { struct savefpu hwstate; -- cgit v1.1 From 361bfae5c2c758540993427b5fd4d32422b143d4 Mon Sep 17 00:00:00 2001 From: kib Date: Sat, 21 Jan 2012 17:45:27 +0000 Subject: Add support for the extended FPU states on amd64, both for native 64bit and 32bit ABIs. As a side-effect, it enables AVX on capable CPUs. In particular: - Query the CPU support for XSAVE, list of the supported extensions and the required size of FPU save area. The hw.use_xsave tunable is provided for disabling XSAVE, and hw.xsave_mask may be used to select the enabled extensions. - Remove the FPU save area from PCB and dynamically allocate the (run-time sized) user save area on the top of the kernel stack, right above the PCB. Reorganize the thread0 PCB initialization to postpone it after BSP is queried for save area size. - The dumppcb, stoppcbs and susppcbs now do not carry the FPU state as well. FPU state is only useful for suspend, where it is saved in dynamically allocated suspfpusave area. - Use XSAVE and XRSTOR to save/restore FPU state, if supported and enabled. - Define new mcontext_t flag _MC_HASFPXSTATE, indicating that mcontext_t has a valid pointer to out-of-struct extended FPU state. Signal handlers are supplied with stack-allocated fpu state. The sigreturn(2) and setcontext(2) syscall honour the flag, allowing the signal handlers to inspect and manipilate extended state in the interrupted context. - The getcontext(2) never returns extended state, since there is no place in the fixed-sized mcontext_t to place variable-sized save area. And, since mcontext_t is embedded into ucontext_t, makes it impossible to fix in a reasonable way. Instead of extending getcontext(2) syscall, provide a sysarch(2) facility to query extended FPU state. - Add ptrace(2) support for getting and setting extended state; while there, implement missed PT_I386_{GET,SET}XMMREGS for 32bit binaries. - Change fpu_kern KPI to not expose struct fpu_kern_ctx layout to consumers, making it opaque. Internally, struct fpu_kern_ctx now contains a space for the extended state. Convert in-kernel consumers of fpu_kern KPI both on i386 and amd64. First version of the support for AVX was submitted by Tim Bird on behalf of Sony. This version was written from scratch. Tested by: pho (previous version), Yamagi Burmeister MFC after: 1 month --- sys/amd64/include/fpu.h | 22 ++++++++++++++-------- sys/amd64/include/frame.h | 3 ++- sys/amd64/include/md_var.h | 10 ++++++++++ sys/amd64/include/pcb.h | 4 +++- sys/amd64/include/ptrace.h | 5 +++++ sys/amd64/include/sysarch.h | 12 ++++++++++++ sys/amd64/include/ucontext.h | 8 ++++++-- 7 files changed, 52 insertions(+), 12 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/fpu.h b/sys/amd64/include/fpu.h index 1e7103e..d208789 100644 --- a/sys/amd64/include/fpu.h +++ b/sys/amd64/include/fpu.h @@ -101,14 +101,13 @@ struct savefpu_ymm { } __aligned(64); #ifdef _KERNEL -struct fpu_kern_ctx { - struct savefpu hwstate; - struct savefpu *prev; - uint32_t flags; -}; -#define FPU_KERN_CTX_FPUINITDONE 0x01 + +struct fpu_kern_ctx; #define PCB_USER_FPU(pcb) (((pcb)->pcb_flags & PCB_KERNFPU) == 0) + +#define XSAVE_AREA_ALIGN 64 + #endif /* @@ -141,9 +140,15 @@ void fpuexit(struct thread *td); int fpuformat(void); int fpugetregs(struct thread *td); void fpuinit(void); -void fpusetregs(struct thread *td, struct savefpu *addr); +void fpusave(void *addr); +int fpusetregs(struct thread *td, struct savefpu *addr, + char *xfpustate, size_t xfpustate_size); +int fpusetxstate(struct thread *td, char *xfpustate, + size_t xfpustate_size); int fputrap(void); void fpuuserinited(struct thread *td); +struct fpu_kern_ctx *fpu_kern_alloc_ctx(u_int flags); +void fpu_kern_free_ctx(struct fpu_kern_ctx *ctx); int fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags); int fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx); @@ -151,9 +156,10 @@ int fpu_kern_thread(u_int flags); int is_fpu_kern_thread(u_int flags); /* - * Flags for fpu_kern_enter() and fpu_kern_thread(). + * Flags for fpu_kern_alloc_ctx(), fpu_kern_enter() and fpu_kern_thread(). */ #define FPU_KERN_NORMAL 0x0000 +#define FPU_KERN_NOWAIT 0x0001 #endif diff --git a/sys/amd64/include/frame.h b/sys/amd64/include/frame.h index 12722a4..e171407 100644 --- a/sys/amd64/include/frame.h +++ b/sys/amd64/include/frame.h @@ -81,6 +81,7 @@ struct trapframe { }; #define TF_HASSEGS 0x1 -/* #define _MC_HASBASES 0x2 */ +#define TF_HASBASES 0x2 +#define TF_HASFPXSTATE 0x4 #endif /* _MACHINE_FRAME_H_ */ diff --git a/sys/amd64/include/md_var.h b/sys/amd64/include/md_var.h index 479c84e..ff11ea1 100644 --- a/sys/amd64/include/md_var.h +++ b/sys/amd64/include/md_var.h @@ -51,6 +51,7 @@ extern u_int cpu_clflush_line_size; extern u_int cpu_fxsr; extern u_int cpu_high; extern u_int cpu_id; +extern u_int cpu_max_ext_state_size; extern u_int cpu_mxcsr_mask; extern u_int cpu_procinfo; extern u_int cpu_procinfo2; @@ -67,17 +68,23 @@ extern int _ucodesel; extern int _ucode32sel; extern int _ufssel; extern int _ugssel; +extern int use_xsave; +extern uint64_t xsave_mask; typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); +struct pcb; +struct savefpu; struct thread; struct reg; struct fpreg; struct dbreg; struct dumperinfo; +void *alloc_fpusave(int flags); void amd64_syscall(struct thread *td, int traced); void busdma_swi(void); void cpu_setregs(void); +void ctx_fpusave(void *); void doreti_iret(void) __asm(__STRING(doreti_iret)); void doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault)); void ld_ds(void) __asm(__STRING(ld_ds)); @@ -105,5 +112,8 @@ void pagezero(void *addr); void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int ist); int user_dbreg_trap(void); void minidumpsys(struct dumperinfo *); +struct savefpu *get_pcb_user_save_td(struct thread *td); +struct savefpu *get_pcb_user_save_pcb(struct pcb *pcb); +struct pcb *get_pcb_td(struct thread *td); #endif /* !_MACHINE_MD_VAR_H_ */ diff --git a/sys/amd64/include/pcb.h b/sys/amd64/include/pcb.h index 1af8f6d..61f651bb 100644 --- a/sys/amd64/include/pcb.h +++ b/sys/amd64/include/pcb.h @@ -92,7 +92,8 @@ struct pcb { struct amd64tss *pcb_tssp; struct savefpu *pcb_save; - struct savefpu pcb_user_save; + + uint64_t pcb_pad[2]; }; #ifdef _KERNEL @@ -130,6 +131,7 @@ clear_pcb_flags(struct pcb *pcb, const u_int flags) void makectx(struct trapframe *, struct pcb *); int savectx(struct pcb *); + #endif #endif /* _AMD64_PCB_H_ */ diff --git a/sys/amd64/include/ptrace.h b/sys/amd64/include/ptrace.h index eef24f8..28f94f7 100644 --- a/sys/amd64/include/ptrace.h +++ b/sys/amd64/include/ptrace.h @@ -33,4 +33,9 @@ #ifndef _MACHINE_PTRACE_H_ #define _MACHINE_PTRACE_H_ +#define __HAVE_PTRACE_MACHDEP + +#define PT_GETXSTATE (PT_FIRSTMACH + 0) +#define PT_SETXSTATE (PT_FIRSTMACH + 1) + #endif diff --git a/sys/amd64/include/sysarch.h b/sys/amd64/include/sysarch.h index 7b95a8b..195d882 100644 --- a/sys/amd64/include/sysarch.h +++ b/sys/amd64/include/sysarch.h @@ -50,12 +50,14 @@ #define I386_SET_FSBASE 8 #define I386_GET_GSBASE 9 #define I386_SET_GSBASE 10 +#define I386_GET_XFPUSTATE 11 /* Leave space for 0-127 for to avoid translating syscalls */ #define AMD64_GET_FSBASE 128 #define AMD64_SET_FSBASE 129 #define AMD64_GET_GSBASE 130 #define AMD64_SET_GSBASE 131 +#define AMD64_GET_XFPUSTATE 132 struct i386_ldt_args { unsigned int start; @@ -69,6 +71,16 @@ struct i386_ioperm_args { int enable; }; +struct i386_get_xfpustate { + unsigned int addr; + int len; +}; + +struct amd64_get_xfpustate { + void *addr; + int len; +}; + #ifndef _KERNEL __BEGIN_DECLS int amd64_get_fsbase(void **); diff --git a/sys/amd64/include/ucontext.h b/sys/amd64/include/ucontext.h index 75b7bd2..5ab841e 100644 --- a/sys/amd64/include/ucontext.h +++ b/sys/amd64/include/ucontext.h @@ -37,7 +37,8 @@ */ #define _MC_HASSEGS 0x1 #define _MC_HASBASES 0x2 -#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES) +#define _MC_HASFPXSTATE 0x4 +#define _MC_FLAG_MASK (_MC_HASSEGS | _MC_HASBASES | _MC_HASFPXSTATE) typedef struct __mcontext { /* @@ -93,7 +94,10 @@ typedef struct __mcontext { __register_t mc_fsbase; __register_t mc_gsbase; - long mc_spare[6]; + __register_t mc_xfpustate; + __register_t mc_xfpustate_len; + + long mc_spare[4]; } mcontext_t; #endif /* !_MACHINE_UCONTEXT_H_ */ -- cgit v1.1 From 9feb719605e703444f28b933c01a8a42ed35a2b0 Mon Sep 17 00:00:00 2001 From: das Date: Mon, 23 Jan 2012 06:36:41 +0000 Subject: Add C11 macros describing subnormal numbers to float.h. Reviewed by: bde --- sys/amd64/include/float.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/float.h b/sys/amd64/include/float.h index 8f0d713..00ed6e2 100644 --- a/sys/amd64/include/float.h +++ b/sys/amd64/include/float.h @@ -55,6 +55,11 @@ __END_DECLS #define FLT_MAX_EXP 128 /* emax */ #define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ #define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ #define DBL_MANT_DIG 53 #define DBL_EPSILON 2.2204460492503131E-16 @@ -65,6 +70,11 @@ __END_DECLS #define DBL_MAX_EXP 1024 #define DBL_MAX 1.7976931348623157E+308 #define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ #define LDBL_MANT_DIG 64 #define LDBL_EPSILON 1.0842021724855044340E-19L @@ -75,4 +85,10 @@ __END_DECLS #define LDBL_MAX_EXP 16384 #define LDBL_MAX 1.1897314953572317650E+4932L #define LDBL_MAX_10_EXP 4932 +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN 3.6451995318824746025E-4951L +#define LDBL_DECIMAL_DIG 21 +#define LDBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + #endif /* _MACHINE_FLOAT_H_ */ -- cgit v1.1 From dbd94fb4b8925880c1e2cefc7dfd8d653c627fa3 Mon Sep 17 00:00:00 2001 From: kib Date: Wed, 25 Jan 2012 12:43:27 +0000 Subject: Order newly added functions alphabetically. Requested by: bde MFC after: 3 days --- sys/amd64/include/cpufunc.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h index 9b147c7..d112e66 100644 --- a/sys/amd64/include/cpufunc.h +++ b/sys/amd64/include/cpufunc.h @@ -670,17 +670,6 @@ intr_restore(register_t rflags) } static __inline void -xsetbv(uint32_t reg, uint64_t val) -{ - uint32_t low, hi; - - low = val; - hi = val >> 32; - __asm __volatile(".byte 0x0f,0x01,0xd1" : : - "c" (reg), "a" (low), "d" (hi)); -} - -static __inline void xsave(char *addr, uint64_t mask) { uint32_t low, hi; @@ -693,6 +682,17 @@ xsave(char *addr, uint64_t mask) } static __inline void +xsetbv(uint32_t reg, uint64_t val) +{ + uint32_t low, hi; + + low = val; + hi = val >> 32; + __asm __volatile(".byte 0x0f,0x01,0xd1" : : + "c" (reg), "a" (low), "d" (hi)); +} + +static __inline void xrstor(char *addr, uint64_t mask) { uint32_t low, hi; @@ -768,8 +768,8 @@ u_int rgs(void); void wbinvd(void); void write_rflags(u_int rf); void wrmsr(u_int msr, uint64_t newval); -void xsetbv(uint32_t reg, uint64_t val); void xsave(char *addr, uint64_t mask); +void xsetbv(uint32_t reg, uint64_t val); void xrstor(char *addr, uint64_t mask); #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ -- cgit v1.1 From 82e1b5ac867860ddecd754a27c6cd091f40baa9e Mon Sep 17 00:00:00 2001 From: kib Date: Mon, 30 Jan 2012 07:51:52 +0000 Subject: Synchronize the struct sigcontext definitions on x86 with mcontext_t. Pointed out by: bde MFC after: 1 month --- sys/amd64/include/signal.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/signal.h b/sys/amd64/include/signal.h index 0374339..085d43a 100644 --- a/sys/amd64/include/signal.h +++ b/sys/amd64/include/signal.h @@ -99,7 +99,10 @@ struct sigcontext { long sc_fsbase; long sc_gsbase; - long sc_spare[6]; + long sc_xfpustate; + long sc_xfpustate_len; + + long sc_spare[4]; }; #endif /* __BSD_VISIBLE */ -- cgit v1.1 From a39b6a3bffcf6cca87ef96f29c24d81e39d0fa2d Mon Sep 17 00:00:00 2001 From: kib Date: Mon, 30 Jan 2012 07:53:33 +0000 Subject: Move xrstor/xsave/xsetbv into fpu.c and reorder them. Requested by: bde MFC after: 1 month --- sys/amd64/include/cpufunc.h | 38 -------------------------------------- 1 file changed, 38 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h index d112e66..c07e09b 100644 --- a/sys/amd64/include/cpufunc.h +++ b/sys/amd64/include/cpufunc.h @@ -669,41 +669,6 @@ intr_restore(register_t rflags) write_rflags(rflags); } -static __inline void -xsave(char *addr, uint64_t mask) -{ - uint32_t low, hi; - - low = mask; - hi = mask >> 32; - /* xsave (%rdi) */ - __asm __volatile(".byte 0x0f,0xae,0x27" : : - "a" (low), "d" (hi), "D" (addr) : "memory"); -} - -static __inline void -xsetbv(uint32_t reg, uint64_t val) -{ - uint32_t low, hi; - - low = val; - hi = val >> 32; - __asm __volatile(".byte 0x0f,0x01,0xd1" : : - "c" (reg), "a" (low), "d" (hi)); -} - -static __inline void -xrstor(char *addr, uint64_t mask) -{ - uint32_t low, hi; - - low = mask; - hi = mask >> 32; - /* xrstor (%rdi) */ - __asm __volatile(".byte 0x0f,0xae,0x2f" : : - "a" (low), "d" (hi), "D" (addr)); -} - #else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */ int breakpoint(void); @@ -768,9 +733,6 @@ u_int rgs(void); void wbinvd(void); void write_rflags(u_int rf); void wrmsr(u_int msr, uint64_t newval); -void xsave(char *addr, uint64_t mask); -void xsetbv(uint32_t reg, uint64_t val); -void xrstor(char *addr, uint64_t mask); #endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */ -- cgit v1.1 From f436893eac090f2bde9fb877fcec9890a7b6e359 Mon Sep 17 00:00:00 2001 From: jhb Date: Mon, 27 Feb 2012 17:28:47 +0000 Subject: Correct function prototype for read_rflags(). --- sys/amd64/include/cpufunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h index c07e09b..9440694 100644 --- a/sys/amd64/include/cpufunc.h +++ b/sys/amd64/include/cpufunc.h @@ -727,7 +727,7 @@ uint64_t rdr5(void); uint64_t rdr6(void); uint64_t rdr7(void); uint64_t rdtsc(void); -u_int read_rflags(void); +u_long read_rflags(void); u_int rfs(void); u_int rgs(void); void wbinvd(void); -- cgit v1.1 From 8e4f58c4d2f60566a324371354ae598327815115 Mon Sep 17 00:00:00 2001 From: jhb Date: Mon, 27 Feb 2012 17:29:37 +0000 Subject: Resort the IDT_DTRACE_RET constant after it was changed to be less than IDT_SYSCALL. --- sys/amd64/include/segments.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/segments.h b/sys/amd64/include/segments.h index 2796511..247cc34 100644 --- a/sys/amd64/include/segments.h +++ b/sys/amd64/include/segments.h @@ -213,8 +213,8 @@ struct region_descriptor { #define IDT_MC 18 /* #MC: Machine Check */ #define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */ #define IDT_IO_INTS NRSVIDT /* Base of IDT entries for I/O interrupts. */ -#define IDT_SYSCALL 0x80 /* System Call Interrupt Vector */ #define IDT_DTRACE_RET 0x20 /* DTrace pid provider Interrupt Vector */ +#define IDT_SYSCALL 0x80 /* System Call Interrupt Vector */ /* * Entries in the Global Descriptor Table (GDT) -- cgit v1.1 From 3b29ed2286b5864c63a73515a0a5ec9ed14c7bd5 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 18:15:28 +0000 Subject: Copy amd64 _types.h to x86 and merge with i386 _types.h. Replace existing amd64/i386/pc98 _types.h with stubs. --- sys/amd64/include/_types.h | 116 ++------------------------------------------- 1 file changed, 3 insertions(+), 113 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/_types.h b/sys/amd64/include/_types.h index 99db9b0..2680367 100644 --- a/sys/amd64/include/_types.h +++ b/sys/amd64/include/_types.h @@ -1,116 +1,6 @@ /*- - * Copyright (c) 2002 Mike Barcroft - * Copyright (c) 1990, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 - * From: @(#)types.h 8.3 (Berkeley) 1/5/94 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE__TYPES_H_ -#define _MACHINE__TYPES_H_ - -#ifndef _SYS_CDEFS_H_ -#error this file needs sys/cdefs.h as a prerequisite -#endif - -#define __NO_STRICT_ALIGNMENT - -/* - * Basic types upon which most other types are built. - */ -typedef signed char __int8_t; -typedef unsigned char __uint8_t; -typedef short __int16_t; -typedef unsigned short __uint16_t; -typedef int __int32_t; -typedef unsigned int __uint32_t; -typedef long __int64_t; -typedef unsigned long __uint64_t; - -/* - * Standard type definitions. - */ -typedef __int32_t __clock_t; /* clock()... */ -typedef __int64_t __critical_t; -typedef double __double_t; -typedef float __float_t; -typedef __int64_t __intfptr_t; -typedef __int64_t __intmax_t; -typedef __int64_t __intptr_t; -typedef __int32_t __int_fast8_t; -typedef __int32_t __int_fast16_t; -typedef __int32_t __int_fast32_t; -typedef __int64_t __int_fast64_t; -typedef __int8_t __int_least8_t; -typedef __int16_t __int_least16_t; -typedef __int32_t __int_least32_t; -typedef __int64_t __int_least64_t; -typedef __int64_t __ptrdiff_t; /* ptr1 - ptr2 */ -typedef __int64_t __register_t; -typedef __int64_t __segsz_t; /* segment size (in pages) */ -typedef __uint64_t __size_t; /* sizeof() */ -typedef __int64_t __ssize_t; /* byte count or error */ -typedef __int64_t __time_t; /* time()... */ -typedef __uint64_t __uintfptr_t; -typedef __uint64_t __uintmax_t; -typedef __uint64_t __uintptr_t; -typedef __uint32_t __uint_fast8_t; -typedef __uint32_t __uint_fast16_t; -typedef __uint32_t __uint_fast32_t; -typedef __uint64_t __uint_fast64_t; -typedef __uint8_t __uint_least8_t; -typedef __uint16_t __uint_least16_t; -typedef __uint32_t __uint_least32_t; -typedef __uint64_t __uint_least64_t; -typedef __uint64_t __u_register_t; -typedef __uint64_t __vm_offset_t; -typedef __int64_t __vm_ooffset_t; -typedef __uint64_t __vm_paddr_t; -typedef __uint64_t __vm_pindex_t; -typedef __uint64_t __vm_size_t; - -/* - * Unusual type definitions. - */ -#ifdef __GNUCLIKE_BUILTIN_VARARGS -typedef __builtin_va_list __va_list; /* internally known to gcc */ -#elif defined(lint) -typedef char * __va_list; /* pretend */ -#endif -#if defined(__GNUC_VA_LIST_COMPATIBILITY) && !defined(__GNUC_VA_LIST) \ - && !defined(__NO_GNUC_VA_LIST) -#define __GNUC_VA_LIST -typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ -#endif - -#endif /* !_MACHINE__TYPES_H_ */ +#include -- cgit v1.1 From 86b4719ed57cc44687bc6f6b1ea3786dce60a2d1 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 18:24:28 +0000 Subject: Copy amd64 _limits.h to x86 and merge with i386 _limits.h. Replace amd64/i386/pc98 _limits.h with stubs. --- sys/amd64/include/_limits.h | 87 ++------------------------------------------- 1 file changed, 3 insertions(+), 84 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/_limits.h b/sys/amd64/include/_limits.h index 2f3352b..3c7365b 100644 --- a/sys/amd64/include/_limits.h +++ b/sys/amd64/include/_limits.h @@ -1,87 +1,6 @@ /*- - * Copyright (c) 1988, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)limits.h 8.3 (Berkeley) 1/4/94 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE__LIMITS_H_ -#define _MACHINE__LIMITS_H_ - -/* - * According to ANSI (section 2.2.4.2), the values below must be usable by - * #if preprocessing directives. Additionally, the expression must have the - * same type as would an expression that is an object of the corresponding - * type converted according to the integral promotions. The subtraction for - * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an - * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). - */ - -#define __CHAR_BIT 8 /* number of bits in a char */ - -#define __SCHAR_MAX 0x7f /* max value for a signed char */ -#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */ - -#define __UCHAR_MAX 0xff /* max value for an unsigned char */ - -#define __USHRT_MAX 0xffff /* max value for an unsigned short */ -#define __SHRT_MAX 0x7fff /* max value for a short */ -#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */ - -#define __UINT_MAX 0xffffffff /* max value for an unsigned int */ -#define __INT_MAX 0x7fffffff /* max value for an int */ -#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */ - -#define __ULONG_MAX 0xffffffffffffffff /* max for an unsigned long */ -#define __LONG_MAX 0x7fffffffffffffff /* max for a long */ -#define __LONG_MIN (-0x7fffffffffffffff - 1) /* min for a long */ - - /* max value for an unsigned long long */ -#define __ULLONG_MAX 0xffffffffffffffffULL -#define __LLONG_MAX 0x7fffffffffffffffLL /* max value for a long long */ -#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */ - -#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ - -#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ - -#define __OFF_MAX __LONG_MAX /* max value for an off_t */ -#define __OFF_MIN __LONG_MIN /* min value for an off_t */ - -/* Quads and longs are the same on the amd64. Ensure they stay in sync. */ -#define __UQUAD_MAX __ULONG_MAX /* max value for a uquad_t */ -#define __QUAD_MAX __LONG_MAX /* max value for a quad_t */ -#define __QUAD_MIN __LONG_MIN /* min value for a quad_t */ - -#define __LONG_BIT 64 -#define __WORD_BIT 32 - -/* Minimum signal stack size. */ -#define __MINSIGSTKSZ (512 * 4) - -#endif /* !_MACHINE__LIMITS_H_ */ +#include -- cgit v1.1 From 738f5859fbaedfa052e9d809ac04a31d3dcd9ab5 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 18:38:33 +0000 Subject: Copy amd64 _stdint.h to x86 and merge with i386 _stdint.h. Replace amd64/i386/pc98 _stdint.h with stubs. --- sys/amd64/include/_stdint.h | 171 +------------------------------------------- 1 file changed, 3 insertions(+), 168 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/_stdint.h b/sys/amd64/include/_stdint.h index d755bb3..db1affc 100644 --- a/sys/amd64/include/_stdint.h +++ b/sys/amd64/include/_stdint.h @@ -1,171 +1,6 @@ /*- - * Copyright (c) 2001, 2002 Mike Barcroft - * Copyright (c) 2001 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Klaus Klein. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE__STDINT_H_ -#define _MACHINE__STDINT_H_ - -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) - -#define INT8_C(c) (c) -#define INT16_C(c) (c) -#define INT32_C(c) (c) -#define INT64_C(c) (c ## L) - -#define UINT8_C(c) (c) -#define UINT16_C(c) (c) -#define UINT32_C(c) (c ## U) -#define UINT64_C(c) (c ## UL) - -#define INTMAX_C(c) INT64_C(c) -#define UINTMAX_C(c) UINT64_C(c) - -#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) - -/* - * ISO/IEC 9899:1999 - * 7.18.2.1 Limits of exact-width integer types - */ -/* Minimum values of exact-width signed integer types. */ -#define INT8_MIN (-0x7f-1) -#define INT16_MIN (-0x7fff-1) -#define INT32_MIN (-0x7fffffff-1) -#define INT64_MIN (-0x7fffffffffffffffL-1) - -/* Maximum values of exact-width signed integer types. */ -#define INT8_MAX 0x7f -#define INT16_MAX 0x7fff -#define INT32_MAX 0x7fffffff -#define INT64_MAX 0x7fffffffffffffffL - -/* Maximum values of exact-width unsigned integer types. */ -#define UINT8_MAX 0xff -#define UINT16_MAX 0xffff -#define UINT32_MAX 0xffffffffU -#define UINT64_MAX 0xffffffffffffffffUL - -/* - * ISO/IEC 9899:1999 - * 7.18.2.2 Limits of minimum-width integer types - */ -/* Minimum values of minimum-width signed integer types. */ -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST64_MIN INT64_MIN - -/* Maximum values of minimum-width signed integer types. */ -#define INT_LEAST8_MAX INT8_MAX -#define INT_LEAST16_MAX INT16_MAX -#define INT_LEAST32_MAX INT32_MAX -#define INT_LEAST64_MAX INT64_MAX - -/* Maximum values of minimum-width unsigned integer types. */ -#define UINT_LEAST8_MAX UINT8_MAX -#define UINT_LEAST16_MAX UINT16_MAX -#define UINT_LEAST32_MAX UINT32_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -/* - * ISO/IEC 9899:1999 - * 7.18.2.3 Limits of fastest minimum-width integer types - */ -/* Minimum values of fastest minimum-width signed integer types. */ -#define INT_FAST8_MIN INT32_MIN -#define INT_FAST16_MIN INT32_MIN -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST64_MIN INT64_MIN - -/* Maximum values of fastest minimum-width signed integer types. */ -#define INT_FAST8_MAX INT32_MAX -#define INT_FAST16_MAX INT32_MAX -#define INT_FAST32_MAX INT32_MAX -#define INT_FAST64_MAX INT64_MAX - -/* Maximum values of fastest minimum-width unsigned integer types. */ -#define UINT_FAST8_MAX UINT32_MAX -#define UINT_FAST16_MAX UINT32_MAX -#define UINT_FAST32_MAX UINT32_MAX -#define UINT_FAST64_MAX UINT64_MAX - -/* - * ISO/IEC 9899:1999 - * 7.18.2.4 Limits of integer types capable of holding object pointers - */ -#define INTPTR_MIN INT64_MIN -#define INTPTR_MAX INT64_MAX -#define UINTPTR_MAX UINT64_MAX - -/* - * ISO/IEC 9899:1999 - * 7.18.2.5 Limits of greatest-width integer types - */ -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -/* - * ISO/IEC 9899:1999 - * 7.18.3 Limits of other integer types - */ -/* Limits of ptrdiff_t. */ -#define PTRDIFF_MIN INT64_MIN -#define PTRDIFF_MAX INT64_MAX - -/* Limits of sig_atomic_t. */ -#define SIG_ATOMIC_MIN LONG_MIN -#define SIG_ATOMIC_MAX LONG_MAX - -/* Limit of size_t. */ -#define SIZE_MAX UINT64_MAX - -#ifndef WCHAR_MIN /* Also possibly defined in */ -/* Limits of wchar_t. */ -#define WCHAR_MIN INT32_MIN -#define WCHAR_MAX INT32_MAX -#endif - -/* Limits of wint_t. */ -#define WINT_MIN INT32_MIN -#define WINT_MAX INT32_MAX - -#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ - -#endif /* !_MACHINE__STDINT_H_ */ +#include -- cgit v1.1 From bfd7a07500d59035447033f67bf7408d4150ce05 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 19:39:54 +0000 Subject: Copy amd64 endian.h to x86 and merge with i386 endian.h. Replace amd64/i386/pc98 endian.h with stubs. In __bswap64_const(x) the conflict between 0xffUL and 0xffULL has been resolved by reimplementing the macro in terms of __bswap32(x). As a side effect __bswap64_var(x) is now implemented using two bswap instructions on i386 and should be much faster. __bswap32_const(x) has been reimplemented in terms of __bswap16(x) for consistency. --- sys/amd64/include/endian.h | 145 +-------------------------------------------- 1 file changed, 3 insertions(+), 142 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/endian.h b/sys/amd64/include/endian.h index de22c8b..2ad27a9 100644 --- a/sys/amd64/include/endian.h +++ b/sys/amd64/include/endian.h @@ -1,145 +1,6 @@ /*- - * Copyright (c) 1987, 1991 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)endian.h 7.8 (Berkeley) 4/3/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_ENDIAN_H_ -#define _MACHINE_ENDIAN_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Define the order of 32-bit words in 64-bit words. - */ -#define _QUAD_HIGHWORD 1 -#define _QUAD_LOWWORD 0 - -/* - * Definitions for byte order, according to byte significance from low - * address to high. - */ -#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ -#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ -#define _PDP_ENDIAN 3412 /* LSB first in word, MSW first in long */ - -#define _BYTE_ORDER _LITTLE_ENDIAN - -/* - * Deprecated variants that don't have enough underscores to be useful in more - * strict namespaces. - */ -#if __BSD_VISIBLE -#define LITTLE_ENDIAN _LITTLE_ENDIAN -#define BIG_ENDIAN _BIG_ENDIAN -#define PDP_ENDIAN _PDP_ENDIAN -#define BYTE_ORDER _BYTE_ORDER -#endif - -#if defined(__GNUCLIKE_ASM) && defined(__GNUCLIKE_BUILTIN_CONSTANT_P) - -#define __bswap64_const(_x) \ - (((_x) >> 56) | \ - (((_x) >> 40) & (0xffUL << 8)) | \ - (((_x) >> 24) & (0xffUL << 16)) | \ - (((_x) >> 8) & (0xffUL << 24)) | \ - (((_x) << 8) & (0xffUL << 32)) | \ - (((_x) << 24) & (0xffUL << 40)) | \ - (((_x) << 40) & (0xffUL << 48)) | \ - ((_x) << 56)) - -#define __bswap32_const(_x) \ - (((_x) >> 24) | \ - (((_x) & (0xff << 16)) >> 8) | \ - (((_x) & (0xff << 8)) << 8) | \ - ((_x) << 24)) - -#define __bswap16_const(_x) (__uint16_t)((_x) << 8 | (_x) >> 8) - -static __inline __uint64_t -__bswap64_var(__uint64_t _x) -{ - - __asm ("bswap %0" : "+r" (_x)); - return (_x); -} - -static __inline __uint32_t -__bswap32_var(__uint32_t _x) -{ - - __asm ("bswap %0" : "+r" (_x)); - return (_x); -} - -static __inline __uint16_t -__bswap16_var(__uint16_t _x) -{ - - return (__bswap16_const(_x)); -} - -#define __bswap64(_x) \ - (__builtin_constant_p(_x) ? \ - __bswap64_const((__uint64_t)(_x)) : __bswap64_var(_x)) - -#define __bswap32(_x) \ - (__builtin_constant_p(_x) ? \ - __bswap32_const((__uint32_t)(_x)) : __bswap32_var(_x)) - -#define __bswap16(_x) \ - (__builtin_constant_p(_x) ? \ - __bswap16_const((__uint16_t)(_x)) : __bswap16_var(_x)) - -#define __htonl(x) __bswap32(x) -#define __htons(x) __bswap16(x) -#define __ntohl(x) __bswap32(x) -#define __ntohs(x) __bswap16(x) - -#else /* !(__GNUCLIKE_ASM && __GNUCLIKE_BUILTIN_CONSTANT_P) */ - -/* - * No optimizations are available for this compiler. Fall back to - * non-optimized functions by defining the constant usually used to prevent - * redefinition. - */ -#define _BYTEORDER_FUNC_DEFINED - -#endif /* __GNUCLIKE_ASM && __GNUCLIKE_BUILTIN_CONSTANT_P */ - -#ifdef __cplusplus -} -#endif - -#endif /* !_MACHINE_ENDIAN_H_ */ +#include -- cgit v1.1 From e5cc7570cf77fb32aebfcb893b650cae4d611a68 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 22:17:52 +0000 Subject: Copy amd64 setjmp.h to x86 and replace amd64/i386/pc98 setjmp.h with stubs. --- sys/amd64/include/setjmp.h | 50 +++------------------------------------------- 1 file changed, 3 insertions(+), 47 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/setjmp.h b/sys/amd64/include/setjmp.h index c33f9a5..c4101a7 100644 --- a/sys/amd64/include/setjmp.h +++ b/sys/amd64/include/setjmp.h @@ -1,50 +1,6 @@ /*- - * Copyright (c) 1998 John Birrell . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_SETJMP_H_ -#define _MACHINE_SETJMP_H_ - -#include - -#define _JBLEN 12 /* Size of the jmp_buf on AMD64. */ - -/* - * jmp_buf and sigjmp_buf are encapsulated in different structs to force - * compile-time diagnostics for mismatches. The structs are the same - * internally to avoid some run-time errors for mismatches. - */ -#if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE -typedef struct _sigjmp_buf { long _sjb[_JBLEN]; } sigjmp_buf[1]; -#endif - -typedef struct _jmp_buf { long _jb[_JBLEN]; } jmp_buf[1]; - -#endif /* !_MACHINE_SETJMP_H_ */ +#include -- cgit v1.1 From 2db0395534d0b3319e7f923a1be5bc6410c3d006 Mon Sep 17 00:00:00 2001 From: tijl Date: Tue, 28 Feb 2012 22:30:58 +0000 Subject: Copy amd64 stdarg.h to x86 and replace amd64/i386/pc98 stdarg.h with stubs. --- sys/amd64/include/stdarg.h | 75 ++-------------------------------------------- 1 file changed, 3 insertions(+), 72 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/stdarg.h b/sys/amd64/include/stdarg.h index c315dfc..1f80090 100644 --- a/sys/amd64/include/stdarg.h +++ b/sys/amd64/include/stdarg.h @@ -1,75 +1,6 @@ /*- - * Copyright (c) 2002 David E. O'Brien. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_STDARG_H_ -#define _MACHINE_STDARG_H_ - -#include -#include - -#ifndef _VA_LIST_DECLARED -#define _VA_LIST_DECLARED -typedef __va_list va_list; -#endif - -#ifdef __GNUCLIKE_BUILTIN_STDARG - -#define va_start(ap, last) \ - __builtin_va_start((ap), (last)) - -#define va_arg(ap, type) \ - __builtin_va_arg((ap), type) - -#define __va_copy(dest, src) \ - __builtin_va_copy((dest), (src)) - -#if __ISO_C_VISIBLE >= 1999 -#define va_copy(dest, src) \ - __va_copy(dest, src) -#endif - -#define va_end(ap) \ - __builtin_va_end(ap) - -#elif defined(lint) -/* Provide a fake implementation for lint's benefit */ -#define __va_size(type) \ - (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) -#define va_start(ap, last) \ - ((ap) = (va_list)&(last) + __va_size(last)) -#define va_arg(ap, type) \ - (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) -#define va_end(ap) - -#else -#error this file needs to be ported to your compiler -#endif - -#endif /* !_MACHINE_STDARG_H_ */ +#include -- cgit v1.1 From 28848902c77a2d9cc69d4827c19a592aa8c8f601 Mon Sep 17 00:00:00 2001 From: tijl Date: Sun, 4 Mar 2012 14:00:32 +0000 Subject: Copy amd64 float.h to x86 and merge with i386 float.h. Replace amd64/i386/pc98 float.h with stubs. --- sys/amd64/include/float.h | 94 ++--------------------------------------------- 1 file changed, 3 insertions(+), 91 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/float.h b/sys/amd64/include/float.h index 00ed6e2..4759963 100644 --- a/sys/amd64/include/float.h +++ b/sys/amd64/include/float.h @@ -1,94 +1,6 @@ /*- - * Copyright (c) 1989 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)float.h 7.1 (Berkeley) 5/8/90 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_FLOAT_H_ -#define _MACHINE_FLOAT_H_ 1 - -#include - -__BEGIN_DECLS -extern int __flt_rounds(void); -__END_DECLS - -#define FLT_RADIX 2 /* b */ -#define FLT_ROUNDS __flt_rounds() -#if __ISO_C_VISIBLE >= 1999 -#define FLT_EVAL_METHOD 0 /* no promotions */ -#define DECIMAL_DIG 21 /* max precision in decimal digits */ -#endif - -#define FLT_MANT_DIG 24 /* p */ -#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ -#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ -#define FLT_MIN_EXP (-125) /* emin */ -#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ -#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ -#define FLT_MAX_EXP 128 /* emax */ -#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ -#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ -#if __ISO_C_VISIBLE >= 2011 -#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ -#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ -#define FLT_HAS_SUBNORM 1 -#endif /* __ISO_C_VISIBLE >= 2011 */ - -#define DBL_MANT_DIG 53 -#define DBL_EPSILON 2.2204460492503131E-16 -#define DBL_DIG 15 -#define DBL_MIN_EXP (-1021) -#define DBL_MIN 2.2250738585072014E-308 -#define DBL_MIN_10_EXP (-307) -#define DBL_MAX_EXP 1024 -#define DBL_MAX 1.7976931348623157E+308 -#define DBL_MAX_10_EXP 308 -#if __ISO_C_VISIBLE >= 2011 -#define DBL_TRUE_MIN 4.9406564584124654E-324 -#define DBL_DECIMAL_DIG 17 -#define DBL_HAS_SUBNORM 1 -#endif /* __ISO_C_VISIBLE >= 2011 */ - -#define LDBL_MANT_DIG 64 -#define LDBL_EPSILON 1.0842021724855044340E-19L -#define LDBL_DIG 18 -#define LDBL_MIN_EXP (-16381) -#define LDBL_MIN 3.3621031431120935063E-4932L -#define LDBL_MIN_10_EXP (-4931) -#define LDBL_MAX_EXP 16384 -#define LDBL_MAX 1.1897314953572317650E+4932L -#define LDBL_MAX_10_EXP 4932 -#if __ISO_C_VISIBLE >= 2011 -#define LDBL_TRUE_MIN 3.6451995318824746025E-4951L -#define LDBL_DECIMAL_DIG 21 -#define LDBL_HAS_SUBNORM 1 -#endif /* __ISO_C_VISIBLE >= 2011 */ - -#endif /* _MACHINE_FLOAT_H_ */ +#include -- cgit v1.1 From bb4b86d0ab9a9ef56906ea47e3111a404c3094cf Mon Sep 17 00:00:00 2001 From: tijl Date: Sun, 4 Mar 2012 14:12:57 +0000 Subject: Copy amd64 trap.h to x86 and replace amd64/i386/pc98 trap.h with stubs. --- sys/amd64/include/trap.h | 95 ++---------------------------------------------- 1 file changed, 3 insertions(+), 92 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/trap.h b/sys/amd64/include/trap.h index a395d62..4d95077 100644 --- a/sys/amd64/include/trap.h +++ b/sys/amd64/include/trap.h @@ -1,95 +1,6 @@ /*- - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)trap.h 5.4 (Berkeley) 5/9/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_TRAP_H_ -#define _MACHINE_TRAP_H_ - -/* - * Trap type values - * also known in trap.c for name strings - */ - -#define T_PRIVINFLT 1 /* privileged instruction */ -#define T_BPTFLT 3 /* breakpoint instruction */ -#define T_ARITHTRAP 6 /* arithmetic trap */ -#define T_PROTFLT 9 /* protection fault */ -#define T_TRCTRAP 10 /* debug exception (sic) */ -#define T_PAGEFLT 12 /* page fault */ -#define T_ALIGNFLT 14 /* alignment fault */ - -#define T_DIVIDE 18 /* integer divide fault */ -#define T_NMI 19 /* non-maskable trap */ -#define T_OFLOW 20 /* overflow trap */ -#define T_BOUND 21 /* bound instruction fault */ -#define T_DNA 22 /* device not available fault */ -#define T_DOUBLEFLT 23 /* double fault */ -#define T_FPOPFLT 24 /* fp coprocessor operand fetch fault */ -#define T_TSSFLT 25 /* invalid tss fault */ -#define T_SEGNPFLT 26 /* segment not present fault */ -#define T_STKFLT 27 /* stack fault */ -#define T_MCHK 28 /* machine check trap */ -#define T_XMMFLT 29 /* SIMD floating-point exception */ -#define T_RESERVED 30 /* reserved (unknown) */ -#define T_DTRACE_RET 32 /* DTrace pid return */ -#define T_DTRACE_PROBE 33 /* DTrace fasttrap probe */ - -/* XXX most of the following codes aren't used, but could be. */ - -/* definitions for */ -#define ILL_RESAD_FAULT T_RESADFLT -#define ILL_PRIVIN_FAULT T_PRIVINFLT -#define ILL_RESOP_FAULT T_RESOPFLT -#define ILL_ALIGN_FAULT T_ALIGNFLT -#define ILL_FPOP_FAULT T_FPOPFLT /* coprocessor operand fault */ - -/* old FreeBSD macros, deprecated */ -#define FPE_INTOVF_TRAP 0x1 /* integer overflow */ -#define FPE_INTDIV_TRAP 0x2 /* integer divide by zero */ -#define FPE_FLTDIV_TRAP 0x3 /* floating/decimal divide by zero */ -#define FPE_FLTOVF_TRAP 0x4 /* floating overflow */ -#define FPE_FLTUND_TRAP 0x5 /* floating underflow */ -#define FPE_FPU_NP_TRAP 0x6 /* floating point unit not present */ -#define FPE_SUBRNG_TRAP 0x7 /* subrange out of bounds */ - -/* codes for SIGBUS */ -#define BUS_PAGE_FAULT T_PAGEFLT /* page fault protection base */ -#define BUS_SEGNP_FAULT T_SEGNPFLT /* segment not present */ -#define BUS_STK_FAULT T_STKFLT /* stack segment */ -#define BUS_SEGM_FAULT T_RESERVED /* segment protection base */ - -/* Trap's coming from user mode */ -#define T_USER 0x100 - -#endif /* !_MACHINE_TRAP_H_ */ +#include -- cgit v1.1 From ab137477da9e3fd1376fff4b2d20a7333cdbfa1b Mon Sep 17 00:00:00 2001 From: tijl Date: Sun, 4 Mar 2012 20:24:28 +0000 Subject: Copy amd64 ptrace.h to x86 and merge with i386 ptrace.h. Replace amd64/i386/pc98 ptrace.h with stubs. For amd64 PT_GETXSTATE and PT_SETXSTATE have been redefined to match the i386 values. The old values are still supported but should no longer be used. Reviewed by: kib --- sys/amd64/include/ptrace.h | 41 +++-------------------------------------- 1 file changed, 3 insertions(+), 38 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/ptrace.h b/sys/amd64/include/ptrace.h index 28f94f7..bf86754 100644 --- a/sys/amd64/include/ptrace.h +++ b/sys/amd64/include/ptrace.h @@ -1,41 +1,6 @@ /*- - * Copyright (c) 1992, 1993 - * The Regents of the University of California. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)ptrace.h 8.1 (Berkeley) 6/11/93 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_PTRACE_H_ -#define _MACHINE_PTRACE_H_ - -#define __HAVE_PTRACE_MACHDEP - -#define PT_GETXSTATE (PT_FIRSTMACH + 0) -#define PT_SETXSTATE (PT_FIRSTMACH + 1) - -#endif +#include -- cgit v1.1 From 9c671fcacaa05105013becd8a9a70514228bb3fd Mon Sep 17 00:00:00 2001 From: tijl Date: Fri, 16 Mar 2012 20:24:30 +0000 Subject: Move userland bits of i386 npx.h and amd64 fpu.h to x86 fpu.h. Remove FPU types from compat/ia32/ia32_reg.h that are no longer needed. Create machine/npx.h on amd64 to allow compiling i386 code that uses this header. The original npx.h and fpu.h define struct envxmm differently. Both definitions have been included in the new x86 header as struct __envxmm32 and struct __envxmm64. During compilation either __envxmm32 or __envxmm64 is defined as envxmm depending on machine architecture. On amd64 the i386 struct is also available as struct envxmm32. Reviewed by: kib --- sys/amd64/include/fpu.h | 85 +------------------------------------------------ sys/amd64/include/npx.h | 6 ++++ 2 files changed, 7 insertions(+), 84 deletions(-) create mode 100644 sys/amd64/include/npx.h (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/fpu.h b/sys/amd64/include/fpu.h index d208789..98a016b 100644 --- a/sys/amd64/include/fpu.h +++ b/sys/amd64/include/fpu.h @@ -41,64 +41,7 @@ #ifndef _MACHINE_FPU_H_ #define _MACHINE_FPU_H_ -/* Contents of each x87 floating point accumulator */ -struct fpacc87 { - uint8_t fp_bytes[10]; -}; - -/* Contents of each SSE extended accumulator */ -struct xmmacc { - uint8_t xmm_bytes[16]; -}; - -/* Contents of the upper 16 bytes of each AVX extended accumulator */ -struct ymmacc { - uint8_t ymm_bytes[16]; -}; - -struct envxmm { - uint16_t en_cw; /* control word (16bits) */ - uint16_t en_sw; /* status word (16bits) */ - uint8_t en_tw; /* tag word (8bits) */ - uint8_t en_zero; - uint16_t en_opcode; /* opcode last executed (11 bits ) */ - uint64_t en_rip; /* floating point instruction pointer */ - uint64_t en_rdp; /* floating operand pointer */ - uint32_t en_mxcsr; /* SSE sontorol/status register */ - uint32_t en_mxcsr_mask; /* valid bits in mxcsr */ -}; - -struct savefpu { - struct envxmm sv_env; - struct { - struct fpacc87 fp_acc; - uint8_t fp_pad[6]; /* padding */ - } sv_fp[8]; - struct xmmacc sv_xmm[16]; - uint8_t sv_pad[96]; -} __aligned(16); - -struct xstate_hdr { - uint64_t xstate_bv; - uint8_t xstate_rsrv0[16]; - uint8_t xstate_rsrv[40]; -}; - -struct savefpu_xstate { - struct xstate_hdr sx_hd; - struct ymmacc sx_ymm[16]; -}; - -struct savefpu_ymm { - struct envxmm sv_env; - struct { - struct fpacc87 fp_acc; - int8_t fp_pad[6]; /* padding */ - } sv_fp[8]; - struct xmmacc sv_xmm[16]; - uint8_t sv_pad[96]; - struct savefpu_xstate sv_xstate; -} __aligned(64); +#include #ifdef _KERNEL @@ -108,32 +51,6 @@ struct fpu_kern_ctx; #define XSAVE_AREA_ALIGN 64 -#endif - -/* - * The hardware default control word for i387's and later coprocessors is - * 0x37F, giving: - * - * round to nearest - * 64-bit precision - * all exceptions masked. - * - * FreeBSD/i386 uses 53 bit precision for things like fadd/fsub/fsqrt etc - * because of the difference between memory and fpu register stack arguments. - * If its using an intermediate fpu register, it has 80/64 bits to work - * with. If it uses memory, it has 64/53 bits to work with. However, - * gcc is aware of this and goes to a fair bit of trouble to make the - * best use of it. - * - * This is mostly academic for AMD64, because the ABI prefers the use - * SSE2 based math. For FreeBSD/amd64, we go with the default settings. - */ -#define __INITIAL_FPUCW__ 0x037F -#define __INITIAL_FPUCW_I386__ 0x127F -#define __INITIAL_MXCSR__ 0x1F80 -#define __INITIAL_MXCSR_MASK__ 0xFFBF - -#ifdef _KERNEL void fpudna(void); void fpudrop(void); void fpuexit(struct thread *td); diff --git a/sys/amd64/include/npx.h b/sys/amd64/include/npx.h new file mode 100644 index 0000000..ec70f1c --- /dev/null +++ b/sys/amd64/include/npx.h @@ -0,0 +1,6 @@ +/*- + * This file is in the public domain. + */ +/* $FreeBSD$ */ + +#include -- cgit v1.1 From f36691a4af70956621d759efff296eb1fa3d40fa Mon Sep 17 00:00:00 2001 From: tijl Date: Sun, 18 Mar 2012 18:44:42 +0000 Subject: Use exact width integer types in amd64/i386 reg.h to prepare for a merge. The only real change is replacing long with int on i386. --- sys/amd64/include/reg.h | 62 ++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/reg.h b/sys/amd64/include/reg.h index 275a998..3cb8596 100644 --- a/sys/amd64/include/reg.h +++ b/sys/amd64/include/reg.h @@ -45,32 +45,32 @@ * Register set accessible via /proc/$pid/regs and PT_{SET,GET}REGS. */ struct reg { - register_t r_r15; - register_t r_r14; - register_t r_r13; - register_t r_r12; - register_t r_r11; - register_t r_r10; - register_t r_r9; - register_t r_r8; - register_t r_rdi; - register_t r_rsi; - register_t r_rbp; - register_t r_rbx; - register_t r_rdx; - register_t r_rcx; - register_t r_rax; - uint32_t r_trapno; - uint16_t r_fs; - uint16_t r_gs; - uint32_t r_err; - uint16_t r_es; - uint16_t r_ds; - register_t r_rip; - register_t r_cs; - register_t r_rflags; - register_t r_rsp; - register_t r_ss; + __int64_t r_r15; + __int64_t r_r14; + __int64_t r_r13; + __int64_t r_r12; + __int64_t r_r11; + __int64_t r_r10; + __int64_t r_r9; + __int64_t r_r8; + __int64_t r_rdi; + __int64_t r_rsi; + __int64_t r_rbp; + __int64_t r_rbx; + __int64_t r_rdx; + __int64_t r_rcx; + __int64_t r_rax; + __uint32_t r_trapno; + __uint16_t r_fs; + __uint16_t r_gs; + __uint32_t r_err; + __uint16_t r_es; + __uint16_t r_ds; + __int64_t r_rip; + __int64_t r_cs; + __int64_t r_rflags; + __int64_t r_rsp; + __int64_t r_ss; }; /* @@ -82,17 +82,17 @@ struct fpreg { * simplified struct. This may be too much detail. Perhaps * an array of unsigned longs is best. */ - unsigned long fpr_env[4]; - unsigned char fpr_acc[8][16]; - unsigned char fpr_xacc[16][16]; - unsigned long fpr_spare[12]; + __uint64_t fpr_env[4]; + __uint8_t fpr_acc[8][16]; + __uint8_t fpr_xacc[16][16]; + __uint64_t fpr_spare[12]; }; /* * Register set accessible via /proc/$pid/dbregs. */ struct dbreg { - unsigned long dr[16]; /* debug registers */ + __uint64_t dr[16]; /* debug registers */ /* Index 0-3: debug address registers */ /* Index 4-5: reserved */ /* Index 6: debug status */ -- cgit v1.1 From 2bf580ea66d788d822942a29b2d9fe19d7d0c7d6 Mon Sep 17 00:00:00 2001 From: tijl Date: Sun, 18 Mar 2012 19:06:38 +0000 Subject: Copy i386 reg.h to x86 and merge with amd64 reg.h. Replace i386/amd64/pc98 reg.h with stubs. The tREGISTER macros are only made visible on i386. These macros are deprecated and should not be available on amd64. The i386 and amd64 versions of struct reg have been renamed to struct __reg32 and struct __reg64. During compilation either __reg32 or __reg64 is defined as reg depending on the machine architecture. On amd64 the i386 struct is also available as struct reg32 which is used in COMPAT_FREEBSD32 code. Most of compat/ia32/ia32_reg.h is now IA64 only. Reviewed by: kib (previous version) --- sys/amd64/include/reg.h | 141 ++---------------------------------------------- 1 file changed, 3 insertions(+), 138 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/reg.h b/sys/amd64/include/reg.h index 3cb8596..f6fb2bc 100644 --- a/sys/amd64/include/reg.h +++ b/sys/amd64/include/reg.h @@ -1,141 +1,6 @@ /*- - * Copyright (c) 2003 Peter Wemm. - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)reg.h 5.5 (Berkeley) 1/18/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_REG_H_ -#define _MACHINE_REG_H_ - -#if defined(_KERNEL) && !defined(_STANDALONE) -#include "opt_compat.h" -#endif - -/* - * Register set accessible via /proc/$pid/regs and PT_{SET,GET}REGS. - */ -struct reg { - __int64_t r_r15; - __int64_t r_r14; - __int64_t r_r13; - __int64_t r_r12; - __int64_t r_r11; - __int64_t r_r10; - __int64_t r_r9; - __int64_t r_r8; - __int64_t r_rdi; - __int64_t r_rsi; - __int64_t r_rbp; - __int64_t r_rbx; - __int64_t r_rdx; - __int64_t r_rcx; - __int64_t r_rax; - __uint32_t r_trapno; - __uint16_t r_fs; - __uint16_t r_gs; - __uint32_t r_err; - __uint16_t r_es; - __uint16_t r_ds; - __int64_t r_rip; - __int64_t r_cs; - __int64_t r_rflags; - __int64_t r_rsp; - __int64_t r_ss; -}; - -/* - * Register set accessible via /proc/$pid/fpregs. - */ -struct fpreg { - /* - * XXX should get struct from fpu.h. Here we give a slightly - * simplified struct. This may be too much detail. Perhaps - * an array of unsigned longs is best. - */ - __uint64_t fpr_env[4]; - __uint8_t fpr_acc[8][16]; - __uint8_t fpr_xacc[16][16]; - __uint64_t fpr_spare[12]; -}; - -/* - * Register set accessible via /proc/$pid/dbregs. - */ -struct dbreg { - __uint64_t dr[16]; /* debug registers */ - /* Index 0-3: debug address registers */ - /* Index 4-5: reserved */ - /* Index 6: debug status */ - /* Index 7: debug control */ - /* Index 8-15: reserved */ -}; - -#define DBREG_DR7_LOCAL_ENABLE 0x01 -#define DBREG_DR7_GLOBAL_ENABLE 0x02 -#define DBREG_DR7_LEN_1 0x00 /* 1 byte length */ -#define DBREG_DR7_LEN_2 0x01 -#define DBREG_DR7_LEN_4 0x03 -#define DBREG_DR7_LEN_8 0x02 -#define DBREG_DR7_EXEC 0x00 /* break on execute */ -#define DBREG_DR7_WRONLY 0x01 /* break on write */ -#define DBREG_DR7_RDWR 0x03 /* break on read or write */ -#define DBREG_DR7_MASK(i) (0xful << ((i) * 4 + 16) | 0x3 << (i) * 2) -#define DBREG_DR7_SET(i, len, access, enable) \ - ((u_long)((len) << 2 | (access)) << ((i) * 4 + 16) | (enable) << (i) * 2) -#define DBREG_DR7_GD 0x2000 -#define DBREG_DR7_ENABLED(d, i) (((d) & 0x3 << (i) * 2) != 0) -#define DBREG_DR7_ACCESS(d, i) ((d) >> ((i) * 4 + 16) & 0x3) -#define DBREG_DR7_LEN(d, i) ((d) >> ((i) * 4 + 18) & 0x3) - -#define DBREG_DRX(d,x) ((d)->dr[(x)]) /* reference dr0 - dr15 by - register number */ - -#ifdef COMPAT_FREEBSD32 -#include -#include -#endif - -#ifdef _KERNEL -/* - * XXX these interfaces are MI, so they should be declared in a MI place. - */ -int fill_regs(struct thread *, struct reg *); -int fill_frame_regs(struct trapframe *, struct reg *); -int set_regs(struct thread *, struct reg *); -int fill_fpregs(struct thread *, struct fpreg *); -int set_fpregs(struct thread *, struct fpreg *); -int fill_dbregs(struct thread *, struct dbreg *); -int set_dbregs(struct thread *, struct dbreg *); -#endif - -#endif /* !_MACHINE_REG_H_ */ +#include -- cgit v1.1 From 2a126f1975785720c0ebda4bddf37bdb73b6a197 Mon Sep 17 00:00:00 2001 From: tijl Date: Mon, 19 Mar 2012 21:24:50 +0000 Subject: Move userland bits (and some common kernel bits) from amd64 and i386 segments.h to a new x86 segments.h. Add __packed attribute to some structs (just to be sure). Also make it clear that i386 GDT and LDT entries are used in ia64 code. --- sys/amd64/include/segments.h | 151 +------------------------------------------ 1 file changed, 1 insertion(+), 150 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/segments.h b/sys/amd64/include/segments.h index 247cc34..d9f4280 100644 --- a/sys/amd64/include/segments.h +++ b/sys/amd64/include/segments.h @@ -41,45 +41,7 @@ * AMD64 Segmentation Data Structures and definitions */ -/* - * Selectors - */ - -#define SEL_RPL_MASK 3 /* requester priv level */ -#define ISPL(s) ((s)&3) /* what is the priority level of a selector */ -#define SEL_KPL 0 /* kernel priority level */ -#define SEL_UPL 3 /* user priority level */ -#define ISLDT(s) ((s)&SEL_LDT) /* is it local or global */ -#define SEL_LDT 4 /* local descriptor table */ -#define IDXSEL(s) (((s)>>3) & 0x1fff) /* index of selector */ -#define LSEL(s,r) (((s)<<3) | SEL_LDT | r) /* a local selector */ -#define GSEL(s,r) (((s)<<3) | r) /* a global selector */ - -/* - * User segment descriptors (%cs, %ds etc for compatability apps. 64 bit wide) - * For long-mode apps, %cs only has the conforming bit in sd_type, the sd_dpl, - * sd_p, sd_l and sd_def32 which must be zero). %ds only has sd_p. - */ -struct user_segment_descriptor { - u_int64_t sd_lolimit:16; /* segment extent (lsb) */ - u_int64_t sd_lobase:24; /* segment base address (lsb) */ - u_int64_t sd_type:5; /* segment type */ - u_int64_t sd_dpl:2; /* segment descriptor priority level */ - u_int64_t sd_p:1; /* segment descriptor present */ - u_int64_t sd_hilimit:4; /* segment extent (msb) */ - u_int64_t sd_xx:1; /* unused */ - u_int64_t sd_long:1; /* long mode (cs only) */ - u_int64_t sd_def32:1; /* default 32 vs 16 bit size */ - u_int64_t sd_gran:1; /* limit granularity (byte/page units)*/ - u_int64_t sd_hibase:8; /* segment base address (msb) */ -} __packed; - -#define USD_GETBASE(sd) (((sd)->sd_lobase) | (sd)->sd_hibase << 24) -#define USD_SETBASE(sd, b) (sd)->sd_lobase = (b); \ - (sd)->sd_hibase = ((b) >> 24); -#define USD_GETLIMIT(sd) (((sd)->sd_lolimit) | (sd)->sd_hilimit << 16) -#define USD_SETLIMIT(sd, l) (sd)->sd_lolimit = (l); \ - (sd)->sd_hilimit = ((l) >> 16); +#include /* * System segment descriptors (128 bit wide) @@ -100,66 +62,6 @@ struct system_segment_descriptor { } __packed; /* - * Gate descriptors (e.g. indirect descriptors, trap, interrupt etc. 128 bit) - * Only interrupt and trap gates have gd_ist. - */ -struct gate_descriptor { - u_int64_t gd_looffset:16; /* gate offset (lsb) */ - u_int64_t gd_selector:16; /* gate segment selector */ - u_int64_t gd_ist:3; /* IST table index */ - u_int64_t gd_xx:5; /* unused */ - u_int64_t gd_type:5; /* segment type */ - u_int64_t gd_dpl:2; /* segment descriptor priority level */ - u_int64_t gd_p:1; /* segment descriptor present */ - u_int64_t gd_hioffset:48 __packed; /* gate offset (msb) */ - u_int64_t sd_xx1:32; -} __packed; - -/* - * Generic descriptor - */ -union descriptor { - struct user_segment_descriptor sd; - struct gate_descriptor gd; -}; - - /* system segments and gate types */ -#define SDT_SYSNULL 0 /* system null */ -#define SDT_SYS286TSS 1 /* system 286 TSS available */ -#define SDT_SYSLDT 2 /* system 64 bit local descriptor table */ -#define SDT_SYS286BSY 3 /* system 286 TSS busy */ -#define SDT_SYS286CGT 4 /* system 286 call gate */ -#define SDT_SYSTASKGT 5 /* system task gate */ -#define SDT_SYS286IGT 6 /* system 286 interrupt gate */ -#define SDT_SYS286TGT 7 /* system 286 trap gate */ -#define SDT_SYSNULL2 8 /* system null again */ -#define SDT_SYSTSS 9 /* system available 64 bit TSS */ -#define SDT_SYSNULL3 10 /* system null again */ -#define SDT_SYSBSY 11 /* system busy 64 bit TSS */ -#define SDT_SYSCGT 12 /* system 64 bit call gate */ -#define SDT_SYSNULL4 13 /* system null again */ -#define SDT_SYSIGT 14 /* system 64 bit interrupt gate */ -#define SDT_SYSTGT 15 /* system 64 bit trap gate */ - - /* memory segment types */ -#define SDT_MEMRO 16 /* memory read only */ -#define SDT_MEMROA 17 /* memory read only accessed */ -#define SDT_MEMRW 18 /* memory read write */ -#define SDT_MEMRWA 19 /* memory read write accessed */ -#define SDT_MEMROD 20 /* memory read only expand dwn limit */ -#define SDT_MEMRODA 21 /* memory read only expand dwn limit accessed */ -#define SDT_MEMRWD 22 /* memory read write expand dwn limit */ -#define SDT_MEMRWDA 23 /* memory read write expand dwn limit accessed */ -#define SDT_MEME 24 /* memory execute only */ -#define SDT_MEMEA 25 /* memory execute only accessed */ -#define SDT_MEMER 26 /* memory execute read */ -#define SDT_MEMERA 27 /* memory execute read accessed */ -#define SDT_MEMEC 28 /* memory execute only conforming */ -#define SDT_MEMEAC 29 /* memory execute only accessed conforming */ -#define SDT_MEMERC 30 /* memory execute read conforming */ -#define SDT_MEMERAC 31 /* memory execute read accessed conforming */ - -/* * Software definitions are in this convenient format, * which are translated into inconvenient segment descriptors * when needed to be used by the 386 hardware @@ -184,56 +86,6 @@ struct region_descriptor { unsigned long rd_base:64 __packed; /* base address */ } __packed; -/* - * Size of IDT table - */ -#define NIDT 256 /* 32 reserved, 16 h/w, 0 s/w, linux's 0x80 */ -#define NRSVIDT 32 /* reserved entries for cpu exceptions */ - -/* - * Entries in the Interrupt Descriptor Table (IDT) - */ -#define IDT_DE 0 /* #DE: Divide Error */ -#define IDT_DB 1 /* #DB: Debug */ -#define IDT_NMI 2 /* Nonmaskable External Interrupt */ -#define IDT_BP 3 /* #BP: Breakpoint */ -#define IDT_OF 4 /* #OF: Overflow */ -#define IDT_BR 5 /* #BR: Bound Range Exceeded */ -#define IDT_UD 6 /* #UD: Undefined/Invalid Opcode */ -#define IDT_NM 7 /* #NM: No Math Coprocessor */ -#define IDT_DF 8 /* #DF: Double Fault */ -#define IDT_FPUGP 9 /* Coprocessor Segment Overrun */ -#define IDT_TS 10 /* #TS: Invalid TSS */ -#define IDT_NP 11 /* #NP: Segment Not Present */ -#define IDT_SS 12 /* #SS: Stack Segment Fault */ -#define IDT_GP 13 /* #GP: General Protection Fault */ -#define IDT_PF 14 /* #PF: Page Fault */ -#define IDT_MF 16 /* #MF: FPU Floating-Point Error */ -#define IDT_AC 17 /* #AC: Alignment Check */ -#define IDT_MC 18 /* #MC: Machine Check */ -#define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */ -#define IDT_IO_INTS NRSVIDT /* Base of IDT entries for I/O interrupts. */ -#define IDT_DTRACE_RET 0x20 /* DTrace pid provider Interrupt Vector */ -#define IDT_SYSCALL 0x80 /* System Call Interrupt Vector */ - -/* - * Entries in the Global Descriptor Table (GDT) - */ -#define GNULL_SEL 0 /* Null Descriptor */ -#define GNULL2_SEL 1 /* Null Descriptor */ -#define GUFS32_SEL 2 /* User 32 bit %fs Descriptor */ -#define GUGS32_SEL 3 /* User 32 bit %gs Descriptor */ -#define GCODE_SEL 4 /* Kernel Code Descriptor */ -#define GDATA_SEL 5 /* Kernel Data Descriptor */ -#define GUCODE32_SEL 6 /* User 32 bit code Descriptor */ -#define GUDATA_SEL 7 /* User 32/64 bit Data Descriptor */ -#define GUCODE_SEL 8 /* User 64 bit Code Descriptor */ -#define GPROC0_SEL 9 /* TSS for entering kernel etc */ -/* slot 10 is second half of GPROC0_SEL */ -#define GUSERLDT_SEL 11 /* LDT */ -/* slot 11 is second half of GUSERLDT_SEL */ -#define NGDT 13 - #ifdef _KERNEL extern struct user_segment_descriptor gdt[]; extern struct soft_segment_descriptor gdt_segs[]; @@ -249,7 +101,6 @@ void ssdtosyssd(struct soft_segment_descriptor *ssdp, struct system_segment_descriptor *sdp); void update_gdt_gsbase(struct thread *td, uint32_t base); void update_gdt_fsbase(struct thread *td, uint32_t base); - #endif /* _KERNEL */ #endif /* !_MACHINE_SEGMENTS_H_ */ -- cgit v1.1 From ea1f38e564b72654ed1d7384cf6617d5435c44ee Mon Sep 17 00:00:00 2001 From: tijl Date: Mon, 19 Mar 2012 21:29:57 +0000 Subject: Copy i386 psl.h to x86 and replace amd64/i386/pc98 psl.h with stubs. --- sys/amd64/include/psl.h | 84 ++----------------------------------------------- 1 file changed, 3 insertions(+), 81 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/psl.h b/sys/amd64/include/psl.h index 07c21ea..4d945a1 100644 --- a/sys/amd64/include/psl.h +++ b/sys/amd64/include/psl.h @@ -1,84 +1,6 @@ /*- - * Copyright (c) 1990 The Regents of the University of California. - * All rights reserved. - * - * This code is derived from software contributed to Berkeley by - * William Jolitz. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)psl.h 5.2 (Berkeley) 1/18/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_PSL_H_ -#define _MACHINE_PSL_H_ - -/* - * 386 processor status longword. - */ -#define PSL_C 0x00000001 /* carry bit */ -#define PSL_PF 0x00000004 /* parity bit */ -#define PSL_AF 0x00000010 /* bcd carry bit */ -#define PSL_Z 0x00000040 /* zero bit */ -#define PSL_N 0x00000080 /* negative bit */ -#define PSL_T 0x00000100 /* trace enable bit */ -#define PSL_I 0x00000200 /* interrupt enable bit */ -#define PSL_D 0x00000400 /* string instruction direction bit */ -#define PSL_V 0x00000800 /* overflow bit */ -#define PSL_IOPL 0x00003000 /* i/o privilege level */ -#define PSL_NT 0x00004000 /* nested task bit */ -#define PSL_RF 0x00010000 /* resume flag bit */ -/* #define PSL_VM 0x00020000 */ /* virtual 8086 mode bit */ -#define PSL_AC 0x00040000 /* alignment checking */ -/* #define PSL_VIF 0x00080000 */ /* virtual interrupt enable */ -/* #define PSL_VIP 0x00100000 */ /* virtual interrupt pending */ -#define PSL_ID 0x00200000 /* identification bit */ - -/* - * The i486 manual says that we are not supposed to change reserved flags, - * but this is too much trouble since the reserved flags depend on the cpu - * and setting them to their historical values works in practice. - */ -#define PSL_RESERVED_DEFAULT 0x00000002 - -/* - * Initial flags for kernel and user mode. The kernel later inherits - * PSL_I and some other flags from user mode. - */ -#define PSL_KERNEL PSL_RESERVED_DEFAULT -#define PSL_USER (PSL_RESERVED_DEFAULT | PSL_I) - -/* - * Bits that can be changed in user mode on 486's. We allow these bits - * to be changed using ptrace(), sigreturn() and procfs. Setting PS_NT - * is undesirable but it may as well be allowed since users can inflict - * it on the kernel directly. Changes to PSL_AC are silently ignored on - * 386's. - */ -#define PSL_USERCHANGE (PSL_C | PSL_PF | PSL_AF | PSL_Z | PSL_N | PSL_T \ - | PSL_D | PSL_V | PSL_NT | PSL_AC | PSL_ID) - -#endif /* !_MACHINE_PSL_H_ */ +#include -- cgit v1.1 From 42f636fdcd3eb6af00c6ed79f699224d198a1787 Mon Sep 17 00:00:00 2001 From: tijl Date: Mon, 19 Mar 2012 21:34:11 +0000 Subject: Copy i386 specialreg.h to x86 and merge with amd64 specialreg.h. Replace amd64/i386/pc98 specialreg.h with stubs. --- sys/amd64/include/specialreg.h | 597 +---------------------------------------- 1 file changed, 3 insertions(+), 594 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 7ba5f9f..aace4bf 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -1,597 +1,6 @@ /*- - * Copyright (c) 1991 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -#ifndef _MACHINE_SPECIALREG_H_ -#define _MACHINE_SPECIALREG_H_ - -/* - * Bits in 386 special registers: - */ -#define CR0_PE 0x00000001 /* Protected mode Enable */ -#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ -#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ -#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ -#define CR0_PG 0x80000000 /* PaGing enable */ - -/* - * Bits in 486 special registers: - */ -#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ -#define CR0_WP 0x00010000 /* Write Protect (honor page protect in - all modes) */ -#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ -#define CR0_NW 0x20000000 /* Not Write-through */ -#define CR0_CD 0x40000000 /* Cache Disable */ - -/* - * Bits in PPro special registers - */ -#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ -#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ -#define CR4_TSD 0x00000004 /* Time stamp disable */ -#define CR4_DE 0x00000008 /* Debugging extensions */ -#define CR4_PSE 0x00000010 /* Page size extensions */ -#define CR4_PAE 0x00000020 /* Physical address extension */ -#define CR4_MCE 0x00000040 /* Machine check enable */ -#define CR4_PGE 0x00000080 /* Page global enable */ -#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ -#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ -#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ -#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ - -/* - * Bits in AMD64 special registers. EFER is 64 bits wide. - */ -#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ -#define EFER_LME 0x000000100 /* Long mode enable (R/W) */ -#define EFER_LMA 0x000000400 /* Long mode active (R) */ -#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ - -/* - * Intel Extended Features registers - */ -#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ - -#define XFEATURE_ENABLED_X87 0x00000001 -#define XFEATURE_ENABLED_SSE 0x00000002 -#define XFEATURE_ENABLED_AVX 0x00000004 - -#define XFEATURE_AVX \ - (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) - -/* - * CPUID instruction features register - */ -#define CPUID_FPU 0x00000001 -#define CPUID_VME 0x00000002 -#define CPUID_DE 0x00000004 -#define CPUID_PSE 0x00000008 -#define CPUID_TSC 0x00000010 -#define CPUID_MSR 0x00000020 -#define CPUID_PAE 0x00000040 -#define CPUID_MCE 0x00000080 -#define CPUID_CX8 0x00000100 -#define CPUID_APIC 0x00000200 -#define CPUID_B10 0x00000400 -#define CPUID_SEP 0x00000800 -#define CPUID_MTRR 0x00001000 -#define CPUID_PGE 0x00002000 -#define CPUID_MCA 0x00004000 -#define CPUID_CMOV 0x00008000 -#define CPUID_PAT 0x00010000 -#define CPUID_PSE36 0x00020000 -#define CPUID_PSN 0x00040000 -#define CPUID_CLFSH 0x00080000 -#define CPUID_B20 0x00100000 -#define CPUID_DS 0x00200000 -#define CPUID_ACPI 0x00400000 -#define CPUID_MMX 0x00800000 -#define CPUID_FXSR 0x01000000 -#define CPUID_SSE 0x02000000 -#define CPUID_XMM 0x02000000 -#define CPUID_SSE2 0x04000000 -#define CPUID_SS 0x08000000 -#define CPUID_HTT 0x10000000 -#define CPUID_TM 0x20000000 -#define CPUID_IA64 0x40000000 -#define CPUID_PBE 0x80000000 - -#define CPUID2_SSE3 0x00000001 -#define CPUID2_PCLMULQDQ 0x00000002 -#define CPUID2_DTES64 0x00000004 -#define CPUID2_MON 0x00000008 -#define CPUID2_DS_CPL 0x00000010 -#define CPUID2_VMX 0x00000020 -#define CPUID2_SMX 0x00000040 -#define CPUID2_EST 0x00000080 -#define CPUID2_TM2 0x00000100 -#define CPUID2_SSSE3 0x00000200 -#define CPUID2_CNXTID 0x00000400 -#define CPUID2_FMA 0x00001000 -#define CPUID2_CX16 0x00002000 -#define CPUID2_XTPR 0x00004000 -#define CPUID2_PDCM 0x00008000 -#define CPUID2_PCID 0x00020000 -#define CPUID2_DCA 0x00040000 -#define CPUID2_SSE41 0x00080000 -#define CPUID2_SSE42 0x00100000 -#define CPUID2_X2APIC 0x00200000 -#define CPUID2_MOVBE 0x00400000 -#define CPUID2_POPCNT 0x00800000 -#define CPUID2_TSCDLT 0x01000000 -#define CPUID2_AESNI 0x02000000 -#define CPUID2_XSAVE 0x04000000 -#define CPUID2_OSXSAVE 0x08000000 -#define CPUID2_AVX 0x10000000 -#define CPUID2_F16C 0x20000000 -#define CPUID2_HV 0x80000000 - -/* - * Important bits in the Thermal and Power Management flags - * CPUID.6 EAX and ECX. - */ -#define CPUTPM1_SENSOR 0x00000001 -#define CPUTPM1_TURBO 0x00000002 -#define CPUTPM1_ARAT 0x00000004 -#define CPUTPM2_EFFREQ 0x00000001 - -/* - * Important bits in the AMD extended cpuid flags - */ -#define AMDID_SYSCALL 0x00000800 -#define AMDID_MP 0x00080000 -#define AMDID_NX 0x00100000 -#define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 -#define AMDID_PAGE1GB 0x04000000 -#define AMDID_RDTSCP 0x08000000 -#define AMDID_LM 0x20000000 -#define AMDID_EXT_3DNOW 0x40000000 -#define AMDID_3DNOW 0x80000000 - -#define AMDID2_LAHF 0x00000001 -#define AMDID2_CMP 0x00000002 -#define AMDID2_SVM 0x00000004 -#define AMDID2_EXT_APIC 0x00000008 -#define AMDID2_CR8 0x00000010 -#define AMDID2_ABM 0x00000020 -#define AMDID2_SSE4A 0x00000040 -#define AMDID2_MAS 0x00000080 -#define AMDID2_PREFETCH 0x00000100 -#define AMDID2_OSVW 0x00000200 -#define AMDID2_IBS 0x00000400 -#define AMDID2_XOP 0x00000800 -#define AMDID2_SKINIT 0x00001000 -#define AMDID2_WDT 0x00002000 -#define AMDID2_LWP 0x00008000 -#define AMDID2_FMA4 0x00010000 -#define AMDID2_NODE_ID 0x00080000 -#define AMDID2_TBM 0x00200000 -#define AMDID2_TOPOLOGY 0x00400000 - -/* - * CPUID instruction 1 eax info - */ -#define CPUID_STEPPING 0x0000000f -#define CPUID_MODEL 0x000000f0 -#define CPUID_FAMILY 0x00000f00 -#define CPUID_EXT_MODEL 0x000f0000 -#define CPUID_EXT_FAMILY 0x0ff00000 -#define CPUID_TO_MODEL(id) \ - ((((id) & CPUID_MODEL) >> 4) | \ - (((id) & CPUID_EXT_MODEL) >> 12)) -#define CPUID_TO_FAMILY(id) \ - ((((id) & CPUID_FAMILY) >> 8) + \ - (((id) & CPUID_EXT_FAMILY) >> 20)) - -/* - * CPUID instruction 1 ebx info - */ -#define CPUID_BRAND_INDEX 0x000000ff -#define CPUID_CLFUSH_SIZE 0x0000ff00 -#define CPUID_HTT_CORES 0x00ff0000 -#define CPUID_LOCAL_APIC_ID 0xff000000 - -/* - * CPUID instruction 6 ecx info - */ -#define CPUID_PERF_STAT 0x00000001 -#define CPUID_PERF_BIAS 0x00000008 - -/* - * CPUID instruction 0xb ebx info. - */ -#define CPUID_TYPE_INVAL 0 -#define CPUID_TYPE_SMT 1 -#define CPUID_TYPE_CORE 2 - -/* - * AMD extended function 8000_0007h edx info - */ -#define AMDPM_TS 0x00000001 -#define AMDPM_FID 0x00000002 -#define AMDPM_VID 0x00000004 -#define AMDPM_TTP 0x00000008 -#define AMDPM_TM 0x00000010 -#define AMDPM_STC 0x00000020 -#define AMDPM_100MHZ_STEPS 0x00000040 -#define AMDPM_HW_PSTATE 0x00000080 -#define AMDPM_TSC_INVARIANT 0x00000100 -#define AMDPM_CPB 0x00000200 - -/* - * AMD extended function 8000_0008h ecx info - */ -#define AMDID_CMP_CORES 0x000000ff -#define AMDID_COREID_SIZE 0x0000f000 -#define AMDID_COREID_SIZE_SHIFT 12 - -/* - * CPUID manufacturers identifiers - */ -#define AMD_VENDOR_ID "AuthenticAMD" -#define CENTAUR_VENDOR_ID "CentaurHauls" -#define INTEL_VENDOR_ID "GenuineIntel" - -/* - * Model-specific registers for the i386 family - */ -#define MSR_P5_MC_ADDR 0x000 -#define MSR_P5_MC_TYPE 0x001 -#define MSR_TSC 0x010 -#define MSR_P5_CESR 0x011 -#define MSR_P5_CTR0 0x012 -#define MSR_P5_CTR1 0x013 -#define MSR_IA32_PLATFORM_ID 0x017 -#define MSR_APICBASE 0x01b -#define MSR_EBL_CR_POWERON 0x02a -#define MSR_TEST_CTL 0x033 -#define MSR_BIOS_UPDT_TRIG 0x079 -#define MSR_BBL_CR_D0 0x088 -#define MSR_BBL_CR_D1 0x089 -#define MSR_BBL_CR_D2 0x08a -#define MSR_BIOS_SIGN 0x08b -#define MSR_PERFCTR0 0x0c1 -#define MSR_PERFCTR1 0x0c2 -#define MSR_MPERF 0x0e7 -#define MSR_APERF 0x0e8 -#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ -#define MSR_MTRRcap 0x0fe -#define MSR_BBL_CR_ADDR 0x116 -#define MSR_BBL_CR_DECC 0x118 -#define MSR_BBL_CR_CTL 0x119 -#define MSR_BBL_CR_TRIG 0x11a -#define MSR_BBL_CR_BUSY 0x11b -#define MSR_BBL_CR_CTL3 0x11e -#define MSR_SYSENTER_CS_MSR 0x174 -#define MSR_SYSENTER_ESP_MSR 0x175 -#define MSR_SYSENTER_EIP_MSR 0x176 -#define MSR_MCG_CAP 0x179 -#define MSR_MCG_STATUS 0x17a -#define MSR_MCG_CTL 0x17b -#define MSR_EVNTSEL0 0x186 -#define MSR_EVNTSEL1 0x187 -#define MSR_THERM_CONTROL 0x19a -#define MSR_THERM_INTERRUPT 0x19b -#define MSR_THERM_STATUS 0x19c -#define MSR_IA32_MISC_ENABLE 0x1a0 -#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 -#define MSR_DEBUGCTLMSR 0x1d9 -#define MSR_LASTBRANCHFROMIP 0x1db -#define MSR_LASTBRANCHTOIP 0x1dc -#define MSR_LASTINTFROMIP 0x1dd -#define MSR_LASTINTTOIP 0x1de -#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 -#define MSR_MTRRVarBase 0x200 -#define MSR_MTRR64kBase 0x250 -#define MSR_MTRR16kBase 0x258 -#define MSR_MTRR4kBase 0x268 -#define MSR_PAT 0x277 -#define MSR_MC0_CTL2 0x280 -#define MSR_MTRRdefType 0x2ff -#define MSR_MC0_CTL 0x400 -#define MSR_MC0_STATUS 0x401 -#define MSR_MC0_ADDR 0x402 -#define MSR_MC0_MISC 0x403 -#define MSR_MC1_CTL 0x404 -#define MSR_MC1_STATUS 0x405 -#define MSR_MC1_ADDR 0x406 -#define MSR_MC1_MISC 0x407 -#define MSR_MC2_CTL 0x408 -#define MSR_MC2_STATUS 0x409 -#define MSR_MC2_ADDR 0x40a -#define MSR_MC2_MISC 0x40b -#define MSR_MC3_CTL 0x40c -#define MSR_MC3_STATUS 0x40d -#define MSR_MC3_ADDR 0x40e -#define MSR_MC3_MISC 0x40f -#define MSR_MC4_CTL 0x410 -#define MSR_MC4_STATUS 0x411 -#define MSR_MC4_ADDR 0x412 -#define MSR_MC4_MISC 0x413 - -/* - * Constants related to MSR's. - */ -#define APICBASE_RESERVED 0x000006ff -#define APICBASE_BSP 0x00000100 -#define APICBASE_ENABLED 0x00000800 -#define APICBASE_ADDRESS 0xfffff000 - -/* - * PAT modes. - */ -#define PAT_UNCACHEABLE 0x00 -#define PAT_WRITE_COMBINING 0x01 -#define PAT_WRITE_THROUGH 0x04 -#define PAT_WRITE_PROTECTED 0x05 -#define PAT_WRITE_BACK 0x06 -#define PAT_UNCACHED 0x07 -#define PAT_VALUE(i, m) ((long)(m) << (8 * (i))) -#define PAT_MASK(i) PAT_VALUE(i, 0xff) - -/* - * Constants related to MTRRs - */ -#define MTRR_UNCACHEABLE 0x00 -#define MTRR_WRITE_COMBINING 0x01 -#define MTRR_WRITE_THROUGH 0x04 -#define MTRR_WRITE_PROTECTED 0x05 -#define MTRR_WRITE_BACK 0x06 -#define MTRR_N64K 8 /* numbers of fixed-size entries */ -#define MTRR_N16K 16 -#define MTRR_N4K 64 -#define MTRR_CAP_WC 0x0000000000000400 -#define MTRR_CAP_FIXED 0x0000000000000100 -#define MTRR_CAP_VCNT 0x00000000000000ff -#define MTRR_DEF_ENABLE 0x0000000000000800 -#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 -#define MTRR_DEF_TYPE 0x00000000000000ff -#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 -#define MTRR_PHYSBASE_TYPE 0x00000000000000ff -#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 -#define MTRR_PHYSMASK_VALID 0x0000000000000800 - -/* Performance Control Register (5x86 only). */ -#define PCR0 0x20 -#define PCR0_RSTK 0x01 /* Enables return stack */ -#define PCR0_BTB 0x02 /* Enables branch target buffer */ -#define PCR0_LOOP 0x04 /* Enables loop */ -#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to - serialize pipe. */ -#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ -#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ -#define PCR0_LSSER 0x80 /* Disable reorder */ - -/* Device Identification Registers */ -#define DIR0 0xfe -#define DIR1 0xff - -/* - * Machine Check register constants. - */ -#define MCG_CAP_COUNT 0x000000ff -#define MCG_CAP_CTL_P 0x00000100 -#define MCG_CAP_EXT_P 0x00000200 -#define MCG_CAP_CMCI_P 0x00000400 -#define MCG_CAP_TES_P 0x00000800 -#define MCG_CAP_EXT_CNT 0x00ff0000 -#define MCG_CAP_SER_P 0x01000000 -#define MCG_STATUS_RIPV 0x00000001 -#define MCG_STATUS_EIPV 0x00000002 -#define MCG_STATUS_MCIP 0x00000004 -#define MCG_CTL_ENABLE 0xffffffffffffffff -#define MCG_CTL_DISABLE 0x0000000000000000 -#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) -#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) -#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) -#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) -#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ -#define MC_STATUS_MCA_ERROR 0x000000000000ffff -#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 -#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 -#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ -#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ -#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ -#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ -#define MC_STATUS_PCC 0x0200000000000000 -#define MC_STATUS_ADDRV 0x0400000000000000 -#define MC_STATUS_MISCV 0x0800000000000000 -#define MC_STATUS_EN 0x1000000000000000 -#define MC_STATUS_UC 0x2000000000000000 -#define MC_STATUS_OVER 0x4000000000000000 -#define MC_STATUS_VAL 0x8000000000000000 -#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ -#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ -#define MC_CTL2_THRESHOLD 0x0000000000007fff -#define MC_CTL2_CMCI_EN 0x0000000040000000 - -/* - * The following four 3-byte registers control the non-cacheable regions. - * These registers must be written as three separate bytes. - * - * NCRx+0: A31-A24 of starting address - * NCRx+1: A23-A16 of starting address - * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. - * - * The non-cacheable region's starting address must be aligned to the - * size indicated by the NCR_SIZE_xx field. - */ -#define NCR1 0xc4 -#define NCR2 0xc7 -#define NCR3 0xca -#define NCR4 0xcd - -#define NCR_SIZE_0K 0 -#define NCR_SIZE_4K 1 -#define NCR_SIZE_8K 2 -#define NCR_SIZE_16K 3 -#define NCR_SIZE_32K 4 -#define NCR_SIZE_64K 5 -#define NCR_SIZE_128K 6 -#define NCR_SIZE_256K 7 -#define NCR_SIZE_512K 8 -#define NCR_SIZE_1M 9 -#define NCR_SIZE_2M 10 -#define NCR_SIZE_4M 11 -#define NCR_SIZE_8M 12 -#define NCR_SIZE_16M 13 -#define NCR_SIZE_32M 14 -#define NCR_SIZE_4G 15 - -/* - * The address region registers are used to specify the location and - * size for the eight address regions. - * - * ARRx + 0: A31-A24 of start address - * ARRx + 1: A23-A16 of start address - * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx - */ -#define ARR0 0xc4 -#define ARR1 0xc7 -#define ARR2 0xca -#define ARR3 0xcd -#define ARR4 0xd0 -#define ARR5 0xd3 -#define ARR6 0xd6 -#define ARR7 0xd9 - -#define ARR_SIZE_0K 0 -#define ARR_SIZE_4K 1 -#define ARR_SIZE_8K 2 -#define ARR_SIZE_16K 3 -#define ARR_SIZE_32K 4 -#define ARR_SIZE_64K 5 -#define ARR_SIZE_128K 6 -#define ARR_SIZE_256K 7 -#define ARR_SIZE_512K 8 -#define ARR_SIZE_1M 9 -#define ARR_SIZE_2M 10 -#define ARR_SIZE_4M 11 -#define ARR_SIZE_8M 12 -#define ARR_SIZE_16M 13 -#define ARR_SIZE_32M 14 -#define ARR_SIZE_4G 15 - -/* - * The region control registers specify the attributes associated with - * the ARRx addres regions. - */ -#define RCR0 0xdc -#define RCR1 0xdd -#define RCR2 0xde -#define RCR3 0xdf -#define RCR4 0xe0 -#define RCR5 0xe1 -#define RCR6 0xe2 -#define RCR7 0xe3 - -#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ -#define RCR_RCE 0x01 /* Enables caching for ARR7. */ -#define RCR_WWO 0x02 /* Weak write ordering. */ -#define RCR_WL 0x04 /* Weak locking. */ -#define RCR_WG 0x08 /* Write gathering. */ -#define RCR_WT 0x10 /* Write-through. */ -#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ - -/* AMD Write Allocate Top-Of-Memory and Control Register */ -#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ -#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ -#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ - -/* AMD64 MSR's */ -#define MSR_EFER 0xc0000080 /* extended features */ -#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ -#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ -#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ -#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ -#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ -#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ -#define MSR_PERFEVSEL0 0xc0010000 -#define MSR_PERFEVSEL1 0xc0010001 -#define MSR_PERFEVSEL2 0xc0010002 -#define MSR_PERFEVSEL3 0xc0010003 -#undef MSR_PERFCTR0 -#undef MSR_PERFCTR1 -#define MSR_PERFCTR0 0xc0010004 -#define MSR_PERFCTR1 0xc0010005 -#define MSR_PERFCTR2 0xc0010006 -#define MSR_PERFCTR3 0xc0010007 -#define MSR_SYSCFG 0xc0010010 -#define MSR_HWCR 0xc0010015 -#define MSR_IORRBASE0 0xc0010016 -#define MSR_IORRMASK0 0xc0010017 -#define MSR_IORRBASE1 0xc0010018 -#define MSR_IORRMASK1 0xc0010019 -#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ -#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ -#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ -#define MSR_MC0_CTL_MASK 0xc0010044 - -/* VIA ACE crypto featureset: for via_feature_rng */ -#define VIA_HAS_RNG 1 /* cpu has RNG */ - -/* VIA ACE crypto featureset: for via_feature_xcrypt */ -#define VIA_HAS_AES 1 /* cpu has AES */ -#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ -#define VIA_HAS_MM 4 /* cpu has RSA instructions */ -#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ - -/* Centaur Extended Feature flags */ -#define VIA_CPUID_HAS_RNG 0x000004 -#define VIA_CPUID_DO_RNG 0x000008 -#define VIA_CPUID_HAS_ACE 0x000040 -#define VIA_CPUID_DO_ACE 0x000080 -#define VIA_CPUID_HAS_ACE2 0x000100 -#define VIA_CPUID_DO_ACE2 0x000200 -#define VIA_CPUID_HAS_PHE 0x000400 -#define VIA_CPUID_DO_PHE 0x000800 -#define VIA_CPUID_HAS_PMM 0x001000 -#define VIA_CPUID_DO_PMM 0x002000 - -/* VIA ACE xcrypt-* instruction context control options */ -#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f -#define VIA_CRYPT_CWLO_ALG_M 0x00000070 -#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 -#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 -#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 -#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 -#define VIA_CRYPT_CWLO_NORMAL 0x00000000 -#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 -#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 -#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 -#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ -#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ -#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ - -#endif /* !_MACHINE_SPECIALREG_H_ */ +#include -- cgit v1.1 From fee85d364e5ebc10f4a95df0ba963b173e5b9c8f Mon Sep 17 00:00:00 2001 From: tijl Date: Mon, 19 Mar 2012 21:57:31 +0000 Subject: Copy amd64 sysarch.h to x86 and merge with i386 sysarch.h. Replace amd64/i386/pc98 sysarch.h with stubs. --- sys/amd64/include/sysarch.h | 103 ++------------------------------------------ 1 file changed, 3 insertions(+), 100 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/sysarch.h b/sys/amd64/include/sysarch.h index 195d882..cd380d4 100644 --- a/sys/amd64/include/sysarch.h +++ b/sys/amd64/include/sysarch.h @@ -1,103 +1,6 @@ /*- - * Copyright (c) 1993 The Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ + * This file is in the public domain. */ +/* $FreeBSD$ */ -/* - * Architecture specific syscalls (AMD64) - */ -#ifndef _MACHINE_SYSARCH_H_ -#define _MACHINE_SYSARCH_H_ - -#include - -#define I386_GET_LDT 0 -#define I386_SET_LDT 1 -#define LDT_AUTO_ALLOC 0xffffffff - /* I386_IOPL */ -#define I386_GET_IOPERM 3 -#define I386_SET_IOPERM 4 - -/* XXX Not implementable #define I386_VM86 6 */ - -#define I386_GET_FSBASE 7 -#define I386_SET_FSBASE 8 -#define I386_GET_GSBASE 9 -#define I386_SET_GSBASE 10 -#define I386_GET_XFPUSTATE 11 - -/* Leave space for 0-127 for to avoid translating syscalls */ -#define AMD64_GET_FSBASE 128 -#define AMD64_SET_FSBASE 129 -#define AMD64_GET_GSBASE 130 -#define AMD64_SET_GSBASE 131 -#define AMD64_GET_XFPUSTATE 132 - -struct i386_ldt_args { - unsigned int start; - struct user_segment_descriptor *descs __packed; - unsigned int num; -}; - -struct i386_ioperm_args { - unsigned int start; - unsigned int length; - int enable; -}; - -struct i386_get_xfpustate { - unsigned int addr; - int len; -}; - -struct amd64_get_xfpustate { - void *addr; - int len; -}; - -#ifndef _KERNEL -__BEGIN_DECLS -int amd64_get_fsbase(void **); -int amd64_get_gsbase(void **); -int amd64_set_fsbase(void *); -int amd64_set_gsbase(void *); -int sysarch(int, void *); -__END_DECLS -#else -struct thread; -union descriptor; - -int amd64_get_ldt(struct thread *, struct i386_ldt_args *); -int amd64_set_ldt(struct thread *, struct i386_ldt_args *, - struct user_segment_descriptor *); -int amd64_get_ioperm(struct thread *, struct i386_ioperm_args *); -int amd64_set_ioperm(struct thread *, struct i386_ioperm_args *); -#endif - -#endif /* !_MACHINE_SYSARCH_H_ */ +#include -- cgit v1.1 From e02fd6b8423e63f1fdbfc1f984d7c7291a1bacd1 Mon Sep 17 00:00:00 2001 From: alc Date: Thu, 22 Mar 2012 04:52:51 +0000 Subject: Handle spurious page faults that may occur in no-fault sections of the kernel. When access restrictions are added to a page table entry, we flush the corresponding virtual address mapping from the TLB. In contrast, when access restrictions are removed from a page table entry, we do not flush the virtual address mapping from the TLB. This is exactly as recommended in AMD's documentation. In effect, when access restrictions are removed from a page table entry, AMD's MMUs will transparently refresh a stale TLB entry. In short, this saves us from having to perform potentially costly TLB flushes. In contrast, Intel's MMUs are allowed to generate a spurious page fault based upon the stale TLB entry. Usually, such spurious page faults are handled by vm_fault() without incident. However, when we are executing no-fault sections of the kernel, we are not allowed to execute vm_fault(). This change introduces special-case handling for spurious page faults that occur in no-fault sections of the kernel. In collaboration with: kib Tested by: gibbs (an earlier version) I would also like to acknowledge Hiroki Sato's assistance in diagnosing this problem. MFC after: 1 week --- sys/amd64/include/proc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/proc.h b/sys/amd64/include/proc.h index 5207d89..14585fb 100644 --- a/sys/amd64/include/proc.h +++ b/sys/amd64/include/proc.h @@ -46,6 +46,7 @@ struct proc_ldt { struct mdthread { int md_spinlock_count; /* (k) */ register_t md_saved_flags; /* (k) */ + register_t md_spurflt_addr; /* (k) Spurious page fault address. */ }; struct mdproc { -- cgit v1.1 From 5edfb77dd3a164bb9d2d40c6604faa6c9f3dce15 Mon Sep 17 00:00:00 2001 From: fabient Date: Wed, 28 Mar 2012 20:58:30 +0000 Subject: Add software PMC support. New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month --- sys/amd64/include/pmc_mdep.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/pmc_mdep.h b/sys/amd64/include/pmc_mdep.h index 4f16485..73c93fe 100644 --- a/sys/amd64/include/pmc_mdep.h +++ b/sys/amd64/include/pmc_mdep.h @@ -50,13 +50,13 @@ struct pmc_mdep; * measurement architecture have PMCs of the following classes: TSC, * IAF, IAP, UCF and UCP. */ -#define PMC_MDEP_CLASS_INDEX_TSC 0 -#define PMC_MDEP_CLASS_INDEX_K8 1 -#define PMC_MDEP_CLASS_INDEX_P4 1 -#define PMC_MDEP_CLASS_INDEX_IAP 1 -#define PMC_MDEP_CLASS_INDEX_IAF 2 -#define PMC_MDEP_CLASS_INDEX_UCP 3 -#define PMC_MDEP_CLASS_INDEX_UCF 4 +#define PMC_MDEP_CLASS_INDEX_TSC 1 +#define PMC_MDEP_CLASS_INDEX_K8 2 +#define PMC_MDEP_CLASS_INDEX_P4 2 +#define PMC_MDEP_CLASS_INDEX_IAP 2 +#define PMC_MDEP_CLASS_INDEX_IAF 3 +#define PMC_MDEP_CLASS_INDEX_UCP 4 +#define PMC_MDEP_CLASS_INDEX_UCF 5 /* * On the amd64 platform we support the following PMCs. @@ -119,6 +119,15 @@ union pmc_md_pmc { #define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS) +/* Build a fake kernel trapframe from current instruction pointer. */ +#define PMC_FAKE_TRAPFRAME(TF) \ + do { \ + (TF)->tf_cs = 0; (TF)->tf_rflags = 0; \ + __asm __volatile("movq %%rbp,%0" : "=r" ((TF)->tf_rbp)); \ + __asm __volatile("movq %%rsp,%0" : "=r" ((TF)->tf_rsp)); \ + __asm __volatile("call 1f \n\t1: pop %0" : "=r"((TF)->tf_rip)); \ + } while (0) + /* * Prototypes */ -- cgit v1.1 From 98fa920cd519a461bb15b9a966b79df86f036f15 Mon Sep 17 00:00:00 2001 From: jhb Date: Thu, 29 Mar 2012 16:51:22 +0000 Subject: - Rename VM_MEMATTR_UNCACHED to VM_MEMATTR_WEAK_UNCACHEABLE on x86 to be less ambiguous and more clearly identify what it means. This attribute is what Intel refers to as UC-, and it's only difference relative to normal UC memory is that a WC MTRR will override a UC- PAT entry causing the memory to be treated as WC, whereas a UC PAT entry will always override the MTRR. - Remove the VM_MEMATTR_UNCACHED alias from powerpc. --- sys/amd64/include/vm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/vm.h b/sys/amd64/include/vm.h index 4065a36..6573e37 100644 --- a/sys/amd64/include/vm.h +++ b/sys/amd64/include/vm.h @@ -38,7 +38,7 @@ #define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)PAT_WRITE_THROUGH) #define VM_MEMATTR_WRITE_PROTECTED ((vm_memattr_t)PAT_WRITE_PROTECTED) #define VM_MEMATTR_WRITE_BACK ((vm_memattr_t)PAT_WRITE_BACK) -#define VM_MEMATTR_UNCACHED ((vm_memattr_t)PAT_UNCACHED) +#define VM_MEMATTR_WEAK_UNCACHEABLE ((vm_memattr_t)PAT_UNCACHED) #define VM_MEMATTR_DEFAULT VM_MEMATTR_WRITE_BACK -- cgit v1.1 From 876e74a14e5e797af724083627fdae328d77d62a Mon Sep 17 00:00:00 2001 From: jhb Date: Thu, 29 Mar 2012 19:03:22 +0000 Subject: Use a more proper fix for enabling HT MSI mapping windows on Host-PCI bridges. Rather than blindly enabling the windows on all of them, only enable the window when an MSI interrupt is enabled for a device behind the bridge, similar to what already happens for HT PCI-PCI bridges. To implement this, each x86 Host-PCI bridge driver has to be able to locate it's actual backing device on bus 0. For ACPI, use the _ADR method to find the slot and function of the device. For the non-ACPI case, the legacy(4) driver already scans bus 0 looking for Host-PCI bridge devices. Now it saves the slot and function of each bridge that it finds as ivars that the Host-PCI bridge driver can then use in its pcib_map_msi() method. This fixes machines where non-MSI interrupts were broken by the previous round of HT MSI changes. Tested by: bapt MFC after: 1 week --- sys/amd64/include/legacyvar.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/legacyvar.h b/sys/amd64/include/legacyvar.h index 12a2864..8116db0 100644 --- a/sys/amd64/include/legacyvar.h +++ b/sys/amd64/include/legacyvar.h @@ -31,7 +31,9 @@ enum legacy_device_ivars { LEGACY_IVAR_PCIDOMAIN, - LEGACY_IVAR_PCIBUS + LEGACY_IVAR_PCIBUS, + LEGACY_IVAR_PCISLOT, + LEGACY_IVAR_PCIFUNC }; #define LEGACY_ACCESSOR(var, ivar, type) \ @@ -39,6 +41,8 @@ enum legacy_device_ivars { LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t) LEGACY_ACCESSOR(pcibus, PCIBUS, uint32_t) +LEGACY_ACCESSOR(pcislot, PCISLOT, int) +LEGACY_ACCESSOR(pcifunc, PCIFUNC, int) #undef LEGACY_ACCESSOR @@ -53,5 +57,7 @@ int legacy_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value); struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags); +int legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, + uint64_t *addr, uint32_t *data); #endif /* !_MACHINE_LEGACYVAR_H_ */ -- cgit v1.1 From 1dd88fec2f6597efdfc693ade6e17b4a47b033c3 Mon Sep 17 00:00:00 2001 From: jhb Date: Fri, 30 Mar 2012 19:10:14 +0000 Subject: Move the legacy(4) driver to x86. --- sys/amd64/include/legacyvar.h | 63 ------------------------------------------- 1 file changed, 63 deletions(-) delete mode 100644 sys/amd64/include/legacyvar.h (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/legacyvar.h b/sys/amd64/include/legacyvar.h deleted file mode 100644 index 8116db0..0000000 --- a/sys/amd64/include/legacyvar.h +++ /dev/null @@ -1,63 +0,0 @@ -/*- - * Copyright (c) 2000 Peter Wemm - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _MACHINE_LEGACYVAR_H_ -#define _MACHINE_LEGACYVAR_H_ - -enum legacy_device_ivars { - LEGACY_IVAR_PCIDOMAIN, - LEGACY_IVAR_PCIBUS, - LEGACY_IVAR_PCISLOT, - LEGACY_IVAR_PCIFUNC -}; - -#define LEGACY_ACCESSOR(var, ivar, type) \ - __BUS_ACCESSOR(legacy, var, LEGACY, ivar, type) - -LEGACY_ACCESSOR(pcidomain, PCIDOMAIN, uint32_t) -LEGACY_ACCESSOR(pcibus, PCIBUS, uint32_t) -LEGACY_ACCESSOR(pcislot, PCISLOT, int) -LEGACY_ACCESSOR(pcifunc, PCIFUNC, int) - -#undef LEGACY_ACCESSOR - -int legacy_pcib_maxslots(device_t dev); -uint32_t legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, - u_int func, u_int reg, int bytes); -int legacy_pcib_read_ivar(device_t dev, device_t child, int which, - uintptr_t *result); -void legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, - u_int func, u_int reg, uint32_t data, int bytes); -int legacy_pcib_write_ivar(device_t dev, device_t child, int which, - uintptr_t value); -struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child, - int type, int *rid, u_long start, u_long end, u_long count, u_int flags); -int legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, - uint64_t *addr, uint32_t *data); - -#endif /* !_MACHINE_LEGACYVAR_H_ */ -- cgit v1.1 From 3e4fba4c321faeac172654f57e0c6b03a3de1a12 Mon Sep 17 00:00:00 2001 From: avg Date: Fri, 13 Apr 2012 07:15:40 +0000 Subject: bump INTRCNT_COUNT values to reflect actual numbers of IPI counters Maybe the numbers should be conditionalized on COUNT_IPIS Reviewed by: jhb MFC after: 1 week --- sys/amd64/include/intr_machdep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sys/amd64/include') diff --git a/sys/amd64/include/intr_machdep.h b/sys/amd64/include/intr_machdep.h index 6cd4eee..700e35f 100644 --- a/sys/amd64/include/intr_machdep.h +++ b/sys/amd64/include/intr_machdep.h @@ -60,10 +60,10 @@ * - 1 ??? dummy counter. * - 2 counters for each I/O interrupt. * - 1 counter for each CPU for lapic timer. - * - 7 counters for each CPU for IPI counters for SMP. + * - 8 counters for each CPU for IPI counters for SMP. */ #ifdef SMP -#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) +#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 8) * MAXCPU) #else #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) #endif -- cgit v1.1