From 872b317d89fc2a1a202495e2d8321c2c50b36f8c Mon Sep 17 00:00:00 2001 From: kib Date: Thu, 1 Nov 2012 15:14:37 +0000 Subject: Provide the reading and display of the Standard Extended Features, introduced with the IvyBridge CPUs. Provide the definitions for new bits in CR3 and CR4 registers. Tested by: avg, Michael Moll MFC after: 2 weeks --- sys/amd64/amd64/initcpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sys/amd64/amd64/initcpu.c') diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index dbeaec6..148b1ec 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -72,6 +72,7 @@ u_int cpu_vendor_id; /* CPU vendor ID */ u_int cpu_fxsr; /* SSE enabled */ u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ u_int cpu_clflush_line_size = 32; +u_int cpu_stdext_feature; u_int cpu_max_ext_state_size; SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, -- cgit v1.1