From adbadeedc1436461332343fdb618f844de5fca51 Mon Sep 17 00:00:00 2001 From: dfr Date: Mon, 10 Aug 1998 07:53:59 +0000 Subject: Lots of changes, including: * Support for AlphaStation 200, 250, 255, 400 * Untested support for UDB, Multia, AXPpci33 (Noname) * Support for Personal Workstation 433a/433au, 500a/500au, 600a/600au (Miata) * Some minor fixes and improvements to interrupt handling. Submitted by: Andrew Gallatin (AS200, Miata) Obtained from: NetBSD (some code for AS200, Miata, Noname) --- sys/alpha/pci/apecs.c | 488 +++++++++++++++++++++++++++++++++++++++++++++++ sys/alpha/pci/apecsreg.h | 343 +++++++++++++++++++++++++++++++++ sys/alpha/pci/apecsvar.h | 30 +++ sys/alpha/pci/cia.c | 61 ++---- sys/alpha/pci/lca.c | 371 +++++++++++++++++++++++++++++++++++ sys/alpha/pci/lcareg.h | 95 +++++++++ sys/alpha/pci/lcavar.h | 29 +++ sys/alpha/pci/pcibus.c | 9 +- 8 files changed, 1378 insertions(+), 48 deletions(-) create mode 100644 sys/alpha/pci/apecs.c create mode 100644 sys/alpha/pci/apecsreg.h create mode 100644 sys/alpha/pci/apecsvar.h create mode 100644 sys/alpha/pci/lca.c create mode 100644 sys/alpha/pci/lcareg.h create mode 100644 sys/alpha/pci/lcavar.h (limited to 'sys/alpha/pci') diff --git a/sys/alpha/pci/apecs.c b/sys/alpha/pci/apecs.c new file mode 100644 index 0000000..4043fd3 --- /dev/null +++ b/sys/alpha/pci/apecs.c @@ -0,0 +1,488 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: cia.c,v 1.3 1998/07/22 08:32:17 dfr Exp $ + */ +/* + * Copyright (c) 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ +/* + * Additional Copyright (c) 1998 by Andrew Gallatin for Duke University + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t apecs_devclass; +static device_t apecs0; /* XXX only one for now */ +static device_t isa0; + +struct apecs_softc { + vm_offset_t dmem_base; /* dense memory */ + vm_offset_t smem_base; /* sparse memory */ + vm_offset_t io_base; /* dense i/o */ + vm_offset_t cfg0_base; /* dense pci0 config */ + vm_offset_t cfg1_base; /* dense pci1 config */ +}; + +#define APECS_SOFTC(dev) (struct apecs_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t apecs_swiz_inb; +static alpha_chipset_inw_t apecs_swiz_inw; +static alpha_chipset_inl_t apecs_swiz_inl; +static alpha_chipset_outb_t apecs_swiz_outb; +static alpha_chipset_outw_t apecs_swiz_outw; +static alpha_chipset_outl_t apecs_swiz_outl; +static alpha_chipset_readb_t apecs_swiz_readb; +static alpha_chipset_readw_t apecs_swiz_readw; +static alpha_chipset_readl_t apecs_swiz_readl; +static alpha_chipset_writeb_t apecs_swiz_writeb; +static alpha_chipset_writew_t apecs_swiz_writew; +static alpha_chipset_writel_t apecs_swiz_writel; +static alpha_chipset_maxdevs_t apecs_swiz_maxdevs; +static alpha_chipset_cfgreadb_t apecs_swiz_cfgreadb; +static alpha_chipset_cfgreadw_t apecs_swiz_cfgreadw; +static alpha_chipset_cfgreadl_t apecs_swiz_cfgreadl; +static alpha_chipset_cfgwriteb_t apecs_swiz_cfgwriteb; +static alpha_chipset_cfgwritew_t apecs_swiz_cfgwritew; +static alpha_chipset_cfgwritel_t apecs_swiz_cfgwritel; + +static alpha_chipset_t apecs_swiz_chipset = { + apecs_swiz_inb, + apecs_swiz_inw, + apecs_swiz_inl, + apecs_swiz_outb, + apecs_swiz_outw, + apecs_swiz_outl, + apecs_swiz_readb, + apecs_swiz_readw, + apecs_swiz_readl, + apecs_swiz_writeb, + apecs_swiz_writew, + apecs_swiz_writel, + apecs_swiz_maxdevs, + apecs_swiz_cfgreadb, + apecs_swiz_cfgreadw, + apecs_swiz_cfgreadl, + apecs_swiz_cfgwriteb, + apecs_swiz_cfgwritew, + apecs_swiz_cfgwritel, +}; + +static int +apecs_swiz_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + + + +static u_int8_t +apecs_swiz_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(APECS_PCI_SIO), port); +} + +static u_int16_t +apecs_swiz_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(APECS_PCI_SIO), port); +} + +static u_int32_t +apecs_swiz_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(APECS_PCI_SIO), port); +} + +static void +apecs_swiz_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +apecs_swiz_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(APECS_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * Memory functions. + * + * XXX linux does 32-bit reads/writes via dense space. This doesn't + * appear to work for devices behind a ppb. I'm using sparse + * accesses & they appear to work just fine everywhere. + */ + +static u_int32_t apecs_hae_mem; + +#define REG1 (1UL << 24) +static __inline void +apecs_swiz_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != apecs_hae_mem) { + apecs_hae_mem = msb; + REGVAL(EPIC_HAXR1) = apecs_hae_mem; + alpha_mb(); + apecs_hae_mem = REGVAL(EPIC_HAXR1); + } + splx(s); + } +} + +static u_int8_t +apecs_swiz_readb(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(APECS_PCI_SPARSE), pa); +} + +static u_int16_t +apecs_swiz_readw(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(APECS_PCI_SPARSE), pa); +} + +static u_int32_t +apecs_swiz_readl(u_int32_t pa) +{ + alpha_mb(); + apecs_swiz_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(APECS_PCI_SPARSE), pa); +} + +static void +apecs_swiz_writeb(u_int32_t pa, u_int8_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +apecs_swiz_writew(u_int32_t pa, u_int16_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); +} + + +static void +apecs_swiz_writel(u_int32_t pa, u_int32_t data) +{ + apecs_swiz_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(APECS_PCI_SPARSE), pa, data); + alpha_wmb(); + +} + + +#define APECS_SWIZ_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define APECS_TYPE1_SETUP(b,s,old_haxr2) if((b)) { \ + do { \ + (s) = splhigh(); \ + (old_haxr2) = REGVAL(EPIC_HAXR2); \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2) | 0x1; \ + alpha_mb(); \ + } while(0); \ +} + +#define APECS_TYPE1_TEARDOWN(b,s,old_haxr2) if((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(EPIC_HAXR2) = (old_haxr2); \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define SWIZ_CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return val; + +#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + u_int32_t old_haxr2 = 0; \ + struct apecs_softc* sc = APECS_SOFTC(apecs0); \ + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + alpha_mb(); \ + APECS_TYPE1_SETUP(b,ipl,old_haxr2); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + APECS_TYPE1_TEARDOWN(b,ipl,old_haxr2); \ + return; + +#if 1 +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t); +} + +#else +static u_int8_t +apecs_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return ~0; + return SPARSE_READ_BYTE(sc->cfg0_base, off); +} + +static u_int16_t +apecs_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return ~0; + return SPARSE_READ_WORD(sc->cfg0_base, off); +} + +static u_int32_t +apecs_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + alpha_mb(); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return ~0; + return SPARSE_READ_LONG(sc->cfg0_base, off); +} + +static void +apecs_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_BYTE_OFFSET(off)), 1)) return; + SPARSE_WRITE_BYTE(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_WORD_OFFSET(off)), 2)) return; + SPARSE_WRITE_WORD(sc->cfg0_base, off, data); + alpha_wmb(); +} + +static void +apecs_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + struct apecs_softc* sc = APECS_SOFTC(apecs0); + vm_offset_t off = APECS_SWIZ_CFGOFF(b, s, f, r); + if (badaddr((caddr_t)(sc->cfg0_base + SPARSE_LONG_OFFSET(off)), 4)) return; + SPARSE_WRITE_LONG(sc->cfg0_base, off, data); + alpha_wmb(); +} +#endif + +static int apecs_probe(device_t dev); +static int apecs_attach(device_t dev); +static void *apecs_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int apecs_connect_intr(device_t dev, void* ih); + +static device_method_t apecs_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, apecs_probe), + DEVMETHOD(device_attach, apecs_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t apecs_driver = { + "apecs", + apecs_methods, + DRIVER_TYPE_MISC, + sizeof(struct apecs_softc), +}; + +void +apecs_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = apecs_swiz_chipset; +} + +static int +apecs_probe(device_t dev) +{ + int memwidth; + if (apecs0) + return ENXIO; + apecs0 = dev; + memwidth = (REGVAL(COMANCHE_GCR) & COMANCHE_GCR_WIDEMEM) != 0 ? 128 : 64; + if(memwidth == 64){ + device_set_desc(dev, "DECchip 21071 Core Logic chipset"); + } else { + device_set_desc(dev, "DECchip 21072 Core Logic chipset"); + } + apecs_hae_mem = REGVAL(EPIC_HAXR1); + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +extern void isa_intr(void* frame, u_long vector); + +static int +apecs_attach(device_t dev) +{ + struct apecs_softc* sc = APECS_SOFTC(dev); + apecs_init(); + chipset.intrdev = isa0; + + sc->dmem_base = APECS_PCI_DENSE; + sc->smem_base = APECS_PCI_SPARSE; + sc->io_base = APECS_PCI_SIO; + sc->cfg0_base = KV(APECS_PCI_CONF); + sc->cfg1_base = NULL; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0); + diff --git a/sys/alpha/pci/apecsreg.h b/sys/alpha/pci/apecsreg.h new file mode 100644 index 0000000..66e2c5e --- /dev/null +++ b/sys/alpha/pci/apecsreg.h @@ -0,0 +1,343 @@ +/* $NetBSD: apecsreg.h,v 1.7 1997/06/06 23:54:24 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * APECS Chipset registers and constants. + * + * Taken from ``DECchip 21071 and DECchip 21072 Core Logic Chipsets Data + * Sheet'' (DEC order number EC-QAEMA-TE), pages 4-1 - 4-27, 10-21 - 10-38. + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define COMANCHE_BASE 0x180000000L /* 21071-CA Regs */ +#define EPIC_BASE 0x1a0000000L /* 21071-DA Regs */ +#define APECS_PCI_IACK 0x1b0000000L /* PCI Int. Ack. */ +#define APECS_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define APECS_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define APECS_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define APECS_PCI_DENSE 0x300000000L /* PCI Dense Space */ + + +/* + * 21071-CA Registers + */ + +/* + * 21071-CA General Registers + */ +#define COMANCHE_GCR (COMANCHE_BASE + 0x0000) /* General Control */ +#define COMANCHE_GCR_RSVD 0xc009 +#define COMANCHE_GCR_SYSARB 0x0006 +#define COMANCHE_GCR_WIDEMEM 0x0010 +#define COMANCHE_GCR_BC_EN 0x0020 +#define COMANCHE_GCR_BC_NOALLOC 0x0040 +#define COMANCHE_GCR_BC_LONGWR 0x0080 +#define COMANCHE_GCR_BC_IGNTAG 0x0100 +#define COMANCHE_GCR_BC_FRCTAG 0x0200 +#define COMANCHE_GCR_BC_FRCD 0x0400 +#define COMANCHE_GCR_BC_FRCV 0x0800 +#define COMANCHE_GCR_BC_FRCP 0x1000 +#define COMANCHE_GCR_BC_BADAP 0x2000 + +#define COMANCHE_RSVD (COMANCHE_BASE + 0x0020) /* Reserved */ + +#define COMANCHE_ED (COMANCHE_BASE + 0x0040) /* Err & Diag Status */ +#define COMANCHE_ED_LOSTERR 0x0001 +#define COMANCHE_ED_BC_TAPERR 0x0002 +#define COMANCHE_ED_BC_TCPERR 0x0004 +#define COMANCHE_ED_NXMERR 0x0008 +#define COMANCHE_ED_DMACAUSE 0x0010 +#define COMANCHE_ED_VICCAUSE 0x0020 +#define COMANCHE_ED_CREQCAUSE 0x01c0 +#define COMANCHE_ED_RSVD 0x1e00 +#define COMANCHE_ED_PASS2 0x2000 +#define COMANCHE_ED_IDXLLOCK 0x4000 +#define COMANCHE_ED_WRPEND 0x8000 + +#define COMANCHE_TAGENB (COMANCHE_BASE + 0x0060) /* Tag Enable */ +#define COMANCHE_TAGENB_RSVD 0x0001 + +#define COMANCHE_TAGENB_C_4G 0x0000 +#define COMANCHE_TAGENB_C_2G 0x8000 +#define COMANCHE_TAGENB_C_1G 0xc000 +#define COMANCHE_TAGENB_C_512M 0xe000 +#define COMANCHE_TAGENB_C_256M 0xf000 +#define COMANCHE_TAGENB_C_128M 0xf800 +#define COMANCHE_TAGENB_C_64M 0xfc00 +#define COMANCHE_TAGENB_C_32M 0xfe00 +#define COMANCHE_TAGENB_C_16M 0xff00 +#define COMANCHE_TAGENB_C_8M 0xff80 +#define COMANCHE_TAGENB_C_4M 0xffc0 +#define COMANCHE_TAGENB_C_2M 0xffe0 +#define COMANCHE_TAGENB_C_1M 0xfff0 +#define COMANCHE_TAGENB_C_512K 0xfff8 +#define COMANCHE_TAGENB_C_256K 0xfffc +#define COMANCHE_TAGENB_C_128K 0xfffe + +#define COMANCHE_TAGENB_M_4G 0xffff +#define COMANCHE_TAGENB_M_2G 0x7fff +#define COMANCHE_TAGENB_M_1G 0x3fff +#define COMANCHE_TAGENB_M_512M 0x1fff +#define COMANCHE_TAGENB_M_256M 0x0fff +#define COMANCHE_TAGENB_M_128M 0x07ff +#define COMANCHE_TAGENB_M_64M 0x03ff +#define COMANCHE_TAGENB_M_32M 0x01ff +#define COMANCHE_TAGENB_M_16M 0x00ff +#define COMANCHE_TAGENB_M_8M 0x007f +#define COMANCHE_TAGENB_M_4M 0x003f +#define COMANCHE_TAGENB_M_2M 0x001f +#define COMANCHE_TAGENB_M_1M 0x000e +#define COMANCHE_TAGENB_M_512K 0x0006 +#define COMANCHE_TAGENB_M_256K 0x0002 +#define COMANCHE_TAGENB_M_128K 0x0000 + +#define COMANCHE_ERR_LO (COMANCHE_BASE + 0x0080) /* Error Low Address */ + +#define COMANCHE_ERR_HI (COMANCHE_BASE + 0x00a0) /* Error High Address */ +#define COMANCHE_ERR_HI_RSVD 0xe000 + +#define COMANCHE_LCK_LO (COMANCHE_BASE + 0x00c0) /* LDx_L Low Address */ + +#define COMANCHE_LCK_HI (COMANCHE_BASE + 0x00e0) /* LDx_L High Address */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +/* + * 21071-CA Memory Registers + */ +#define COMANCHE_GTIM (COMANCHE_BASE + 0x0200) /* Global Timing */ +#define COMANCHE_LOCK_HI_RSVD 0xe000 + +#define COMANCHE_RTIM (COMANCHE_BASE + 0x0220) /* Refresh Timing */ + +#define COMANCHE_VFP (COMANCHE_BASE + 0x0240) /* Video Frame Ptr. */ +#define COMANCHE_VFP_COL 0x001f +#define COMANCHE_VFP_ROW 0x3fe0 +#define COMANCHE_VFP_SUBBANK 0x4000 +#define COMANCHE_VFP_RSVD 0x8000 + +#define COMANCHE_PD_LO (COMANCHE_BASE + 0x0260) /* Pres Detect Low */ + +#define COMANCHE_PD_HI (COMANCHE_BASE + 0x0280) /* Pres Detect High */ + +/* + * 21071-CA Memory banks' Base Address Register format + */ +#define COMANCHE_B0_BAR (COMANCHE_BASE + 0x0800) /* Bank 0 BA */ +#define COMANCHE_B1_BAR (COMANCHE_BASE + 0x0820) /* Bank 1 BA */ +#define COMANCHE_B2_BAR (COMANCHE_BASE + 0x0840) /* Bank 2 BA */ +#define COMANCHE_B3_BAR (COMANCHE_BASE + 0x0860) /* Bank 3 BA */ +#define COMANCHE_B4_BAR (COMANCHE_BASE + 0x0880) /* Bank 4 BA */ +#define COMANCHE_B5_BAR (COMANCHE_BASE + 0x08a0) /* Bank 5 BA */ +#define COMANCHE_B6_BAR (COMANCHE_BASE + 0x08c0) /* Bank 6 BA */ +#define COMANCHE_B7_BAR (COMANCHE_BASE + 0x08e0) /* Bank 7 BA */ +#define COMANCHE_B8_BAR (COMANCHE_BASE + 0x0900) /* Bank 8 BA */ +#define COMANCHE_BAR_RSVD 0x001f + +/* + * 21071-CA Memory banks' Configuration Register format + */ +#define COMANCHE_B0_CR (COMANCHE_BASE + 0x0a00) /* Bank 0 Config */ +#define COMANCHE_B1_CR (COMANCHE_BASE + 0x0a20) /* Bank 1 Config */ +#define COMANCHE_B2_CR (COMANCHE_BASE + 0x0a40) /* Bank 2 Config */ +#define COMANCHE_B3_CR (COMANCHE_BASE + 0x0a60) /* Bank 3 Config */ +#define COMANCHE_B4_CR (COMANCHE_BASE + 0x0a80) /* Bank 4 Config */ +#define COMANCHE_B5_CR (COMANCHE_BASE + 0x0aa0) /* Bank 5 Config */ +#define COMANCHE_B6_CR (COMANCHE_BASE + 0x0ac0) /* Bank 6 Config */ +#define COMANCHE_B7_CR (COMANCHE_BASE + 0x0ae0) /* Bank 7 Config */ +#define COMANCHE_B8_CR (COMANCHE_BASE + 0x0b00) /* Bank 8 Config */ +#define COMANCHE_CR_VALID 0x0001 +#define COMANCHE_CR_SIZE 0x001e +#define COMANCHE_CR_SUBENA 0x0020 +#define COMANCHE_CR_COLSEL 0x01c0 +#define COMANCHE_CR_S0_RSVD 0xfe00 +#define COMANCHE_CR_S8_CHECK 0x0200 +#define COMANCHE_CR_S8_RSVD 0xfc00 + +/* + * 21071-CA Memory banks' Timing Register A format + */ +#define COMANCHE_B0_TRA (COMANCHE_BASE + 0x0c00) /* Bank 0 Timing A */ +#define COMANCHE_B1_TRA (COMANCHE_BASE + 0x0c20) /* Bank 1 Timing A */ +#define COMANCHE_B2_TRA (COMANCHE_BASE + 0x0c40) /* Bank 2 Timing A */ +#define COMANCHE_B3_TRA (COMANCHE_BASE + 0x0c60) /* Bank 3 Timing A */ +#define COMANCHE_B4_TRA (COMANCHE_BASE + 0x0c80) /* Bank 4 Timing A */ +#define COMANCHE_B5_TRA (COMANCHE_BASE + 0x0ca0) /* Bank 5 Timing A */ +#define COMANCHE_B6_TRA (COMANCHE_BASE + 0x0cc0) /* Bank 6 Timing A */ +#define COMANCHE_B7_TRA (COMANCHE_BASE + 0x0ce0) /* Bank 7 Timing A */ +#define COMANCHE_B8_TRA (COMANCHE_BASE + 0x0d00) /* Bank 8 Timing A */ +#define COMANCHE_TRA_ROWSETUP 0x0003 +#define COMANCHE_TRA_ROWHOLD 0x000c +#define COMANCHE_TRA_COLSETUP 0x0070 +#define COMANCHE_TRA_COLHOLD 0x0180 +#define COMANCHE_TRA_RDLYROW 0x0e00 +#define COMANCHE_TRA_RDLYCOL 0x7000 +#define COMANCHE_TRA_RSVD 0x8000 + +/* + * 21071-CA Memory banks' Timing Register B format + */ +#define COMANCHE_B0_TRB (COMANCHE_BASE + 0x0e00) /* Bank 0 Timing B */ +#define COMANCHE_B1_TRB (COMANCHE_BASE + 0x0e20) /* Bank 1 Timing B */ +#define COMANCHE_B2_TRB (COMANCHE_BASE + 0x0e40) /* Bank 2 Timing B */ +#define COMANCHE_B3_TRB (COMANCHE_BASE + 0x0e60) /* Bank 3 Timing B */ +#define COMANCHE_B4_TRB (COMANCHE_BASE + 0x0e80) /* Bank 4 Timing B */ +#define COMANCHE_B5_TRB (COMANCHE_BASE + 0x0ea0) /* Bank 5 Timing B */ +#define COMANCHE_B6_TRB (COMANCHE_BASE + 0x0ec0) /* Bank 6 Timing B */ +#define COMANCHE_B7_TRB (COMANCHE_BASE + 0x0ee0) /* Bank 7 Timing B */ +#define COMANCHE_B8_TRB (COMANCHE_BASE + 0x0f00) /* Bank 8 Timing B */ +#define COMANCHE_TRB_RTCAS 0x0007 +#define COMANCHE_TRB_WTCAS 0x0038 +#define COMANCHE_TRB_TCP 0x00c0 +#define COMANCHE_TRB_WHOLD0ROW 0x0700 +#define COMANCHE_TRB_WHOLD0COL 0x3800 +#define COMANCHE_TRB_RSVD 0xc000 + + +/* + * 21071-DA Registers + */ +#define EPIC_DCSR (EPIC_BASE + 0x0000) /* Diagnostic CSR */ +#define EPIC_DCSR_TENB 0x00000001 +#define EPIC_DCSR_RSVD 0x7fc00082 +#define EPIC_DCSR_PENB 0x00000004 +#define EPIC_DCSR_DCEI 0x00000008 +#define EPIC_DCSR_DPEC 0x00000010 +#define EPIC_DCSR_IORT 0x00000020 +#define EPIC_DCSR_LOST 0x00000040 +#define EPIC_DCSR_DDPE 0x00000100 +#define EPIC_DCSR_IOPE 0x00000200 +#define EPIC_DCSR_TABT 0x00000400 +#define EPIC_DCSR_NDEV 0x00000800 +#define EPIC_DCSR_CMRD 0x00001000 +#define EPIC_DCSR_UMRD 0x00002000 +#define EPIC_DCSR_IPTL 0x00004000 +#define EPIC_DCSR_MERR 0x00008000 +#define EPIC_DCSR_DBYP 0x00030000 +#define EPIC_DCSR_PCMD 0x003c0000 +#define EPIC_DCSR_PASS2 0x80000000 + +#define EPIC_PEAR (EPIC_BASE + 0x0020) /* PCI Err Addr. */ + +#define EPIC_SEAR (EPIC_BASE + 0x0040) /* sysBus Err Addr. */ +#define EPIC_SEAR_RSVD 0x0000000f +#define EPIC_SEAR_SYS_ERR 0xfffffff0 + +#define EPIC_DUMMY_1 (EPIC_BASE + 0x0060) /* Dummy 1 */ +#define EPIC_DUMMY_2 (EPIC_BASE + 0x0080) /* Dummy 2 */ +#define EPIC_DUMMY_3 (EPIC_BASE + 0x00a0) /* Dummy 3 */ + +#define EPIC_TBASE_1 (EPIC_BASE + 0x00c0) /* Trans. Base 1 */ +#define EPIC_TBASE_2 (EPIC_BASE + 0x00e0) /* Trans. Base 2 */ +#define EPIC_TBASE_RSVD 0x000001ff +#define EPIC_TBASE_T_BASE 0xfffffe00 +#define EPIC_TBASE_SHIFT 1 + +#define EPIC_PCI_BASE_1 (EPIC_BASE + 0x0100) /* PCI Base 1 */ +#define EPIC_PCI_BASE_2 (EPIC_BASE + 0x0120) /* PCI Base 2 */ +#define EPIC_PCI_BASE_RSVD 0x0003ffff +#define EPIC_PCI_BASE_SGEN 0x00040000 +#define EPIC_PCI_BASE_WENB 0x00080000 +#define EPIC_PCI_BASE_PCI_BASE 0xfff00000 + +#define EPIC_PCI_MASK_1 (EPIC_BASE + 0x0140) /* PCI Mask 1 */ +#define EPIC_PCI_MASK_2 (EPIC_BASE + 0x0160) /* PCI Mask 2 */ +#define EPIC_PCI_MASK_RSVD 0x000fffff +#define EPIC_PCI_MASK_PCI_MASK 0xfff00000 +#define EPIC_PCI_MASK_1M 0x00000000 +#define EPIC_PCI_MASK_2M 0x00100000 +#define EPIC_PCI_MASK_4M 0x00300000 +#define EPIC_PCI_MASK_8M 0x00700000 +#define EPIC_PCI_MASK_16M 0x00f00000 +#define EPIC_PCI_MASK_32M 0x01f00000 +#define EPIC_PCI_MASK_64M 0x03f00000 +#define EPIC_PCI_MASK_128M 0x07f00000 +#define EPIC_PCI_MASK_256M 0x0ff00000 +#define EPIC_PCI_MASK_512M 0x1ff00000 +#define EPIC_PCI_MASK_1G 0x3ff00000 +#define EPIC_PCI_MASK_2G 0x7ff00000 +#define EPIC_PCI_MASK_4G 0xfff00000 + +#define EPIC_HAXR0 (EPIC_BASE + 0x0180) /* Host Addr Extn 0 */ + +#define EPIC_HAXR1 (EPIC_BASE + 0x01a0) /* Host Addr Extn 1 */ +#define EPIC_HAXR1_RSVD 0x07ffffff +#define EPIC_HAXR1_EADDR 0xf8000000 + +#define EPIC_HAXR2 (EPIC_BASE + 0x01c0) /* Host Addr Extn 2 */ +#define EPIC_HAXR2_CONF_TYPE 0x00000003 +#define EPIC_HAXR2_CONF_TYPO0 0x00000000 +#define EPIC_HAXR2_CONF_TYPE1 0x00000001 +#define EPIC_HAXR2_RSVD 0x00fffffc +#define EPIC_HAXR2_EADDR 0xff000000 + +#define EPIC_PMLT (EPIC_BASE + 0x01e0) /* PCI Mstr Lat Tmr */ +#define EPIC_PMLT_PMLC 0x000000ff +#define EPIC_PMLT_RSVD 0xffffff00 + +#define EPIC_TLB_TAG_0 (EPIC_BASE + 0x0200) /* TLB Tag 0 */ +#define EPIC_TLB_TAG_1 (EPIC_BASE + 0x0220) /* TLB Tag 1 */ +#define EPIC_TLB_TAG_2 (EPIC_BASE + 0x0240) /* TLB Tag 2 */ +#define EPIC_TLB_TAG_3 (EPIC_BASE + 0x0260) /* TLB Tag 3 */ +#define EPIC_TLB_TAG_4 (EPIC_BASE + 0x0280) /* TLB Tag 4 */ +#define EPIC_TLB_TAG_5 (EPIC_BASE + 0x02a0) /* TLB Tag 5 */ +#define EPIC_TLB_TAG_6 (EPIC_BASE + 0x02c0) /* TLB Tag 6 */ +#define EPIC_TLB_TAG_7 (EPIC_BASE + 0x02e0) /* TLB Tag 7 */ +#define EPIC_TLB_TAG_RSVD 0x00000fff +#define EPIC_TLB_TAG_EVAL 0x00001000 +#define EPIC_TLB_TAG_PCI_PAGE 0xffffe000 + +#define EPIC_TLB_DATA_0 (EPIC_BASE + 0x0300) /* TLB Data 0 */ +#define EPIC_TLB_DATA_1 (EPIC_BASE + 0x0320) /* TLB Data 1 */ +#define EPIC_TLB_DATA_2 (EPIC_BASE + 0x0340) /* TLB Data 2 */ +#define EPIC_TLB_DATA_3 (EPIC_BASE + 0x0360) /* TLB Data 3 */ +#define EPIC_TLB_DATA_4 (EPIC_BASE + 0x0380) /* TLB Data 4 */ +#define EPIC_TLB_DATA_5 (EPIC_BASE + 0x03a0) /* TLB Data 5 */ +#define EPIC_TLB_DATA_6 (EPIC_BASE + 0x03c0) /* TLB Data 6 */ +#define EPIC_TLB_DATA_7 (EPIC_BASE + 0x03e0) /* TLB Data 7 */ +#define EPIC_TLB_DATA_RSVD 0xffe00001 +#define EPIC_TLB_DATA_CPU_PAGE 0x001ffffe + +#define EPIC_TBIA (EPIC_BASE + 0x0400) /* TLB Invl All */ + +/* + * EPIC Scatter-Gather Map Entries + */ + +struct sgmapent { + u_int64_t val; +}; +#define SGMAPENT_EVAL 0x0000000000000001L +#define SGMAPENT_PFN 0x00000000001ffffeL +#define SGMAPENT_RSVD 0xffffffffffe00000L + +#define SGMAP_MAKEENTRY(pfn) (SGMAPENT_EVAL | ((pfn) << 1)) diff --git a/sys/alpha/pci/apecsvar.h b/sys/alpha/pci/apecsvar.h new file mode 100644 index 0000000..0104b4f --- /dev/null +++ b/sys/alpha/pci/apecsvar.h @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id: ciavar.h,v 1.1 1998/07/05 12:16:15 dfr Exp $ + */ + +extern void apecs_init(void); + diff --git a/sys/alpha/pci/cia.c b/sys/alpha/pci/cia.c index 25f8701..9b33ac8 100644 --- a/sys/alpha/pci/cia.c +++ b/sys/alpha/pci/cia.c @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: cia.c,v 1.4 1998/07/31 09:17:51 dfr Exp $ + * $Id: cia.c,v 1.5 1998/08/07 08:18:44 dfr Exp $ */ #include @@ -45,16 +45,8 @@ static devclass_t cia_devclass; static device_t cia0; /* XXX only one for now */ static u_int32_t cia_hae_mem; -extern void eb164_intr_enable(int irq); -extern void eb164_intr_disable(int irq); -static void cia_intr(void* frame, u_long vector); - struct cia_softc { - vm_offset_t dmem_base; /* dense memory */ - vm_offset_t smem_base; /* sparse memory */ - vm_offset_t io_base; /* dense i/o */ - vm_offset_t cfg0_base; /* dense pci0 config */ - vm_offset_t cfg1_base; /* dense pci1 config */ + int junk; /* no softc */ }; #define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev) @@ -415,9 +407,8 @@ cia_swiz_maxdevs(u_int b) type val = ~0; \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ @@ -429,9 +420,8 @@ cia_swiz_maxdevs(u_int b) #define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \ int ipl = 0; \ u_int32_t old_cfg = 0; \ - struct cia_softc* sc = CIA_SOFTC(cia0); \ vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \ - vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg0_base, off); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(CIA_PCI_CONF, off); \ alpha_mb(); \ CIA_TYPE1_SETUP(b,ipl,old_cfg); \ if (!badaddr((caddr_t)kv, sizeof(type))) { \ @@ -515,6 +505,13 @@ cia_init() else chipset = cia_bwx_chipset; cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM); + +#if 0 + chipset = cia_swiz_chipset; /* XXX */ +#endif + + if (platform.pci_intr_init) + platform.pci_intr_init(); } static int @@ -536,22 +533,10 @@ cia_attach(device_t dev) struct cia_softc* sc = CIA_SOFTC(dev); cia_init(); - chipset.bridge = dev; - - if (alpha_amask(ALPHA_AMASK_BWX) == 0) { - sc->dmem_base = CIA_EV56_BWMEM; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_EV56_BWIO; - sc->cfg0_base = CIA_EV56_BWCONF0; - sc->cfg1_base = CIA_EV56_BWCONF1; - } else { - sc->dmem_base = CIA_PCI_DENSE; - sc->smem_base = CIA_PCI_SMEM1; - sc->io_base = CIA_PCI_SIO1; - sc->cfg0_base = KV(CIA_PCI_CONF); - sc->cfg1_base = NULL; - } - set_iointr(cia_intr); + chipset.intrdev = dev; + + if (!platform.iointr) /* XXX */ + set_iointr(alpha_dispatch_intr); bus_generic_attach(dev); return 0; @@ -561,7 +546,7 @@ static void * cia_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg) { - return alpha_create_intr(irq, intr, arg); + return alpha_create_intr(0x900 + (irq << 4), intr, arg); } static int @@ -571,22 +556,12 @@ cia_connect_intr(device_t dev, void* ih) int s = splhigh(); int error = alpha_connect_intr(i); if (!error) { - if (i->vector > 0x900) - /* PCI interrupt */ - platform.pci_intr_enable((i->vector - 0x900) >> 4); - else if (i->vector > 0x800) - /* ISA interrupt chained to PCI interrupt 4 */ - platform.pci_intr_enable(4);/* XXX */ + /* Enable PCI interrupt */ + platform.pci_intr_enable((i->vector - 0x900) >> 4); } splx(s); return error; } -static void -cia_intr(void* frame, u_long vector) -{ - alpha_dispatch_intr(vector); -} - DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0); diff --git a/sys/alpha/pci/lca.c b/sys/alpha/pci/lca.c new file mode 100644 index 0000000..739d3f0 --- /dev/null +++ b/sys/alpha/pci/lca.c @@ -0,0 +1,371 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa) + +static devclass_t lca_devclass; +static device_t lca0; /* XXX only one for now */ +static device_t isa0; + +struct lca_softc { + int junk; +}; + +#define LCA_SOFTC(dev) (struct lca_softc*) device_get_softc(dev) + +static alpha_chipset_inb_t lca_inb; +static alpha_chipset_inw_t lca_inw; +static alpha_chipset_inl_t lca_inl; +static alpha_chipset_outb_t lca_outb; +static alpha_chipset_outw_t lca_outw; +static alpha_chipset_outl_t lca_outl; +static alpha_chipset_readb_t lca_readb; +static alpha_chipset_readw_t lca_readw; +static alpha_chipset_readl_t lca_readl; +static alpha_chipset_writeb_t lca_writeb; +static alpha_chipset_writew_t lca_writew; +static alpha_chipset_writel_t lca_writel; +static alpha_chipset_maxdevs_t lca_maxdevs; +static alpha_chipset_cfgreadb_t lca_cfgreadb; +static alpha_chipset_cfgreadw_t lca_cfgreadw; +static alpha_chipset_cfgreadl_t lca_cfgreadl; +static alpha_chipset_cfgwriteb_t lca_cfgwriteb; +static alpha_chipset_cfgwritew_t lca_cfgwritew; +static alpha_chipset_cfgwritel_t lca_cfgwritel; + +static alpha_chipset_t lca_chipset = { + lca_inb, + lca_inw, + lca_inl, + lca_outb, + lca_outw, + lca_outl, + lca_readb, + lca_readw, + lca_readl, + lca_writeb, + lca_writew, + lca_writel, + lca_maxdevs, + lca_cfgreadb, + lca_cfgreadw, + lca_cfgreadl, + lca_cfgwriteb, + lca_cfgwritew, + lca_cfgwritel, +}; + +static u_int8_t +lca_inb(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_BYTE(KV(LCA_PCI_SIO), port); +} + +static u_int16_t +lca_inw(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_WORD(KV(LCA_PCI_SIO), port); +} + +static u_int32_t +lca_inl(u_int32_t port) +{ + alpha_mb(); + return SPARSE_READ_LONG(KV(LCA_PCI_SIO), port); +} + +static void +lca_outb(u_int32_t port, u_int8_t data) +{ + SPARSE_WRITE_BYTE(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outw(u_int32_t port, u_int16_t data) +{ + SPARSE_WRITE_WORD(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +static void +lca_outl(u_int32_t port, u_int32_t data) +{ + SPARSE_WRITE_LONG(KV(LCA_PCI_SIO), port, data); + alpha_wmb(); +} + +/* + * The LCA HAE is write-only. According to NetBSD, this is where it starts. + */ +static u_int32_t lca_hae_mem = 0x80000000; + +/* + * The first 16Mb ignores the HAE. The next 112Mb uses the HAE to set + * the high bits of the PCI address. + */ +#define REG1 (1UL << 24) + +static __inline void +lca_set_hae_mem(u_int32_t *pa) +{ + int s; + u_int32_t msb; + if(*pa >= REG1){ + msb = *pa & 0xf8000000; + *pa -= msb; + s = splhigh(); + if (msb != lca_hae_mem) { + lca_hae_mem = msb; + REGVAL(LCA_IOC_HAE) = lca_hae_mem; + alpha_mb(); + alpha_mb(); + } + splx(s); + } +} + +static u_int8_t +lca_readb(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_BYTE(KV(LCA_PCI_SPARSE), pa); +} + +static u_int16_t +lca_readw(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_WORD(KV(LCA_PCI_SPARSE), pa); +} + +static u_int32_t +lca_readl(u_int32_t pa) +{ + alpha_mb(); + lca_set_hae_mem(&pa); + return SPARSE_READ_LONG(KV(LCA_PCI_SPARSE), pa); +} + +static void +lca_writeb(u_int32_t pa, u_int8_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_BYTE(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writew(u_int32_t pa, u_int16_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_WORD(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static void +lca_writel(u_int32_t pa, u_int32_t data) +{ + lca_set_hae_mem(&pa); + SPARSE_WRITE_LONG(KV(LCA_PCI_SPARSE), pa, data); + alpha_wmb(); +} + +static int +lca_maxdevs(u_int b) +{ + return 12; /* XXX */ +} + +#define LCA_CFGOFF(b, s, f, r) \ + (((b) << 16) | ((s) << 11) | ((f) << 8) | (r)) + +#define LCA_TYPE1_SETUP(b,s) if ((b)) { \ + do { \ + (s) = splhigh(); \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 1; \ + alpha_mb(); \ + } while(0); \ +} + +#define LCA_TYPE1_TEARDOWN(b,s) if ((b)) { \ + do { \ + alpha_mb(); \ + REGVAL(LCA_IOC_CONF) = 0; \ + alpha_mb(); \ + splx((s)); \ + } while(0); \ +} + +#define CFGREAD(b, s, f, r, width, type) \ + type val = ~0; \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return val + +#define CFGWRITE(b, s, f, r, data, width, type) \ + int ipl = 0; \ + vm_offset_t off = LCA_CFGOFF(b, s, f, r); \ + vm_offset_t kv = SPARSE_##width##_ADDRESS(LCA_PCI_CONF, off); \ + alpha_mb(); \ + LCA_TYPE1_SETUP(b,ipl); \ + if (!badaddr((caddr_t)kv, sizeof(type))) { \ + SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \ + alpha_wmb(); \ + } \ + LCA_TYPE1_TEARDOWN(b,ipl); \ + return + +static u_int8_t +lca_cfgreadb(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, BYTE, u_int8_t); +} + +static u_int16_t +lca_cfgreadw(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, WORD, u_int16_t); +} + +static u_int32_t +lca_cfgreadl(u_int b, u_int s, u_int f, u_int r) +{ + CFGREAD(b, s, f, r, LONG, u_int32_t); +} + +static void +lca_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data) +{ + CFGWRITE(b, s, f, r, data, BYTE, u_int8_t); +} + +static void +lca_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data) +{ + CFGWRITE(b, s, f, r, data, WORD, u_int16_t); +} + +static void +lca_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data) +{ + CFGWRITE(b, s, f, r, data, LONG, u_int16_t); +} + +static int lca_probe(device_t dev); +static int lca_attach(device_t dev); +static void *lca_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg); +static int lca_connect_intr(device_t dev, void* ih); + +static device_method_t lca_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, lca_probe), + DEVMETHOD(device_attach, lca_attach), + + /* Bus interface */ + + { 0, 0 } +}; + +static driver_t lca_driver = { + "lca", + lca_methods, + DRIVER_TYPE_MISC, + sizeof(struct lca_softc), +}; + +void +lca_init() +{ + static int initted = 0; + + if (initted) return; + initted = 1; + + /* Type 0 PCI conf access. */ + REGVAL64(LCA_IOC_CONF) = 0; + + if (platform.pci_intr_init) + platform.pci_intr_init(); + + chipset = lca_chipset; +} + +static int +lca_probe(device_t dev) +{ + if (lca0) + return ENXIO; + lca0 = dev; + device_set_desc(dev, "21066 PCI adapter"); /* XXX */ + + isa0 = device_add_child(dev, "isa", 0, 0); + + return 0; +} + +static int +lca_attach(device_t dev) +{ + struct lca_softc* sc = LCA_SOFTC(dev); + + lca_init(); + chipset.intrdev = isa0; + + set_iointr(alpha_dispatch_intr); + + bus_generic_attach(dev); + return 0; +} + +DRIVER_MODULE(lca, root, lca_driver, lca_devclass, 0, 0); + diff --git a/sys/alpha/pci/lcareg.h b/sys/alpha/pci/lcareg.h new file mode 100644 index 0000000..f7a655c --- /dev/null +++ b/sys/alpha/pci/lcareg.h @@ -0,0 +1,95 @@ +/* $NetBSD: lcareg.h,v 1.8 1997/09/05 02:14:31 thorpej Exp $ */ + +/* + * Copyright (c) 1995 Carnegie-Mellon University. + * All rights reserved. + * + * Authors: Jeffrey Hsu, Jason R. Thorpe + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * 21066 chip registers + */ + +#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r)) +#define REGVAL64(r) (*(volatile int64_t *)ALPHA_PHYS_TO_K0SEG(r)) + +/* + * Base addresses + */ +#define LCA_IOC_BASE 0x180000000L /* LCA IOC Regs */ +#define LCA_PCI_SIO 0x1c0000000L /* PCI Sp. I/O Space */ +#define LCA_PCI_CONF 0x1e0000000L /* PCI Conf. Space */ +#define LCA_PCI_SPARSE 0x200000000L /* PCI Sparse Space */ +#define LCA_PCI_DENSE 0x300000000L /* PCI Dense Space */ + +#define LCA_IOC_HAE LCA_IOC_BASE /* Host Address Ext. (64) */ +#define IOC_HAE_ADDREXT 0x00000000f8000000UL +#define IOC_HAE_RSVSD 0xffffffff07ffffffUL + +#define LCA_IOC_CONF (LCA_IOC_BASE + 0x020) /* Configuration Cycle Type */ + +#define LCA_IOC_STAT0 (LCA_IOC_BASE + 0x040) /* Status 0 */ +#define IOC_STAT0_CMD 0x000000000000000fUL /* PCI command mask */ +#define IOC_STAT0_ERR 0x0000000000000010UL /* IOC error indicator R/W1C */ +#define IOC_STAT0_LOST 0x0000000000000020UL /* IOC lose error info R/W1C */ +#define IOC_STAT0_THIT 0x0000000000000040UL /* test hit */ +#define IOC_STAT0_TREF 0x0000000000000080UL /* test reference */ +#define IOC_STAT0_CODE 0x0000000000000700UL /* code mask */ +#define IOC_STAT0_CODESHIFT 8 +#define IOC_STAT0_P_NBR 0x00000000ffffe000UL /* page number mask */ + +#define LCA_IOC_STAT1 (LCA_IOC_BASE + 0x060) /* Status 1 */ +#define IOC_STAT1_ADDR 0x00000000ffffffffUL /* PCI address mask */ + +#define LCA_IOC_TBIA (LCA_IOC_BASE + 0x080) /* TLB Invalidate All */ +#define LCA_IOC_TB_ENA (LCA_IOC_BASE + 0x0a0) /* TLB Enable */ +#define IOC_TB_ENA_TEN 0x0000000000000080UL + +#define LCA_IOC_W_BASE0 (LCA_IOC_BASE + 0x100) /* Window Base */ +#define LCA_IOC_W_MASK0 (LCA_IOC_BASE + 0x140) /* Window Mask */ +#define LCA_IOC_W_T_BASE0 (LCA_IOC_BASE + 0x180) /* Translated Base */ + +#define LCA_IOC_W_BASE1 (LCA_IOC_BASE + 0x120) /* Window Base */ +#define LCA_IOC_W_MASK1 (LCA_IOC_BASE + 0x160) /* Window Mask */ +#define LCA_IOC_W_T_BASE1 (LCA_IOC_BASE + 0x1a0) /* Translated Base */ + +#define IOC_W_BASE_W_BASE 0x00000000fff00000UL /* Window base value */ +#define IOC_W_BASE_SG 0x0000000100000000UL /* Window uses SGMAPs */ +#define IOC_W_BASE_WEN 0x0000000200000000UL /* Window enable */ + +#define IOC_W_MASK_1M 0x0000000000000000UL /* 1MB window */ +#define IOC_W_MASK_2M 0x0000000000100000UL /* 2MB window */ +#define IOC_W_MASK_4M 0x0000000000300000UL /* 4MB window */ +#define IOC_W_MASK_8M 0x0000000000700000UL /* 8MB window */ +#define IOC_W_MASK_16M 0x0000000000f00000UL /* 16MB window */ +#define IOC_W_MASK_32M 0x0000000001f00000UL /* 32MB window */ +#define IOC_W_MASK_64M 0x0000000003f00000UL /* 64MB window */ +#define IOC_W_MASK_128M 0x0000000007f00000UL /* 128M window */ +#define IOC_W_MASK_256M 0x000000000ff00000UL /* 256M window */ +#define IOC_W_MASK_512M 0x000000001ff00000UL /* 512M window */ +#define IOC_W_MASK_1G 0x000000003ff00000UL /* 1GB window */ +#define IOC_W_MASK_2G 0x000000007ff00000UL /* 2GB window */ +#define IOC_W_MASK_4G 0x00000000fff00000UL /* 4GB window */ + +#define IOC_W_T_BASE 0x00000000fffffc00UL /* page table base */ diff --git a/sys/alpha/pci/lcavar.h b/sys/alpha/pci/lcavar.h new file mode 100644 index 0000000..53f036d --- /dev/null +++ b/sys/alpha/pci/lcavar.h @@ -0,0 +1,29 @@ +/*- + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $Id$ + */ + +extern void lca_init(void); diff --git a/sys/alpha/pci/pcibus.c b/sys/alpha/pci/pcibus.c index 2735fd1..a350772 100644 --- a/sys/alpha/pci/pcibus.c +++ b/sys/alpha/pci/pcibus.c @@ -23,7 +23,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: pcibus.c,v 1.2 1998/07/12 16:16:20 dfr Exp $ + * $Id: pcibus.c,v 1.3 1998/07/22 08:33:30 dfr Exp $ * */ @@ -98,10 +98,9 @@ struct intrec * intr_create(void *dev_instance, int irq, inthand2_t handler, void *arg, intrmask_t *maskptr, int flags) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) - return BUS_CREATE_INTR(pcib, pcib, - 0x900 + (irq << 4), + return BUS_CREATE_INTR(pcib, pcib, irq, (driver_intr_t*) handler, arg); else return 0; @@ -110,7 +109,7 @@ intr_create(void *dev_instance, int irq, inthand2_t handler, void *arg, int intr_connect(struct intrec *idesc) { - device_t pcib = chipset.bridge; + device_t pcib = chipset.intrdev; if (pcib) return BUS_CONNECT_INTR(pcib, idesc); else -- cgit v1.1