From 20d7a03f75db9b3ab7ed52d5ef1bb5621b70b513 Mon Sep 17 00:00:00 2001 From: peter Date: Thu, 11 Dec 2003 04:47:53 +0000 Subject: CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32. This should probably be 128 since that is what the hardware prefetch fill size is on both the p3, p4 and athlon* cpus. --- libexec/rtld-elf/amd64/lockdflt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libexec') diff --git a/libexec/rtld-elf/amd64/lockdflt.c b/libexec/rtld-elf/amd64/lockdflt.c index fd74cba..b3b4935 100644 --- a/libexec/rtld-elf/amd64/lockdflt.c +++ b/libexec/rtld-elf/amd64/lockdflt.c @@ -55,7 +55,7 @@ #include "debug.h" #include "rtld.h" -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 64 #define WAFLAG 0x1 /* A writer holds the lock */ #define RC_INCR 0x2 /* Adjusts count of readers desiring lock */ -- cgit v1.1