From ff2ba393a56d9d99dcb76ceada542233db28af9a Mon Sep 17 00:00:00 2001 From: dim Date: Wed, 6 Jan 2016 20:01:02 +0000 Subject: Vendor import of llvm trunk r256945: https://llvm.org/svn/llvm-project/llvm/trunk@256945 --- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'lib/Target/AMDGPU/SIMachineFunctionInfo.cpp') diff --git a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 935aad4..bf15516 100644 --- a/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -156,6 +156,17 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( if (!LaneVGPRs.count(LaneVGPRIdx)) { unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass); + + if (LaneVGPR == AMDGPU::NoRegister) { + LLVMContext &Ctx = MF->getFunction()->getContext(); + Ctx.emitError("Ran out of VGPRs for spilling SGPR"); + + // When compiling from inside Mesa, the compilation continues. + // Select an arbitrary register to avoid triggering assertions + // during subsequent passes. + LaneVGPR = AMDGPU::VGPR0; + } + LaneVGPRs[LaneVGPRIdx] = LaneVGPR; // Add this register as live-in to all blocks to avoid machine verifer -- cgit v1.1