From 60b571e49a90d38697b3aca23020d9da42fc7d7f Mon Sep 17 00:00:00 2001 From: dim Date: Sun, 2 Apr 2017 17:24:58 +0000 Subject: Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release: MFC r309142 (by emaste): Add WITH_LLD_AS_LD build knob If set it installs LLD as /usr/bin/ld. LLD (as of version 3.9) is not capable of linking the world and kernel, but can self-host and link many substantial applications. GNU ld continues to be used for the world and kernel build, regardless of how this knob is set. It is on by default for arm64, and off for all other CPU architectures. Sponsored by: The FreeBSD Foundation MFC r310840: Reapply 310775, now it also builds correctly if lldb is disabled: Move llvm-objdump from CLANG_EXTRAS to installed by default We currently install three tools from binutils 2.17.50: as, ld, and objdump. Work is underway to migrate to a permissively-licensed tool-chain, with one goal being the retirement of binutils 2.17.50. LLVM's llvm-objdump is intended to be compatible with GNU objdump although it is currently missing some options and may have formatting differences. Enable it by default for testing and further investigation. It may later be changed to install as /usr/bin/objdump, it becomes a fully viable replacement. Reviewed by: emaste Differential Revision: https://reviews.freebsd.org/D8879 MFC r312855 (by emaste): Rename LLD_AS_LD to LLD_IS_LD, for consistency with CLANG_IS_CC Reported by: Dan McGregor MFC r313559 | glebius | 2017-02-10 18:34:48 +0100 (Fri, 10 Feb 2017) | 5 lines Don't check struct rtentry on FreeBSD, it is an internal kernel structure. On other systems it may be API structure for SIOCADDRT/SIOCDELRT. Reviewed by: emaste, dim MFC r314152 (by jkim): Remove an assembler flag, which is redundant since r309124. The upstream took care of it by introducing a macro NO_EXEC_STACK_DIRECTIVE. http://llvm.org/viewvc/llvm-project?rev=273500&view=rev Reviewed by: dim MFC r314564: Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 (branches/release_40 296509). The release will follow soon. Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11 support to build; see UPDATING for more information. Also note that as of 4.0.0, lld should be able to link the base system on amd64 and aarch64. See the WITH_LLD_IS_LLD setting in src.conf(5). Though please be aware that this is work in progress. Release notes for llvm, clang and lld will be available here: Thanks to Ed Maste, Jan Beich, Antoine Brodin and Eric Fiselier for their help. Relnotes: yes Exp-run: antoine PR: 215969, 216008 MFC r314708: For now, revert r287232 from upstream llvm trunk (by Daniil Fukalov): [SCEV] limit recursion depth of CompareSCEVComplexity Summary: CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled loop) and runs almost infinite time. Added cache of "equal" SCEV pairs to earlier cutoff of further estimation. Recursion depth limit was also introduced as a parameter. Reviewers: sanjoy Subscribers: mzolotukhin, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D26389 This commit is the cause of excessive compile times on skein_block.c (and possibly other files) during kernel builds on amd64. We never saw the problematic behavior described in this upstream commit, so for now it is better to revert it. An upstream bug has been filed here: https://bugs.llvm.org/show_bug.cgi?id=32142 Reported by: mjg MFC r314795: Reapply r287232 from upstream llvm trunk (by Daniil Fukalov): [SCEV] limit recursion depth of CompareSCEVComplexity Summary: CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled loop) and runs almost infinite time. Added cache of "equal" SCEV pairs to earlier cutoff of further estimation. Recursion depth limit was also introduced as a parameter. Reviewers: sanjoy Subscribers: mzolotukhin, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D26389 Pull in r296992 from upstream llvm trunk (by Sanjoy Das): [SCEV] Decrease the recursion threshold for CompareValueComplexity Fixes PR32142. r287232 accidentally increased the recursion threshold for CompareValueComplexity from 2 to 32. This change reverses that change by introducing a separate flag for CompareValueComplexity's threshold. The latter revision fixes the excessive compile times for skein_block.c. MFC r314907 | mmel | 2017-03-08 12:40:27 +0100 (Wed, 08 Mar 2017) | 7 lines Unbreak ARMv6 world. The new compiler_rt library imported with clang 4.0.0 have several fatal issues (non-functional __udivsi3 for example) with ARM specific instrict functions. As temporary workaround, until upstream solve these problems, disable all thumb[1][2] related feature. MFC r315016: Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release. We were already very close to the last release candidate, so this is a pretty minor update. Relnotes: yes MFC r316005: Revert r314907, and pull in r298713 from upstream compiler-rt trunk (by Weiming Zhao): builtins: Select correct code fragments when compiling for Thumb1/Thum2/ARM ISA. Summary: Value of __ARM_ARCH_ISA_THUMB isn't based on the actual compilation mode (-mthumb, -marm), it reflect's capability of given CPU. Due to this: - use __tbumb__ and __thumb2__ insteand of __ARM_ARCH_ISA_THUMB - use '.thumb' directive consistently in all affected files - decorate all thumb functions using DEFINE_COMPILERRT_THUMB_FUNCTION() --------- Note: This patch doesn't fix broken Thumb1 variant of __udivsi3 ! Reviewers: weimingz, rengolin, compnerd Subscribers: aemerson, dim Differential Revision: https://reviews.llvm.org/D30938 Discussed with: mmel --- .../llvm/utils/TableGen/FixedLenDecoderEmitter.cpp | 192 +++++++++++---------- 1 file changed, 105 insertions(+), 87 deletions(-) (limited to 'contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp') diff --git a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp index 0506400..e1aaecc 100644 --- a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -12,21 +12,32 @@ // //===----------------------------------------------------------------------===// +#include "CodeGenInstruction.h" #include "CodeGenTarget.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/CachedHashString.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/Twine.h" #include "llvm/MC/MCFixedLenDisassembler.h" -#include "llvm/Support/DataTypes.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/LEB128.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" +#include +#include +#include +#include #include +#include +#include #include #include #include @@ -36,6 +47,7 @@ using namespace llvm; #define DEBUG_TYPE "decoder-emitter" namespace { + struct EncodingField { unsigned Base, Width, Offset; EncodingField(unsigned B, unsigned W, unsigned O) @@ -66,8 +78,8 @@ typedef std::vector DecoderTable; typedef uint32_t DecoderFixup; typedef std::vector FixupList; typedef std::vector FixupScopeList; -typedef SmallSetVector PredicateSet; -typedef SmallSetVector DecoderSet; +typedef SmallSetVector PredicateSet; +typedef SmallSetVector DecoderSet; struct DecoderTableInfo { DecoderTable Table; FixupScopeList FixupStack; @@ -75,13 +87,10 @@ struct DecoderTableInfo { DecoderSet Decoders; }; -} // End anonymous namespace - -namespace { class FixedLenDecoderEmitter { ArrayRef NumberedInstructions; -public: +public: // Defaults preserved here for documentation, even though they aren't // strictly necessary given the way that this is currently being called. FixedLenDecoderEmitter(RecordKeeper &R, std::string PredicateNamespace, @@ -111,13 +120,15 @@ public: private: CodeGenTarget Target; + public: std::string PredicateNamespace; std::string GuardPrefix, GuardPostfix; std::string ReturnOK, ReturnFail; std::string Locals; }; -} // End anonymous namespace + +} // end anonymous namespace // The set (BIT_TRUE, BIT_FALSE, BIT_UNSET) represents a ternary logic system // for a bit value. @@ -134,12 +145,15 @@ typedef enum { static bool ValueSet(bit_value_t V) { return (V == BIT_TRUE || V == BIT_FALSE); } + static bool ValueNotSet(bit_value_t V) { return (V == BIT_UNSET); } + static int Value(bit_value_t V) { return ValueNotSet(V) ? -1 : (V == BIT_FALSE ? 0 : 1); } + static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { if (BitInit *bit = dyn_cast(bits.getBit(index))) return bit->getValue() ? BIT_TRUE : BIT_FALSE; @@ -147,6 +161,7 @@ static bit_value_t bitFromBits(const BitsInit &bits, unsigned index) { // The bit is uninitialized. return BIT_UNSET; } + // Prints the bit value for each position. static void dumpBits(raw_ostream &o, const BitsInit &bits) { for (unsigned index = bits.getNumBits(); index > 0; --index) { @@ -166,19 +181,18 @@ static void dumpBits(raw_ostream &o, const BitsInit &bits) { } } -static BitsInit &getBitsField(const Record &def, const char *str) { +static BitsInit &getBitsField(const Record &def, StringRef str) { BitsInit *bits = def.getValueAsBitsInit(str); return *bits; } -// Forward declaration. -namespace { -class FilterChooser; -} // End anonymous namespace - // Representation of the instruction to work on. typedef std::vector insn_t; +namespace { + +class FilterChooser; + /// Filter - Filter works with FilterChooser to produce the decoding tree for /// the ISA. /// @@ -215,7 +229,6 @@ typedef std::vector insn_t; /// decoder could try to decode the even/odd register numbering and assign to /// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a" /// version and return the Opcode since the two have the same Asm format string. -namespace { class Filter { protected: const FilterChooser *Owner;// points to the FilterChooser who owns this filter @@ -224,7 +237,7 @@ protected: bool Mixed; // a mixed region contains both set and unset bits // Map of well-known segment value to the set of uid's with that value. - std::map > FilteredInstructions; + std::map> FilteredInstructions; // Set of uid's with non-constant segment values. std::vector VariableInstructions; @@ -239,11 +252,18 @@ protected: unsigned LastOpcFiltered; public: + Filter(Filter &&f); + Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed); + + ~Filter() = default; + unsigned getNumFiltered() const { return NumFiltered; } + unsigned getSingletonOpc() const { assert(NumFiltered == 1); return LastOpcFiltered; } + // Return the filter chooser for the group of instructions without constant // segment values. const FilterChooser &getVariableFC() const { @@ -252,11 +272,6 @@ public: return *(FilterChooserMap.find((unsigned)-1)->second); } - Filter(Filter &&f); - Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, bool mixed); - - ~Filter(); - // Divides the decoding task into sub tasks and delegates them to the // inferior FilterChooser's. // @@ -272,8 +287,9 @@ public: // Returns the number of fanout produced by the filter. More fanout implies // the filter distinguishes more categories of instructions. unsigned usefulness() const; -}; // End of class Filter -} // End anonymous namespace +}; // end class Filter + +} // end anonymous namespace // These are states of our finite state machines used in FilterChooser's // filterProcessor() which produces the filter candidates to use. @@ -301,6 +317,7 @@ typedef enum { /// decoding tree. And each case is delegated to an inferior FilterChooser to /// decide what further remaining bits to look at. namespace { + class FilterChooser { protected: friend class Filter; @@ -312,7 +329,7 @@ protected: const std::vector &Opcodes; // Lookup table for the operand decoding of instructions. - const std::map > &Operands; + const std::map> &Operands; // Vector of candidate filters. std::vector Filters; @@ -333,16 +350,13 @@ protected: // Parent emitter const FixedLenDecoderEmitter *Emitter; - FilterChooser(const FilterChooser &) = delete; - void operator=(const FilterChooser &) = delete; public: - FilterChooser(ArrayRef Insts, const std::vector &IDs, - const std::map > &Ops, + const std::map> &Ops, unsigned BW, const FixedLenDecoderEmitter *E) - : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(), + : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), FilterBitValues(BW, BIT_UNFILTERED), Parent(nullptr), BestIndex(-1), BitWidth(BW), Emitter(E) { doFilter(); @@ -350,16 +364,18 @@ public: FilterChooser(ArrayRef Insts, const std::vector &IDs, - const std::map > &Ops, + const std::map> &Ops, const std::vector &ParentFilterBitValues, const FilterChooser &parent) : AllInstructions(Insts), Opcodes(IDs), Operands(Ops), - Filters(), FilterBitValues(ParentFilterBitValues), - Parent(&parent), BestIndex(-1), BitWidth(parent.BitWidth), - Emitter(parent.Emitter) { + FilterBitValues(ParentFilterBitValues), Parent(&parent), BestIndex(-1), + BitWidth(parent.BitWidth), Emitter(parent.Emitter) { doFilter(); } + FilterChooser(const FilterChooser &) = delete; + void operator=(const FilterChooser &) = delete; + unsigned getBitWidth() const { return BitWidth; } protected: @@ -384,7 +400,7 @@ protected: } // Returns the record name. - const std::string &nameWithID(unsigned Opcode) const { + const StringRef nameWithID(unsigned Opcode) const { return AllInstructions[Opcode]->TheDef->getName(); } @@ -476,7 +492,8 @@ public: // instructions. void emitTableEntries(DecoderTableInfo &TableInfo) const; }; -} // End anonymous namespace + +} // end anonymous namespace /////////////////////////// // // @@ -527,9 +544,6 @@ Filter::Filter(FilterChooser &owner, unsigned startBit, unsigned numBits, && "Filter returns no instruction categories"); } -Filter::~Filter() { -} - // Divides the decoding task into sub tasks and delegates them to the // inferior FilterChooser's. // @@ -1071,7 +1085,7 @@ void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation, for (const auto &Op : Operands.find(Opc)->second) { // If a custom instruction decoder was specified, use that. - if (Op.numFields() == 0 && Op.Decoder.size()) { + if (Op.numFields() == 0 && !Op.Decoder.empty()) { HasCompleteDecoder = Op.HasCompleteDecoder; OS.indent(Indentation) << Emitter->GuardPrefix << Op.Decoder << "(MI, insn, Address, Decoder)" @@ -1106,11 +1120,9 @@ unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders, // overkill for now, though. // Make sure the predicate is in the table. - Decoders.insert(StringRef(Decoder)); + Decoders.insert(CachedHashString(Decoder)); // Now figure out the index for when we write out the table. - DecoderSet::const_iterator P = std::find(Decoders.begin(), - Decoders.end(), - Decoder.str()); + DecoderSet::const_iterator P = find(Decoders, Decoder.str()); return (unsigned)(P - Decoders.begin()); } @@ -1143,7 +1155,7 @@ bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, StringRef SR(P); std::pair pairs = SR.split(','); - while (pairs.second.size()) { + while (!pairs.second.empty()) { emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace); o << " && "; pairs = pairs.second.split(','); @@ -1181,11 +1193,9 @@ unsigned FilterChooser::getPredicateIndex(DecoderTableInfo &TableInfo, // overkill for now, though. // Make sure the predicate is in the table. - TableInfo.Predicates.insert(Predicate.str()); + TableInfo.Predicates.insert(CachedHashString(Predicate)); // Now figure out the index for when we write out the table. - PredicateSet::const_iterator P = std::find(TableInfo.Predicates.begin(), - TableInfo.Predicates.end(), - Predicate.str()); + PredicateSet::const_iterator P = find(TableInfo.Predicates, Predicate); return (unsigned)(P - TableInfo.Predicates.begin()); } @@ -1374,7 +1384,6 @@ void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo, Best.getVariableFC().emitTableEntries(TableInfo); } - // Assign a single filter and run with it. Top level API client can initialize // with a single filter to start the filtering process. void FilterChooser::runSingleFilter(unsigned startBit, unsigned numBit, @@ -1692,9 +1701,37 @@ void FilterChooser::emitTableEntries(DecoderTableInfo &TableInfo) const { } } +static std::string findOperandDecoderMethod(TypedInit *TI) { + std::string Decoder; + + RecordRecTy *Type = cast(TI->getType()); + Record *TypeRecord = Type->getRecord(); + + RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod"); + StringInit *String = DecoderString ? + dyn_cast(DecoderString->getValue()) : nullptr; + if (String) { + Decoder = String->getValue(); + if (!Decoder.empty()) + return Decoder; + } + + if (TypeRecord->isSubClassOf("RegisterOperand")) + TypeRecord = TypeRecord->getValueAsDef("RegClass"); + + if (TypeRecord->isSubClassOf("RegisterClass")) { + Decoder = "Decode" + TypeRecord->getName().str() + "RegisterClass"; + } else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) { + Decoder = "DecodePointerLikeRegClass" + + utostr(TypeRecord->getValueAsInt("RegClassKind")); + } + + return Decoder; +} + static bool populateInstruction(CodeGenTarget &Target, const CodeGenInstruction &CGI, unsigned Opc, - std::map > &Operands){ + std::map> &Operands){ const Record &Def = *CGI.TheDef; // If all the bit positions are not specified; do not decode this instruction. // We are bound to fail! For proper disassembly, the well-known encoding bits @@ -1722,13 +1759,15 @@ static bool populateInstruction(CodeGenTarget &Target, // Gather the outputs/inputs of the instruction, so we can find their // positions in the encoding. This assumes for now that they appear in the // MCInst in the order that they're listed. - std::vector > InOutOperands; + std::vector> InOutOperands; DagInit *Out = Def.getValueAsDag("OutOperandList"); DagInit *In = Def.getValueAsDag("InOperandList"); for (unsigned i = 0; i < Out->getNumArgs(); ++i) - InOutOperands.push_back(std::make_pair(Out->getArg(i), Out->getArgName(i))); + InOutOperands.push_back(std::make_pair(Out->getArg(i), + Out->getArgNameStr(i))); for (unsigned i = 0; i < In->getNumArgs(); ++i) - InOutOperands.push_back(std::make_pair(In->getArg(i), In->getArgName(i))); + InOutOperands.push_back(std::make_pair(In->getArg(i), + In->getArgNameStr(i))); // Search for tied operands, so that we can correctly instantiate // operands that are not explicitly represented in the encoding. @@ -1743,7 +1782,7 @@ static bool populateInstruction(CodeGenTarget &Target, } } - std::map > NumberedInsnOperands; + std::map> NumberedInsnOperands; std::set NumberedInsnOperandsNoTie; if (Target.getInstructionSet()-> getValueAsBit("decodePositionallyEncodedOperands")) { @@ -1828,7 +1867,7 @@ static bool populateInstruction(CodeGenTarget &Target, Name << "(" << SO.first << ", " << SO.second << ") => " << Vals[i].getName() << "\n"); - std::string Decoder = ""; + std::string Decoder; Record *TypeRecord = CGI.Operands[SO.first].Rec; RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod"); @@ -1852,7 +1891,7 @@ static bool populateInstruction(CodeGenTarget &Target, if (TypeRecord->isSubClassOf("RegisterOperand")) TypeRecord = TypeRecord->getValueAsDef("RegClass"); if (TypeRecord->isSubClassOf("RegisterClass")) { - Decoder = "Decode" + TypeRecord->getName() + "RegisterClass"; + Decoder = "Decode" + TypeRecord->getName().str() + "RegisterClass"; isReg = true; } else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) { Decoder = "DecodePointerLikeRegClass" + @@ -1917,33 +1956,13 @@ static bool populateInstruction(CodeGenTarget &Target, continue; } - std::string Decoder = ""; - - // At this point, we can locate the field, but we need to know how to - // interpret it. As a first step, require the target to provide callbacks - // for decoding register classes. - // FIXME: This need to be extended to handle instructions with custom - // decoder methods, and operands with (simple) MIOperandInfo's. TypedInit *TI = cast(Op.first); - RecordRecTy *Type = cast(TI->getType()); - Record *TypeRecord = Type->getRecord(); - bool isReg = false; - if (TypeRecord->isSubClassOf("RegisterOperand")) - TypeRecord = TypeRecord->getValueAsDef("RegClass"); - if (TypeRecord->isSubClassOf("RegisterClass")) { - Decoder = "Decode" + TypeRecord->getName() + "RegisterClass"; - isReg = true; - } else if (TypeRecord->isSubClassOf("PointerLikeRegClass")) { - Decoder = "DecodePointerLikeRegClass" + - utostr(TypeRecord->getValueAsInt("RegClassKind")); - isReg = true; - } - RecordVal *DecoderString = TypeRecord->getValue("DecoderMethod"); - StringInit *String = DecoderString ? - dyn_cast(DecoderString->getValue()) : nullptr; - if (!isReg && String && String->getValue() != "") - Decoder = String->getValue(); + // At this point, we can locate the decoder field, but we need to know how + // to interpret it. As a first step, require the target to provide + // callbacks for decoding register classes. + std::string Decoder = findOperandDecoderMethod(TI); + Record *TypeRecord = cast(TI->getType())->getRecord(); RecordVal *HasCompleteDecoderVal = TypeRecord->getValue("hasCompleteDecoder"); @@ -2009,7 +2028,6 @@ static bool populateInstruction(CodeGenTarget &Target, Operands[Opc] = InsnOperands; - #if 0 DEBUG({ // Dumps the instruction encoding bits. @@ -2062,7 +2080,7 @@ static void emitDecodeInstruction(formatted_raw_ostream &OS) { << " const uint8_t *Ptr = DecodeTable;\n" << " uint32_t CurFieldValue = 0;\n" << " DecodeStatus S = MCDisassembler::Success;\n" - << " for (;;) {\n" + << " while (true) {\n" << " ptrdiff_t Loc = Ptr - DecodeTable;\n" << " switch (*Ptr) {\n" << " default:\n" @@ -2230,8 +2248,8 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { // Parameterize the decoders based on namespace and instruction width. NumberedInstructions = Target.getInstructionsByEnumValue(); std::map, - std::vector > OpcMap; - std::map > Operands; + std::vector> OpcMap; + std::map> Operands; for (unsigned i = 0; i < NumberedInstructions.size(); ++i) { const CodeGenInstruction *Inst = NumberedInstructions[i]; @@ -2304,4 +2322,4 @@ void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, ROK, RFail, L).run(OS); } -} // End llvm namespace +} // end namespace llvm -- cgit v1.1