From ce0b21596585c6ddd828c54e5077ba0aecfae8fc Mon Sep 17 00:00:00 2001
From: dim <dim@FreeBSD.org>
Date: Tue, 18 Mar 2014 22:07:45 +0000
Subject: Add separate patch files for all the customizations we have currently
 applied to our copy of llvm/clang.  These can be applied in alphabetical
 order to a pristine llvm/clang 3.4 release source tree, to result in the same
 version used in FreeBSD.

This is intended to clearly document all the changes until now, which
mostly consist of cherry pickings from the respective upstream trunks,
plus a number of hand-written FreeBSD-specific ones.  Hopefully those
can eventually be cleaned up and sent upstream too.

MFC after:	1 week
X-MFC-With:	r263313
---
 .../patches/patch-r262261-llvm-r200130-sparc.diff  | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 contrib/llvm/patches/patch-r262261-llvm-r200130-sparc.diff

(limited to 'contrib/llvm/patches/patch-r262261-llvm-r200130-sparc.diff')

diff --git a/contrib/llvm/patches/patch-r262261-llvm-r200130-sparc.diff b/contrib/llvm/patches/patch-r262261-llvm-r200130-sparc.diff
new file mode 100644
index 0000000..aad6ae9
--- /dev/null
+++ b/contrib/llvm/patches/patch-r262261-llvm-r200130-sparc.diff
@@ -0,0 +1,45 @@
+Pull in r200130 from upstream llvm trunk (by Jakob Stoklund Olesen):
+
+  Fix swapped CASA operands.
+
+  Found by SingleSource/UnitTests/AtomicOps.c
+
+Introduced here: http://svn.freebsd.org/changeset/base/262261
+
+Index: lib/Target/Sparc/SparcISelLowering.cpp
+===================================================================
+--- lib/Target/Sparc/SparcISelLowering.cpp
++++ lib/Target/Sparc/SparcISelLowering.cpp
+@@ -2972,7 +2972,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr
+   // loop:
+   //   %val = phi %val0, %dest
+   //   %upd = op %val, %rs2
+-  //   %dest = cas %addr, %upd, %val
++  //   %dest = cas %addr, %val, %upd
+   //   cmp %val, %dest
+   //   bne loop
+   // done:
+@@ -3031,7 +3031,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr
+   }
+ 
+   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
+-    .addReg(AddrReg).addReg(UpdReg).addReg(ValReg)
++    .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
+     .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
+   BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
+   BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
+Index: test/CodeGen/SPARC/atomics.ll
+===================================================================
+--- test/CodeGen/SPARC/atomics.ll
++++ test/CodeGen/SPARC/atomics.ll
+@@ -64,8 +64,8 @@ entry:
+ 
+ ; CHECK-LABEL: test_load_add_32
+ ; CHECK: membar
+-; CHECK: add
+-; CHECK: cas [%o0]
++; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
++; CHECK: cas [%o0], [[V]], [[U]]
+ ; CHECK: membar
+ define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
+ entry:
-- 
cgit v1.1