From 92318bc515d223b2eeebb665f76e131dd2318b2b Mon Sep 17 00:00:00 2001 From: kan Date: Thu, 10 Oct 2002 04:40:18 +0000 Subject: Gcc 3.2.1-prerelease from the FSF anoncvs repo gcc-3_2-branch on October 9th 2002 20:15 EST. --- contrib/gcc/config/arm/arm.h | 14 ++++---- contrib/gcc/config/arm/arm.md | 9 +++-- contrib/gcc/config/i386/i386.c | 63 +++++++++++++++++++++++----------- contrib/gcc/config/i386/i386.h | 23 ++++++++----- contrib/gcc/config/i386/linux64.h | 19 ++++------- contrib/gcc/config/i386/t-linux64 | 3 +- contrib/gcc/config/i386/winnt.c | 19 +++++------ contrib/gcc/config/rs6000/rs6000.md | 2 +- contrib/gcc/config/sparc/linux64.h | 67 ++++--------------------------------- contrib/gcc/config/sparc/sol2-bi.h | 29 +++------------- contrib/gcc/config/sparc/sparc.c | 1 - contrib/gcc/config/sparc/sparc.md | 25 ++++++++++---- contrib/gcc/config/sparc/t-linux64 | 14 ++++---- contrib/gcc/config/sparc/t-sol2-64 | 3 +- 14 files changed, 126 insertions(+), 165 deletions(-) (limited to 'contrib/gcc/config') diff --git a/contrib/gcc/config/arm/arm.h b/contrib/gcc/config/arm/arm.h index 5e8b5d9..c5431b5 100644 --- a/contrib/gcc/config/arm/arm.h +++ b/contrib/gcc/config/arm/arm.h @@ -1093,14 +1093,16 @@ enum reg_class /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) -#define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS) +#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) -/* For the Thumb the high registers cannot be used as base - registers when addressing quanitities in QI or HI mode. */ +/* For the Thumb the high registers cannot be used as base registers + when addressing quanitities in QI or HI mode; if we don't know the + mode, then we must be conservative. After reload we must also be + conservative, since we can't support SP+reg addressing, and we + can't fix up any bad substitutions. */ #define MODE_BASE_REG_CLASS(MODE) \ - (TARGET_ARM ? BASE_REGS : \ - (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \ - ? LO_REGS : BASE_REGS)) + (TARGET_ARM ? GENERAL_REGS : \ + (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows registers explicitly used in the rtl to be used as spill registers diff --git a/contrib/gcc/config/arm/arm.md b/contrib/gcc/config/arm/arm.md index b901504..5180c75 100644 --- a/contrib/gcc/config/arm/arm.md +++ b/contrib/gcc/config/arm/arm.md @@ -1837,7 +1837,8 @@ (match_operand:SI 1 "s_register_operand" "r") (match_operand:SI 2 "const_int_operand" "n") (match_operand:SI 3 "const_int_operand" "n")) - (const_int 0)))] + (const_int 0))) + (clobber (reg:CC CC_REGNUM))] "TARGET_ARM && (INTVAL (operands[3]) >= 0 && INTVAL (operands[3]) < 32 && INTVAL (operands[2]) > 0 @@ -8947,7 +8948,8 @@ [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 1) - (match_operand:SI 2 "const_int_operand" "n")))] + (match_operand:SI 2 "const_int_operand" "n"))) + (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" "* operands[2] = GEN_INT (1 << INTVAL (operands[2])); @@ -8963,7 +8965,8 @@ (not:SI (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") (const_int 1) - (match_operand:SI 2 "const_int_operand" "n"))))] + (match_operand:SI 2 "const_int_operand" "n")))) + (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" "* operands[2] = GEN_INT (1 << INTVAL (operands[2])); diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c index f07ebad..5e48715 100644 --- a/contrib/gcc/config/i386/i386.c +++ b/contrib/gcc/config/i386/i386.c @@ -284,25 +284,25 @@ struct processor_costs athlon_cost = { 8, /* "large" insn */ 9, /* MOVE_RATIO */ 4, /* cost for loading QImode using movzbl */ - {4, 5, 4}, /* cost of loading integer registers + {3, 4, 3}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {2, 3, 2}, /* cost of storing integer registers */ + {3, 4, 3}, /* cost of storing integer registers */ 4, /* cost of reg,reg fld/fst */ - {6, 6, 20}, /* cost of loading fp registers + {4, 4, 12}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {4, 4, 16}, /* cost of loading integer registers */ + {6, 6, 8}, /* cost of loading integer registers */ 2, /* cost of moving MMX register */ - {2, 2}, /* cost of loading MMX registers + {4, 4}, /* cost of loading MMX registers in SImode and DImode */ - {2, 2}, /* cost of storing MMX registers + {4, 4}, /* cost of storing MMX registers in SImode and DImode */ 2, /* cost of moving SSE register */ - {2, 2, 8}, /* cost of loading SSE registers + {4, 4, 6}, /* cost of loading SSE registers in SImode, DImode and TImode */ - {2, 2, 8}, /* cost of storing SSE registers + {4, 4, 5}, /* cost of storing SSE registers in SImode, DImode and TImode */ - 6, /* MMX or SSE register to integer */ + 5, /* MMX or SSE register to integer */ 64, /* size of prefetch block */ 6, /* number of parallel prefetches */ }; @@ -1649,7 +1649,11 @@ classify_argument (mode, type, classes, bit_offset) { int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode); - int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + /* Variable sized structures are always passed on the stack. */ + if (mode == BLKmode && type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) + return 0; if (type && AGGREGATE_TYPE_P (type)) { @@ -3206,7 +3210,7 @@ q_regs_operand (op, mode) return 0; if (GET_CODE (op) == SUBREG) op = SUBREG_REG (op); - return QI_REG_P (op); + return ANY_QI_REG_P (op); } /* Return true if op is a NON_Q_REGS class register. */ @@ -6123,7 +6127,10 @@ print_operand_address (file, addr) int scale; if (! ix86_decompose_address (addr, &parts)) - abort (); + { + output_operand_lossage ("Wrong address expression or operand constraint"); + return; + } base = parts.base; index = parts.index; @@ -8237,7 +8244,7 @@ ix86_expand_int_movcc (operands) clob = gen_rtx_CLOBBER (VOIDmode, clob); tmp = gen_rtx_SET (VOIDmode, out, tmp); - tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob)); + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, copy_rtx (tmp), clob)); emit_insn (tmp); } else @@ -12355,17 +12362,33 @@ ix86_register_move_cost (mode, class1, class2) enum reg_class class1, class2; { /* In case we require secondary memory, compute cost of the store followed - by load. In case of copying from general_purpose_register we may emit - multiple stores followed by single load causing memory size mismatch - stall. Count this as arbitarily high cost of 20. */ + by load. In order to avoid bad register allocation choices, we need + for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */ + if (ix86_secondary_memory_needed (class1, class2, mode, 0)) { - int add_cost = 0; + int cost = 1; + + cost += MAX (MEMORY_MOVE_COST (mode, class1, 0), + MEMORY_MOVE_COST (mode, class1, 1)); + cost += MAX (MEMORY_MOVE_COST (mode, class2, 0), + MEMORY_MOVE_COST (mode, class2, 1)); + + /* In case of copying from general_purpose_register we may emit multiple + stores followed by single load causing memory size mismatch stall. + Count this as arbitarily high cost of 20. */ if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode)) - add_cost = 20; - return (MEMORY_MOVE_COST (mode, class1, 0) - + MEMORY_MOVE_COST (mode, class2, 1) + add_cost); + cost += 20; + + /* In the case of FP/MMX moves, the registers actually overlap, and we + have to switch modes in order to treat them differently. */ + if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2)) + || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1))) + cost += 20; + + return cost; } + /* Moves between SSE/MMX and integer unit are expensive. */ if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2) || SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h index 07502a2..58d2c433 100644 --- a/contrib/gcc/config/i386/i386.h +++ b/contrib/gcc/config/i386/i386.h @@ -584,9 +584,13 @@ extern int ix86_arch; %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \ -D__pentium__mmx__ \ %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\ -%{march=pentiumpro|march=i686:-D__i686 -D__i686__ \ +%{march=pentiumpro|march=i686|march=pentium2|march=pentium3:-D__i686 -D__i686__ \ -D__pentiumpro -D__pentiumpro__ \ %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\ +%{march=march=pentium2|march=pentium3: -D__pentium2 -D__pentium2__\ + %{!mcpu*:-D__tune_pentium2__ }}\ +%{march=pentium3: -D__pentium3 -D__pentium3__\ + %{!mcpu*:-D__tune_pentium3__ }}\ %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \ %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\ @@ -601,7 +605,7 @@ extern int ix86_arch; %{m386|mcpu=i386:-D__tune_i386__ }\ %{m486|mcpu=i486:-D__tune_i486__ }\ %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\ -%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \ +%{mpentiumpro|mcpu=pentiumpro|mcpu=i686|mcpu=pentium2|mcpu=pentium3:-D__tune_i686__ \ -D__tune_pentiumpro__ }\ %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\ %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ @@ -609,17 +613,17 @@ extern int ix86_arch; %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\ -D__tune_athlon_sse__ }\ %{mcpu=pentium4:-D__tune_pentium4__ }\ -%{march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\ +%{march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4|msse|msse2:\ -D__SSE__ }\ %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\ |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ -|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\ +|march=athlon-mp|march=pentium2|march=pentium3|march=pentium4|mmx|msse|m3dnow: -D__MMX__ }\ %{march=k6-2|march=k6-3\ |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ -|march=athlon-mp: -D__3dNOW__ }\ +|march=athlon-mp|m3dnow: -D__3dNOW__ }\ %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\ |march=athlon-mp: -D__3dNOW_A__ }\ -%{march=pentium4: -D__SSE2__ }\ +%{march=pentium4|msse2: -D__SSE2__ }\ %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" #ifndef CPP_CPU_SPEC @@ -756,8 +760,11 @@ extern int ix86_arch; #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) -/* Allocation boundary for the code of a function. */ -#define FUNCTION_BOUNDARY 16 +/* Minimum allocation boundary for the code of a function. */ +#define FUNCTION_BOUNDARY 8 + +/* C++ stores the virtual bit in the lowest bit of function pointers. */ +#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn /* Alignment of field after `int : 0' in a structure. */ diff --git a/contrib/gcc/config/i386/linux64.h b/contrib/gcc/config/i386/linux64.h index 6158431..8a0bfbe 100644 --- a/contrib/gcc/config/i386/linux64.h +++ b/contrib/gcc/config/i386/linux64.h @@ -50,21 +50,14 @@ Boston, MA 02111-1307, USA. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ - "%{m32:%{!shared: \ - %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \ - %{!p:%{profile:gcrt1.o%s} %{!profile:crt1.o%s}}}} \ - crti.o%s %{static:crtbeginT.o%s}\ - %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}} \ - %{!m32:%{!shared: \ - %{pg:/usr/lib64/gcrt1.o%s} %{!pg:%{p:/usr/lib64/gcrt1.o%s} \ - %{!p:%{profile:/usr/lib64/gcrt1.o%s} %{!profile:/usr/lib64/crt1.o%s}}}}\ - /usr/lib64/crti.o%s %{static:crtbeginT.o%s} \ - %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}}" + "%{!shared: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \ + %{!p:%{profile:gcrt1.o%s} %{!profile:crt1.o%s}}}} \ + crti.o%s %{static:crtbeginT.o%s} \ + %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" #undef ENDFILE_SPEC -#define ENDFILE_SPEC "\ - %{m32:%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s} \ - %{!m32:%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s}" +#define ENDFILE_SPEC "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" #define MULTILIB_DEFAULTS { "m64" } diff --git a/contrib/gcc/config/i386/t-linux64 b/contrib/gcc/config/i386/t-linux64 index 46a7caa..31b6ad4 100644 --- a/contrib/gcc/config/i386/t-linux64 +++ b/contrib/gcc/config/i386/t-linux64 @@ -6,10 +6,9 @@ SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ MULTILIB_OPTIONS = m64/m32 MULTILIB_DIRNAMES = 64 32 +MULTILIB_OSDIRNAMES = ../lib64 ../lib LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o - -SHLIB_SLIBDIR_SUFFIXES = 64:64 32: diff --git a/contrib/gcc/config/i386/winnt.c b/contrib/gcc/config/i386/winnt.c index 9d955df..6928a8c 100644 --- a/contrib/gcc/config/i386/winnt.c +++ b/contrib/gcc/config/i386/winnt.c @@ -76,6 +76,15 @@ ix86_handle_dll_attribute (node, name, args, flags, no_add_attrs) } } + /* `extern' needn't be specified with dllimport. + Specify `extern' now and hope for the best. Sigh. */ + else if (TREE_CODE (*node) == VAR_DECL + && is_attribute_p ("dllimport", name)) + { + DECL_EXTERNAL (*node) = 1; + TREE_PUBLIC (*node) = 1; + } + return NULL_TREE; } @@ -300,16 +309,6 @@ i386_pe_mark_dllimport (decl) return; } - /* `extern' needn't be specified with dllimport. - Specify `extern' now and hope for the best. Sigh. */ - if (TREE_CODE (decl) == VAR_DECL - /* ??? Is this test for vtables needed? */ - && !DECL_VIRTUAL_P (decl)) - { - DECL_EXTERNAL (decl) = 1; - TREE_PUBLIC (decl) = 1; - } - newname = alloca (strlen (oldname) + 11); sprintf (newname, "@i._imp__%s", oldname); diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md index f032bfd..6e86d73 100644 --- a/contrib/gcc/config/rs6000/rs6000.md +++ b/contrib/gcc/config/rs6000/rs6000.md @@ -9657,7 +9657,7 @@ (define_insn "load_toc_v4_PIC_2" [(set (match_operand:SI 0 "register_operand" "=r") - (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") + (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "b") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" diff --git a/contrib/gcc/config/sparc/linux64.h b/contrib/gcc/config/sparc/linux64.h index 1dfd97f..c7d8f491 100644 --- a/contrib/gcc/config/sparc/linux64.h +++ b/contrib/gcc/config/sparc/linux64.h @@ -1,5 +1,5 @@ /* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF. - Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000, 2002 Free Software Foundation, Inc. Contributed by David S. Miller (davem@caip.rutgers.edu) This file is part of GNU CC. @@ -56,38 +56,12 @@ Boston, MA 02111-1307, USA. */ #undef STARTFILE_SPEC -#define STARTFILE_SPEC32 \ +#define STARTFILE_SPEC \ "%{!shared: \ - %{pg:/usr/lib/gcrt1.o%s} %{!pg:%{p:/usr/lib/gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\ - /usr/lib/crti.o%s %{static:crtbeginT.o%s}\ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + crti.o%s %{static:crtbeginT.o%s}\ %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" -#define STARTFILE_SPEC64 \ - "%{!shared: \ - %{pg:/usr/lib64/gcrt1.o%s} %{!pg:%{p:/usr/lib64/gcrt1.o%s} %{!p:/usr/lib64/crt1.o%s}}}\ - /usr/lib64/crti.o%s %{static:crtbeginT.o%s}\ - %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" - -#ifdef SPARC_BI_ARCH - -#if DEFAULT_ARCH32_P -#define STARTFILE_SPEC "\ -%{m32:" STARTFILE_SPEC32 "} \ -%{m64:" STARTFILE_SPEC64 "} \ -%{!m32:%{!m64:" STARTFILE_SPEC32 "}}" -#else -#define STARTFILE_SPEC "\ -%{m32:" STARTFILE_SPEC32 "} \ -%{m64:" STARTFILE_SPEC64 "} \ -%{!m32:%{!m64:" STARTFILE_SPEC64 "}}" -#endif - -#else - -#define STARTFILE_SPEC STARTFILE_SPEC64 - -#endif - /* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on the GNU/Linux magical crtend.o file (see crtstuff.c) which provides part of the support for getting C++ file-scope static @@ -96,36 +70,9 @@ Boston, MA 02111-1307, USA. */ #undef ENDFILE_SPEC -#define ENDFILE_SPEC32 \ - "%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib/crtn.o%s" - -#define ENDFILE_SPEC64 \ - "%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s" - -#define ENDFILE_SPEC_COMMON \ - "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" - -#ifdef SPARC_BI_ARCH - -#if DEFAULT_ARCH32_P -#define ENDFILE_SPEC "\ -%{m32:" ENDFILE_SPEC32 "} \ -%{m64:" ENDFILE_SPEC64 "} \ -%{!m32:%{!m64:" ENDFILE_SPEC32 "}} " \ -ENDFILE_SPEC_COMMON -#else -#define ENDFILE_SPEC "\ -%{m32:" ENDFILE_SPEC32 "} \ -%{m64:" ENDFILE_SPEC64 "} \ -%{!m32:%{!m64:" ENDFILE_SPEC64 "}} " \ -ENDFILE_SPEC_COMMON -#endif - -#else - -#define ENDFILE_SPEC ENDFILE_SPEC64 " " ENDFILE_SPEC_COMMON - -#endif +#define ENDFILE_SPEC \ + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s\ + %{ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" /* The GNU C++ standard library requires that these macros be defined. */ #undef CPLUSPLUS_CPP_SPEC diff --git a/contrib/gcc/config/sparc/sol2-bi.h b/contrib/gcc/config/sparc/sol2-bi.h index 9828d63..e19e888 100644 --- a/contrib/gcc/config/sparc/sol2-bi.h +++ b/contrib/gcc/config/sparc/sol2-bi.h @@ -72,30 +72,6 @@ %{!mcpu*:%(asm_cpu_default)} \ " -#define STARTFILE_SPEC32 "\ -%{ansi:values-Xc.o%s} \ -%{!ansi: \ - %{traditional:values-Xt.o%s} \ - %{!traditional:values-Xa.o%s}}" - -#define STARTFILE_SPEC64 "\ -%{ansi:/usr/lib/sparcv9/values-Xc.o%s} \ -%{!ansi: \ - %{traditional:/usr/lib/sparcv9/values-Xt.o%s} \ - %{!traditional:/usr/lib/sparcv9/values-Xa.o%s}}" - -#if DEFAULT_ARCH32_P -#define STARTFILE_ARCH_SPEC "\ -%{m32:" STARTFILE_SPEC32 "} \ -%{m64:" STARTFILE_SPEC64 "} \ -%{!m32:%{!m64:" STARTFILE_SPEC32 "}}" -#else -#define STARTFILE_ARCH_SPEC "\ -%{m32:" STARTFILE_SPEC32 "} \ -%{m64:" STARTFILE_SPEC64 "} \ -%{!m32:%{!m64:" STARTFILE_SPEC64 "}}" -#endif - #undef STARTFILE_SPEC #define STARTFILE_SPEC "%{!shared: \ %{!symbolic: \ @@ -103,7 +79,10 @@ %{!p: \ %{pg:gcrt1.o%s gmon.o%s} \ %{!pg:crt1.o%s}}}} \ - crti.o%s " STARTFILE_ARCH_SPEC " \ + crti.o%s \ + %{ansi:values-Xc.o%s} \ + %{!ansi: %{traditional:values-Xt.o%s} \ + %{!traditional:values-Xa.o%s}} \ crtbegin.o%s" #undef CPP_CPU_DEFAULT_SPEC diff --git a/contrib/gcc/config/sparc/sparc.c b/contrib/gcc/config/sparc/sparc.c index 6ef28141c..c23cbef 100644 --- a/contrib/gcc/config/sparc/sparc.c +++ b/contrib/gcc/config/sparc/sparc.c @@ -8650,7 +8650,6 @@ set_extends (insn) return INTVAL (op1) >= 0; return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); } - case ASHIFT: case LSHIFTRT: return GET_MODE (SET_SRC (pat)) == SImode; /* Positive integers leave the high bits zero. */ diff --git a/contrib/gcc/config/sparc/sparc.md b/contrib/gcc/config/sparc/sparc.md index ebb6768..746dc72 100644 --- a/contrib/gcc/config/sparc/sparc.md +++ b/contrib/gcc/config/sparc/sparc.md @@ -2517,7 +2517,7 @@ ; }") -;; Be careful, fmovd does not exist when !arch64. +;; Be careful, fmovd does not exist when !v9. ;; We match MEM moves directly when we have correct even ;; numbered registers, but fall into splits otherwise. ;; The constraint ordering here is really important to @@ -2531,9 +2531,9 @@ (define_insn "*movdi_insn_sp32_v9" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f") + "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W") (match_operand:DI 1 "input_operand" - " J,J,U,T,r,o,i,r, f, T, o, f, f"))] + " J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))] "! TARGET_ARCH64 && TARGET_V9 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ @@ -2549,9 +2549,13 @@ ldd\\t%1, %0 # # - #" - [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*") - (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2")]) + # + fmovd\\t%1, %0 + ldd\\t%1, %0 + std\\t%1, %0" + [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore") + (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*") + (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")]) (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" @@ -2861,7 +2865,14 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "const_double_operand" ""))] - "! TARGET_ARCH64 && reload_completed" + "reload_completed + && (! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))))" [(clobber (const_int 0))] " { diff --git a/contrib/gcc/config/sparc/t-linux64 b/contrib/gcc/config/sparc/t-linux64 index a648626..3e3fa4c 100644 --- a/contrib/gcc/config/sparc/t-linux64 +++ b/contrib/gcc/config/sparc/t-linux64 @@ -1,8 +1,6 @@ -MULTILIB_OPTIONS = m64/m32 mno-app-regs|mcmodel=medany -MULTILIB_DIRNAMES = 64 32 alt -MULTILIB_MATCHES = mcmodel?medany=mcmodel?medmid -MULTILIB_EXCEPTIONS = m32/mno-app-regs* m32/mcmodel=* -MULTILIB_EXCLUSIONS = m32/!m64/mno-app-regs m32/!m64/mcmodel=medany +MULTILIB_OPTIONS = m64/m32 +MULTILIB_DIRNAMES = 64 32 +MULTILIB_OSDIRNAMES = ../lib64 ../lib LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib @@ -10,10 +8,12 @@ INSTALL_LIBGCC = install-multilib EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o \ crtfastmath.o -SHLIB_SLIBDIR_SUFFIXES = 64:64 32: - # Override t-slibgcc-elf-ver to export some libgcc symbols with # the symbol versions that glibc used. # Avoid the t-linux version file. SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver \ $(srcdir)/config/sparc/libgcc-sparc-glibc.ver + +CRTSTUFF_T_CFLAGS = `if test x$$($(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) \ + -print-multi-os-directory) \ + = x../lib64; then echo -mcmodel=medany; fi` diff --git a/contrib/gcc/config/sparc/t-sol2-64 b/contrib/gcc/config/sparc/t-sol2-64 index 39204d7..3c15f0a 100644 --- a/contrib/gcc/config/sparc/t-sol2-64 +++ b/contrib/gcc/config/sparc/t-sol2-64 @@ -1,11 +1,10 @@ MULTILIB_OPTIONS = m32/m64 MULTILIB_DIRNAMES = sparcv7 sparcv9 MULTILIB_MATCHES = +MULTILIB_OSDIRNAMES = . sparcv9 LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o gmon.o crt1.o crti.o crtn.o gcrt1.o \ crtfastmath.o - -SHLIB_SLIBDIR_SUFFIXES = sparcv9:/sparcv9 sparcv7: -- cgit v1.1