From 366976642281939a5ef910427ef046ec6f72af8a Mon Sep 17 00:00:00 2001 From: kan Date: Tue, 17 Sep 2002 04:03:37 +0000 Subject: Gcc 3.2.1-prerelease from the FSF anoncvs repo gcc-3_2-branch on 16-Sep-2002 13:23:11 EDT. --- contrib/gcc/config/alpha/alpha.md | 2 +- contrib/gcc/config/rs6000/linux64.h | 53 ++++ contrib/gcc/config/rs6000/rs6000.c | 477 ++++++++++++++---------------------- contrib/gcc/config/rs6000/rs6000.md | 359 ++++++++++++--------------- contrib/gcc/config/rs6000/sysv4.h | 32 +++ contrib/gcc/config/sparc/linux64.h | 2 +- contrib/gcc/config/sparc/t-netbsd64 | 12 +- 7 files changed, 432 insertions(+), 505 deletions(-) (limited to 'contrib/gcc/config') diff --git a/contrib/gcc/config/alpha/alpha.md b/contrib/gcc/config/alpha/alpha.md index 785a61d..1875b80 100644 --- a/contrib/gcc/config/alpha/alpha.md +++ b/contrib/gcc/config/alpha/alpha.md @@ -2374,7 +2374,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "abstf2" [(parallel [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) + (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) (use (match_dup 2))])] "TARGET_HAS_XFLOATING_LIBS" { diff --git a/contrib/gcc/config/rs6000/linux64.h b/contrib/gcc/config/rs6000/linux64.h index f84e1e3..ce8f7ac 100644 --- a/contrib/gcc/config/rs6000/linux64.h +++ b/contrib/gcc/config/rs6000/linux64.h @@ -37,6 +37,12 @@ Boston, MA 02111-1307, USA. */ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc64" +#undef ASM_SPEC +#define ASM_SPEC "%{.s: %{mregnames} %{mno-regnames}} \ +%{.S: %{mregnames} %{mno-regnames}} \ +%{mlittle} %{mlittle-endian} %{mbig} %{mbig-endian} \ +%{v:-V} %{Qy:} %{!Qn:-Qy} -a64 %(asm_cpu) %{Wa,*:%*}" + /* 64-bit PowerPC Linux always has a TOC. */ #undef TARGET_NO_TOC #define TARGET_NO_TOC 0 @@ -65,6 +71,7 @@ Boston, MA 02111-1307, USA. */ #define USER_LABEL_PREFIX "" /* AIX word-aligns FP doubles but doubleword-aligns 64-bit ints. */ +#undef ADJUST_FIELD_ALIGN #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ (TYPE_MODE (TREE_CODE (TREE_TYPE (FIELD)) == ARRAY_TYPE \ ? get_inner_array_type (FIELD) \ @@ -327,3 +334,49 @@ do \ sym_lineno += 1; \ } \ while (0) + +/* Similarly, we want the function code label here. */ +#define DBX_OUTPUT_BRAC(FILE, NAME, BRAC) \ + do \ + { \ + const char *flab; \ + fprintf (FILE, "%s%d,0,0,", ASM_STABN_OP, BRAC); \ + assemble_name (FILE, NAME); \ + putc ('-', FILE); \ + if (current_function_func_begin_label != NULL_TREE) \ + flab = IDENTIFIER_POINTER (current_function_func_begin_label); \ + else \ + { \ + putc ('.', FILE); \ + flab = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ + } \ + assemble_name (FILE, flab); \ + putc ('\n', FILE); \ + } \ + while (0) + +#define DBX_OUTPUT_LBRAC(FILE, NAME) DBX_OUTPUT_BRAC (FILE, NAME, N_LBRAC) +#define DBX_OUTPUT_RBRAC(FILE, NAME) DBX_OUTPUT_BRAC (FILE, NAME, N_RBRAC) + +/* Another case where we want the dot name. */ +#define DBX_OUTPUT_NFUN(FILE, LSCOPE, DECL) \ + do \ + { \ + fprintf (FILE, "%s\"\",%d,0,0,", ASM_STABS_OP, N_FUN); \ + assemble_name (FILE, LSCOPE); \ + fputs ("-.", FILE); \ + assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ + putc ('\n', FILE); \ + } \ + while (0) + +/* Override sysv4.h as these are ABI_V4 only. */ +#undef ASM_OUTPUT_REG_PUSH +#undef ASM_OUTPUT_REG_POP + +/* Select a format to encode pointers in exception handling data. CODE + is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is + true if the symbol may be affected by dynamic relocations. */ +#undef ASM_PREFERRED_EH_DATA_FORMAT +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ + (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_udata8) diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c index 92b1d64..ad9df44 100644 --- a/contrib/gcc/config/rs6000/rs6000.c +++ b/contrib/gcc/config/rs6000/rs6000.c @@ -120,7 +120,6 @@ static int rs6000_sr_alias_set; static void rs6000_add_gc_roots PARAMS ((void)); static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); -static rtx expand_block_move_mem PARAMS ((enum machine_mode, rtx, rtx)); static void validate_condition_mode PARAMS ((enum rtx_code, enum machine_mode)); static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); @@ -4909,21 +4908,6 @@ altivec_init_builtins (void) } -/* Generate a memory reference for expand_block_move, copying volatile, - and other bits from an original memory reference. */ - -static rtx -expand_block_move_mem (mode, addr, orig_mem) - enum machine_mode mode; - rtx addr; - rtx orig_mem; -{ - rtx mem = gen_rtx_MEM (mode, addr); - - MEM_COPY_ATTRIBUTES (mem, orig_mem); - return mem; -} - /* Expand a block move operation, and return 1 if successful. Return 0 if we should let the compiler generate normal code. @@ -4946,14 +4930,6 @@ expand_block_move (operands) int align; int bytes; int offset; - int num_reg; - int i; - rtx src_reg; - rtx dest_reg; - rtx src_addr; - rtx dest_addr; - rtx tmp_reg; - rtx stores[MAX_MOVE_REG]; int move_bytes; /* If this is not a fixed size move, just call memcpy */ @@ -4975,14 +4951,17 @@ expand_block_move (operands) if (bytes > (TARGET_POWERPC64 ? 64 : 32)) return 0; - /* Move the address into scratch registers. */ - dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0)); - src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); - if (TARGET_STRING) /* string instructions are available */ { - for ( ; bytes > 0; bytes -= move_bytes) + for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) { + union { + rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx)); + rtx (*mov) PARAMS ((rtx, rtx)); + } gen_func; + enum machine_mode mode = BLKmode; + rtx src, dest; + if (bytes > 24 /* move up to 32 bytes at a time */ && ! fixed_regs[5] && ! fixed_regs[6] @@ -4994,15 +4973,7 @@ expand_block_move (operands) && ! fixed_regs[12]) { move_bytes = (bytes > 32) ? 32 : bytes; - emit_insn (gen_movstrsi_8reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT ((move_bytes == 32) - ? 0 : move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_8reg; } else if (bytes > 16 /* move up to 24 bytes at a time */ && ! fixed_regs[5] @@ -5013,14 +4984,7 @@ expand_block_move (operands) && ! fixed_regs[10]) { move_bytes = (bytes > 24) ? 24 : bytes; - emit_insn (gen_movstrsi_6reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_6reg; } else if (bytes > 8 /* move up to 16 bytes at a time */ && ! fixed_regs[5] @@ -5029,14 +4993,7 @@ expand_block_move (operands) && ! fixed_regs[8]) { move_bytes = (bytes > 16) ? 16 : bytes; - emit_insn (gen_movstrsi_4reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_4reg; } else if (bytes >= 8 && TARGET_POWERPC64 /* 64-bit loads and stores require word-aligned @@ -5044,108 +5001,84 @@ expand_block_move (operands) && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) { move_bytes = 8; - tmp_reg = gen_reg_rtx (DImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (DImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (DImode, - dest_reg, orig_dest), - tmp_reg); + mode = DImode; + gen_func.mov = gen_movdi; } else if (bytes > 4 && !TARGET_POWERPC64) { /* move up to 8 bytes at a time */ move_bytes = (bytes > 8) ? 8 : bytes; - emit_insn (gen_movstrsi_2reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_2reg; } else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) { /* move 4 bytes */ move_bytes = 4; - tmp_reg = gen_reg_rtx (SImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (SImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (SImode, - dest_reg, orig_dest), - tmp_reg); + mode = SImode; + gen_func.mov = gen_movsi; } else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT)) { /* move 2 bytes */ move_bytes = 2; - tmp_reg = gen_reg_rtx (HImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (HImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (HImode, - dest_reg, orig_dest), - tmp_reg); + mode = HImode; + gen_func.mov = gen_movhi; } else if (bytes == 1) /* move 1 byte */ { move_bytes = 1; - tmp_reg = gen_reg_rtx (QImode); - emit_move_insn (tmp_reg, - expand_block_move_mem (QImode, - src_reg, orig_src)); - emit_move_insn (expand_block_move_mem (QImode, - dest_reg, orig_dest), - tmp_reg); + mode = QImode; + gen_func.mov = gen_movqi; } else { /* move up to 4 bytes at a time */ move_bytes = (bytes > 4) ? 4 : bytes; - emit_insn (gen_movstrsi_1reg (expand_block_move_mem (BLKmode, - dest_reg, - orig_dest), - expand_block_move_mem (BLKmode, - src_reg, - orig_src), - GEN_INT (move_bytes), - align_rtx)); + gen_func.movstrsi = gen_movstrsi_1reg; } - if (bytes > move_bytes) + src = adjust_address (orig_src, mode, offset); + dest = adjust_address (orig_dest, mode, offset); + + if (mode == BLKmode) { - if (! TARGET_POWERPC64) + /* Move the address into scratch registers. The movstrsi + patterns require zero offset. */ + if (!REG_P (XEXP (src, 0))) { - emit_insn (gen_addsi3 (src_reg, src_reg, - GEN_INT (move_bytes))); - emit_insn (gen_addsi3 (dest_reg, dest_reg, - GEN_INT (move_bytes))); + rtx src_reg = copy_addr_to_reg (XEXP (src, 0)); + src = replace_equiv_address (src, src_reg); } - else + set_mem_size (src, GEN_INT (move_bytes)); + + if (!REG_P (XEXP (dest, 0))) { - emit_insn (gen_adddi3 (src_reg, src_reg, - GEN_INT (move_bytes))); - emit_insn (gen_adddi3 (dest_reg, dest_reg, - GEN_INT (move_bytes))); + rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0)); + dest = replace_equiv_address (dest, dest_reg); } + set_mem_size (dest, GEN_INT (move_bytes)); + + emit_insn ((*gen_func.movstrsi) (dest, src, + GEN_INT (move_bytes & 31), + align_rtx)); + } + else + { + rtx tmp_reg = gen_reg_rtx (mode); + + emit_insn ((*gen_func.mov) (tmp_reg, src)); + emit_insn ((*gen_func.mov) (dest, tmp_reg)); } } } else /* string instructions not available */ { - num_reg = offset = 0; - for ( ; bytes > 0; (bytes -= move_bytes), (offset += move_bytes)) + rtx stores[MAX_MOVE_REG]; + int num_reg = 0; + int i; + + for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes) { - /* Calculate the correct offset for src/dest */ - if (offset == 0) - { - src_addr = src_reg; - dest_addr = dest_reg; - } - else - { - src_addr = plus_constant (src_reg, offset); - dest_addr = plus_constant (dest_reg, offset); - } + rtx (*gen_mov_func) PARAMS ((rtx, rtx)); + enum machine_mode mode; + rtx src, dest, tmp_reg; /* Generate the appropriate load and store, saving the stores for later. */ @@ -5155,56 +5088,35 @@ expand_block_move (operands) && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4))) { move_bytes = 8; - tmp_reg = gen_reg_rtx (DImode); - emit_insn (gen_movdi (tmp_reg, - expand_block_move_mem (DImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movdi (expand_block_move_mem (DImode, - dest_addr, - orig_dest), - tmp_reg); + mode = DImode; + gen_mov_func = gen_movdi; } else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT)) { move_bytes = 4; - tmp_reg = gen_reg_rtx (SImode); - emit_insn (gen_movsi (tmp_reg, - expand_block_move_mem (SImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movsi (expand_block_move_mem (SImode, - dest_addr, - orig_dest), - tmp_reg); + mode = SImode; + gen_mov_func = gen_movsi; } else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT)) { move_bytes = 2; - tmp_reg = gen_reg_rtx (HImode); - emit_insn (gen_movhi (tmp_reg, - expand_block_move_mem (HImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movhi (expand_block_move_mem (HImode, - dest_addr, - orig_dest), - tmp_reg); + mode = HImode; + gen_mov_func = gen_movhi; } else { move_bytes = 1; - tmp_reg = gen_reg_rtx (QImode); - emit_insn (gen_movqi (tmp_reg, - expand_block_move_mem (QImode, - src_addr, - orig_src))); - stores[num_reg++] = gen_movqi (expand_block_move_mem (QImode, - dest_addr, - orig_dest), - tmp_reg); + mode = QImode; + gen_mov_func = gen_movqi; } + src = adjust_address (orig_src, mode, offset); + dest = adjust_address (orig_dest, mode, offset); + tmp_reg = gen_reg_rtx (mode); + + emit_insn ((*gen_mov_func) (tmp_reg, src)); + stores[num_reg++] = (*gen_mov_func) (dest, tmp_reg); + if (num_reg >= MAX_MOVE_REG) { for (i = 0; i < num_reg; i++) @@ -7434,53 +7346,6 @@ first_reg_to_save () || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) break; - if (current_function_profile) - { - /* AIX must save/restore every register that contains a parameter - before/after the .__mcount call plus an additional register - for the static chain, if needed; use registers from 30 down to 22 - to do this. */ - if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) - { - int last_parm_reg, profile_first_reg; - - /* Figure out last used parameter register. The proper thing - to do is to walk incoming args of the function. A function - might have live parameter registers even if it has no - incoming args. */ - for (last_parm_reg = 10; - last_parm_reg > 2 && ! regs_ever_live [last_parm_reg]; - last_parm_reg--) - ; - - /* Calculate first reg for saving parameter registers - and static chain. - Skip reg 31 which may contain the frame pointer. */ - profile_first_reg = (33 - last_parm_reg - - (current_function_needs_context ? 1 : 0)); -#if TARGET_MACHO - /* Need to skip another reg to account for R31 being PICBASE - (when flag_pic is set) or R30 being used as the frame - pointer (when flag_pic is not set). */ - --profile_first_reg; -#endif - /* Do not save frame pointer if no parameters needs to be saved. */ - if (profile_first_reg == 31) - profile_first_reg = 32; - - if (first_reg > profile_first_reg) - first_reg = profile_first_reg; - } - - /* SVR4 may need one register to preserve the static chain. */ - else if (current_function_needs_context) - { - /* Skip reg 31 which may contain the frame pointer. */ - if (first_reg > 30) - first_reg = 30; - } - } - #if TARGET_MACHO if (flag_pic && current_function_uses_pic_offset_table && (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)) @@ -8124,91 +7989,88 @@ rs6000_emit_load_toc_table (fromprolog) rtx dest; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); - if (TARGET_ELF && DEFAULT_ABI != ABI_AIX) + if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) + { + rtx temp = (fromprolog + ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) + : gen_reg_rtx (Pmode)); + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); + rs6000_maybe_dead (emit_move_insn (dest, temp)); + } + else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) { - if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) + char buf[30]; + rtx tempLR = (fromprolog + ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) + : gen_reg_rtx (Pmode)); + rtx temp0 = (fromprolog + ? gen_rtx_REG (Pmode, 0) + : gen_reg_rtx (Pmode)); + rtx symF; + + /* possibly create the toc section */ + if (! toc_initialized) { - rtx temp = (fromprolog - ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) - : gen_reg_rtx (Pmode)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); - rs6000_maybe_dead (emit_move_insn (dest, temp)); + toc_section (); + function_section (current_function_decl); } - else if (flag_pic == 2) - { - char buf[30]; - rtx tempLR = (fromprolog - ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) - : gen_reg_rtx (Pmode)); - rtx temp0 = (fromprolog - ? gen_rtx_REG (Pmode, 0) - : gen_reg_rtx (Pmode)); - rtx symF; - - /* possibly create the toc section */ - if (! toc_initialized) - { - toc_section (); - function_section (current_function_decl); - } - - if (fromprolog) - { - rtx symL; - - ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); - symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); - symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, - symF))); - rs6000_maybe_dead (emit_move_insn (dest, tempLR)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, - symL, - symF))); - } - else - { - rtx tocsym; - static int reload_toc_labelno = 0; - tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); + if (fromprolog) + { + rtx symL; - ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); - symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno); + symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, - symF, - tocsym))); - rs6000_maybe_dead (emit_move_insn (dest, tempLR)); - rs6000_maybe_dead (emit_move_insn (temp0, - gen_rtx_MEM (Pmode, dest))); - } - rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); - } - else if (flag_pic == 0 && TARGET_MINIMAL_TOC) - { - /* This is for AIX code running in non-PIC ELF. */ - char buf[30]; - rtx realsym; - ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); - realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - - rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); - rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno); + symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR, + symF))); + rs6000_maybe_dead (emit_move_insn (dest, tempLR)); + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, + symL, + symF))); } else - abort (); + { + rtx tocsym; + static int reload_toc_labelno = 0; + + tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name); + + ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); + symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, + symF, + tocsym))); + rs6000_maybe_dead (emit_move_insn (dest, tempLR)); + rs6000_maybe_dead (emit_move_insn (temp0, + gen_rtx_MEM (Pmode, dest))); + } + rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); } - else + else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) + { + /* This is for AIX code running in non-PIC ELF32. */ + char buf[30]; + rtx realsym; + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); + realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); + + rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); + rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); + } + else if (DEFAULT_ABI == ABI_AIX) { if (TARGET_32BIT) - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); + rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); else - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); + rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); } + else + abort (); } int @@ -10238,8 +10100,17 @@ output_toc (file, x, labelno, mode) abort ();/* It would be easy to make this work, but it doesn't now. */ if (POINTER_SIZE > GET_MODE_BITSIZE (mode)) - lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), - POINTER_SIZE, &low, &high, 0); + { +#if HOST_BITS_PER_WIDE_INT == 32 + lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), + POINTER_SIZE, &low, &high, 0); +#else + low |= high << 32; + low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); + high = (HOST_WIDE_INT) low >> 32; + low &= 0xffffffff; +#endif + } if (TARGET_64BIT) { @@ -10457,10 +10328,13 @@ rs6000_gen_section_name (buf, filename, section_desc) void output_profile_hook (labelno) - int labelno; + int labelno ATTRIBUTE_UNUSED; { if (DEFAULT_ABI == ABI_AIX) { +#ifdef NO_PROFILE_COUNTERS + emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0); +#else char buf[30]; const char *label_name; rtx fun; @@ -10471,6 +10345,7 @@ output_profile_hook (labelno) emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, fun, Pmode); +#endif } else if (DEFAULT_ABI == ABI_DARWIN) { @@ -10504,6 +10379,7 @@ output_function_profiler (file, labelno) int labelno; { char buf[100]; + int save_lr = 8; ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); switch (DEFAULT_ABI) @@ -10512,13 +10388,21 @@ output_function_profiler (file, labelno) abort (); case ABI_V4: + save_lr = 4; + /* Fall through. */ + case ABI_AIX_NODESC: + if (!TARGET_32BIT) + { + warning ("no profiling of 64-bit code for this ABI"); + return; + } fprintf (file, "\tmflr %s\n", reg_names[0]); if (flag_pic == 1) { fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); asm_fprintf (file, "\tmflr %s\n", reg_names[12]); asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]); assemble_name (file, buf); @@ -10526,8 +10410,8 @@ output_function_profiler (file, labelno) } else if (flag_pic > 1) { - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); /* Now, we need to get the address of the label. */ fputs ("\tbl 1f\n\t.long ", file); assemble_name (file, buf); @@ -10543,27 +10427,32 @@ output_function_profiler (file, labelno) asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]); assemble_name (file, buf); fputs ("@ha\n", file); - asm_fprintf (file, "\t{st|stw} %s,4(%s)\n", - reg_names[0], reg_names[1]); + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[0], save_lr, reg_names[1]); asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]); assemble_name (file, buf); asm_fprintf (file, "@l(%s)\n", reg_names[12]); } - if (current_function_needs_context) - asm_fprintf (file, "\tmr %s,%s\n", - reg_names[30], reg_names[STATIC_CHAIN_REGNUM]); - fprintf (file, "\tbl %s\n", RS6000_MCOUNT); - if (current_function_needs_context) - asm_fprintf (file, "\tmr %s,%s\n", - reg_names[STATIC_CHAIN_REGNUM], reg_names[30]); + if (current_function_needs_context && DEFAULT_ABI == ABI_AIX_NODESC) + { + asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], + 12, reg_names[1]); + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); + asm_fprintf (file, "\t{l|lwz} %s,%d(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], + 12, reg_names[1]); + } + else + /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */ + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); break; case ABI_AIX: case ABI_DARWIN: /* Don't do anything, done in output_profile_hook (). */ break; - } } diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md index 5188ce5..f032bfd 100644 --- a/contrib/gcc/config/rs6000/rs6000.md +++ b/contrib/gcc/config/rs6000/rs6000.md @@ -9641,7 +9641,7 @@ [(set (match_operand:SI 0 "register_operand" "=l") (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1)] 7)] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "bl %1\\n%1:" [(set_attr "type" "branch") (set_attr "length" "4")]) @@ -9650,7 +9650,7 @@ [(set (match_operand:SI 0 "register_operand" "=l") (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "bl %1\\n\\t.long %2-%1+4\\n%1:" [(set_attr "type" "branch") (set_attr "length" "8")]) @@ -9660,7 +9660,7 @@ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] - "TARGET_ELF && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" "{l|lwz} %0,%2-%3(%1)" [(set_attr "type" "load")]) @@ -11253,15 +11253,14 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11292,46 +11291,43 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (le:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 - {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 + {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11481,37 +11477,34 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "8,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11525,14 +11518,13 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "! TARGET_POWERPC64" - "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -11562,34 +11554,32 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (leu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -11597,13 +11587,12 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + [(set (match_dup 0) + (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11648,13 +11637,12 @@ "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11683,44 +11671,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11815,46 +11800,43 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -11905,21 +11887,20 @@ (clobber (match_scratch:SI 3 ""))] "TARGET_POWER && reload_completed" [(parallel [(set (match_dup 0) - (ge:SI (match_dup 1) (match_dup 2))) - (clobber (match_dup 3))]) + (ge:SI (match_dup 1) (match_dup 2))) + (clobber (match_dup 3))]) (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" + "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -11948,44 +11929,41 @@ "TARGET_POWER && reload_completed" [(set (match_dup 4) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 + doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12130,39 +12108,36 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 - {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 + {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 + {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,8,12,12")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_neg_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12178,16 +12153,15 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gpc_reg_operand" "r,r"))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r,r")))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" [(set_attr "length" "12")]) (define_insn "" @@ -12219,36 +12193,34 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) - (and:SI (neg:SI (geu:SI (match_dup 1) - (match_dup 2))) - (match_dup 3))) + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 - {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 + {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 + {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 # #" [(set_attr "type" "compare") (set_attr "length" "12,12,16,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -12256,13 +12228,11 @@ (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12394,13 +12364,12 @@ [(set_attr "length" "12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:DI 2 "gpc_reg_operand" "r"))) - (clobber (match_scratch:DI 3 "=&r"))] + (match_operand:DI 2 "gpc_reg_operand" "r")))] "TARGET_POWERPC64" - "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" + "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" [(set_attr "length" "12")]) (define_insn "" @@ -12461,92 +12430,85 @@ "TARGET_POWERPC64 && reload_completed" [(set (match_dup 3) (plus:DI (gt:DI (match_dup 1) (const_int 0)) - (match_dup 2))) + (match_dup 2))) (set (match_dup 0) (compare:CC (match_dup 3) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64" "@ - {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 + {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:SI 3 ""))] + (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 "=&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64" "@ - addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 + addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") (const_int 0)) (match_operand:DI 2 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_scratch:DI 3 ""))] + (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) - (clobber (match_dup 3))]) - (set (match_dup 4) + (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gpc_reg_operand" "r"))) - (clobber (match_scratch:SI 4 "=&r"))] + (match_operand:SI 3 "gpc_reg_operand" "r")))] "TARGET_POWER" - "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" + "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" [(set_attr "length" "12")]) (define_insn "" @@ -12574,45 +12536,41 @@ (clobber (match_scratch:SI 4 ""))] "TARGET_POWER && reload_completed" [(set (match_dup 4) - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER" "@ - doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 + doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 #" [(set_attr "type" "compare") (set_attr "length" "12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWER && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") @@ -12731,15 +12689,14 @@ [(set_attr "length" "8,12")]) (define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_short_operand" "I,rI")) - (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) - (clobber (match_scratch:DI 4 "=&r,&r"))] + (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" + addic %0,%1,%k2\;addze %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" [(set_attr "length" "8,12")]) (define_insn "" @@ -12770,7 +12727,7 @@ "! TARGET_POWERPC64 && reload_completed" [(set (match_dup 4) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) - (match_dup 3))) + (match_dup 3))) (set (match_dup 0) (compare:CC (match_dup 4) (const_int 0)))] @@ -12811,77 +12768,71 @@ "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] + (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64" "@ - {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 - {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 + {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 + {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (match_operand:SI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:SI 4 ""))] + (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "! TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") (define_insn "" - [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") + [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64" "@ - addic %4,%1,%k2\;addze. %0,%3 - subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 + addic %0,%1,%k2\;addze. %0,%3 + subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 # #" [(set_attr "type" "compare") (set_attr "length" "8,12,12,16")]) (define_split - [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:DI 2 "reg_or_short_operand" "")) (match_operand:DI 3 "gpc_reg_operand" "")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_scratch:DI 4 ""))] + (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) + [(set (match_dup 0) (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) - (clobber (match_dup 4))]) - (set (match_dup 5) + (set (match_dup 4) (compare:CC (match_dup 0) (const_int 0)))] "") diff --git a/contrib/gcc/config/rs6000/sysv4.h b/contrib/gcc/config/rs6000/sysv4.h index 9274d8f..635e926 100644 --- a/contrib/gcc/config/rs6000/sysv4.h +++ b/contrib/gcc/config/rs6000/sysv4.h @@ -770,6 +770,38 @@ do { \ ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ } while (0) +/* This is how to output code to push a register on the stack. + It need not be very fast code. + + On the rs6000, we must keep the backchain up to date. In order + to simplify things, always allocate 16 bytes for a push (System V + wants to keep stack aligned to a 16 byte boundary). */ + +#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ +do { \ + if (DEFAULT_ABI == ABI_V4) \ + asm_fprintf (FILE, \ + (TARGET_32BIT \ + ? "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n" \ + : "\tstdu %s,-32(%s)\n\tstd %s,24(%s)\n"), \ + reg_names[1], reg_names[1], reg_names[REGNO], \ + reg_names[1]); \ +} while (0) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE, REGNO) \ +do { \ + if (DEFAULT_ABI == ABI_V4) \ + asm_fprintf (FILE, \ + (TARGET_32BIT \ + ? "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n" \ + : "\tld %s,24(%s)\n\t{ai|addic} %s,%s,32\n"), \ + reg_names[REGNO], reg_names[1], reg_names[1], \ + reg_names[1]); \ +} while (0) + /* Switch Recognition by gcc.c. Add -G xx support. */ /* Override svr4.h definition. */ diff --git a/contrib/gcc/config/sparc/linux64.h b/contrib/gcc/config/sparc/linux64.h index 33c3f54..1dfd97f 100644 --- a/contrib/gcc/config/sparc/linux64.h +++ b/contrib/gcc/config/sparc/linux64.h @@ -58,7 +58,7 @@ Boston, MA 02111-1307, USA. */ #define STARTFILE_SPEC32 \ "%{!shared: \ - %{pg:/usr/lib/gcrt1.o%s} %{!pg:%{/usr/lib/p:gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\ + %{pg:/usr/lib/gcrt1.o%s} %{!pg:%{p:/usr/lib/gcrt1.o%s} %{!p:/usr/lib/crt1.o%s}}}\ /usr/lib/crti.o%s %{static:crtbeginT.o%s}\ %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" diff --git a/contrib/gcc/config/sparc/t-netbsd64 b/contrib/gcc/config/sparc/t-netbsd64 index 1292b86..0fddb0f 100644 --- a/contrib/gcc/config/sparc/t-netbsd64 +++ b/contrib/gcc/config/sparc/t-netbsd64 @@ -1,6 +1,8 @@ -MULTILIB_OPTIONS = m32/m64 -MULTILIB_DIRNAMES = 32 64 -MULTILIB_MATCHES = +# Disable multilib fow now, as NetBSD/sparc64 does not ship with +# a 32-bit environment. +#MULTILIB_OPTIONS = m32/m64 +#MULTILIB_DIRNAMES = 32 64 +#MULTILIB_MATCHES = -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib +#LIBGCC = stmp-multilib +#INSTALL_LIBGCC = install-multilib -- cgit v1.1