From cf46da7b9b56863c03d08e14aa2ed5a575cb0462 Mon Sep 17 00:00:00 2001
From: ian <ian@FreeBSD.org>
Date: Thu, 8 May 2014 18:36:42 +0000
Subject: Move the mptramp code which is specific to the Marvell ArmadaXP SoC
 out of the common locore.S file and into the mv/armadaxp directory.

---
 sys/arm/arm/locore.S               | 47 --------------------------------
 sys/arm/mv/armadaxp/files.armadaxp |  2 ++
 sys/arm/mv/armadaxp/mptramp.S      | 56 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 47 deletions(-)
 create mode 100644 sys/arm/mv/armadaxp/mptramp.S

diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 90eeeaf..c3207e8 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -349,52 +349,9 @@ pagetable:
 	.word	_C_LABEL(cpufuncs)
 
 #if defined(SMP)
-Lsramaddr:
-	.word	0xffff0080
-
-#if 0
-#define	AP_DEBUG(tmp)			\
-	mrc	p15, 0, r1, c0, c0, 5;	\
-	ldr	r0, Lsramaddr;		\
-	add	r0, r1, lsl #2;		\
-	mov	r1, tmp;		\
-	str	r1, [r0], #0x0000;
-#else
-#define AP_DEBUG(tmp)
-#endif
-
-
-ASENTRY_NP(mptramp)
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0
-
-	AP_DEBUG(#1)
-
-	mrs	r3, cpsr
-	bic	r3, r3, #(PSR_MODE)
-	orr	r3, r3, #(PSR_SVC32_MODE)
-        msr	cpsr_fsxc, r3
-
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, #0x0f		/* Get CPU ID */
-
-	/* Read boot address for CPU */
-	mov	r1, #0x100
-	mul	r2, r0, r1
-	ldr	r1, Lpmureg
-	add	r0, r2, r1
-	ldr	r1, [r0], #0x00
-
-	mov pc, r1
-
-Lpmureg:
-        .word   0xd0022124
-END(mptramp)
 
 ASENTRY_NP(mpentry)
 
-	AP_DEBUG(#2)
-
 	/* Make sure interrupts are disabled. */
 	mrs	r7, cpsr
 	orr	r7, r7, #(I32_bit|F32_bit)
@@ -417,8 +374,6 @@ ASENTRY_NP(mpentry)
 	nop
 	nop
 
-	AP_DEBUG(#3)
-
 Ltag:
 	ldr	r0, Lstartup_pagetable_secondary
 	bic	r0, r0, #0xf0000000
@@ -435,8 +390,6 @@ Ltag:
 	mcr	p15, 0, r0, c13, c0, 1	/* Set ASID to 0 */
 #endif
 
-	AP_DEBUG(#4)
-
 	/* Set the Domain Access register.  Very important! */
 	mov	r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
 	mcr	p15, 0, r0, c3, c0, 0
diff --git a/sys/arm/mv/armadaxp/files.armadaxp b/sys/arm/mv/armadaxp/files.armadaxp
index bd0316f..2ca0836 100644
--- a/sys/arm/mv/armadaxp/files.armadaxp
+++ b/sys/arm/mv/armadaxp/files.armadaxp
@@ -4,3 +4,5 @@ arm/mv/armadaxp/armadaxp.c	standard
 arm/mv/mpic.c			standard
 arm/mv/rtc.c			standard
 arm/mv/armadaxp/armadaxp_mp.c	optional smp
+arm/mv/armadaxp/mptramp.S	optional smp
+
diff --git a/sys/arm/mv/armadaxp/mptramp.S b/sys/arm/mv/armadaxp/mptramp.S
new file mode 100644
index 0000000..4d657e4
--- /dev/null
+++ b/sys/arm/mv/armadaxp/mptramp.S
@@ -0,0 +1,56 @@
+/*-
+ * Copyright 2011 Semihalf
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+#include <machine/armreg.h>
+
+__FBSDID("$FreeBSD$");
+
+ASENTRY_NP(mptramp)
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c7, 0
+
+	mrs	r3, cpsr
+	bic	r3, r3, #(PSR_MODE)
+	orr	r3, r3, #(PSR_SVC32_MODE)
+        msr	cpsr_fsxc, r3
+
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, #0x0f		/* Get CPU ID */
+
+	/* Read boot address for CPU */
+	mov	r1, #0x100
+	mul	r2, r0, r1
+	ldr	r1, Lpmureg
+	add	r0, r2, r1
+	ldr	r1, [r0], #0x00
+
+	mov pc, r1
+
+Lpmureg:
+        .word   0xd0022124
+END(mptramp)
+
-- 
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