From 86778ceeca8b8727f20ce00d041d4a15e0b6db4e Mon Sep 17 00:00:00 2001 From: imp Date: Thu, 12 Mar 2015 06:43:58 +0000 Subject: File names with commas in them cause issues for freebsd-update. We don't actually use these files at the moment, so eliminate them until we actually do. In the mean time, freebsd-update will be updated to eliminate the issues. Requested by: cperciva --- sys/gnu/dts/arm/alphascale-asm9260-devkit.dts | 13 - sys/gnu/dts/arm/alphascale-asm9260.dtsi | 63 -- sys/gnu/dts/arm/axm5516-amarillo.dts | 51 -- sys/gnu/dts/arm/axm55xx.dtsi | 204 ----- sys/gnu/dts/arm/exynos5250-snow.dts | 651 -------------- sys/gnu/dts/arm/exynos5420-peach-pit.dts | 968 --------------------- sys/gnu/dts/arm/exynos5800-peach-pi.dts | 957 -------------------- sys/gnu/dts/arm/mmp2-brownstone.dts | 196 ----- sys/gnu/dts/arm/mmp2.dtsi | 254 ------ sys/gnu/dts/arm/pxa168-aspenite.dts | 38 - sys/gnu/dts/arm/pxa168.dtsi | 158 ---- sys/gnu/dts/arm/pxa910-dkb.dts | 175 ---- sys/gnu/dts/arm/pxa910.dtsi | 175 ---- sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts | 59 -- sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts | 71 -- sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi | 1 - sys/gnu/dts/arm/qcom-apq8064.dtsi | 353 -------- sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts | 66 -- sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts | 23 - sys/gnu/dts/arm/qcom-apq8084-mtp.dts | 12 - sys/gnu/dts/arm/qcom-apq8084.dtsi | 230 ----- sys/gnu/dts/arm/qcom-ipq8064-ap148.dts | 93 -- sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi | 1 - sys/gnu/dts/arm/qcom-ipq8064.dtsi | 283 ------ sys/gnu/dts/arm/qcom-msm8660-surf.dts | 58 -- sys/gnu/dts/arm/qcom-msm8660.dtsi | 201 ----- sys/gnu/dts/arm/qcom-msm8960-cdp.dts | 43 - sys/gnu/dts/arm/qcom-msm8960.dtsi | 242 ------ .../dts/arm/qcom-msm8974-sony-xperia-honami.dts | 17 - sys/gnu/dts/arm/qcom-msm8974.dtsi | 251 ------ sys/gnu/dts/arm/s3c6400.dtsi | 41 - sys/gnu/dts/arm/s3c6410-mini6410.dts | 224 ----- sys/gnu/dts/arm/s3c6410-smdk6410.dts | 103 --- sys/gnu/dts/arm/s3c6410.dtsi | 57 -- sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi | 687 --------------- sys/gnu/dts/arm/s3c64xx.dtsi | 202 ----- sys/gnu/dts/arm/socfpga.dtsi | 782 ----------------- sys/gnu/dts/arm/socfpga_arria10.dtsi | 374 -------- sys/gnu/dts/arm/socfpga_arria10_socdk.dts | 48 - sys/gnu/dts/arm/socfpga_arria5.dtsi | 44 - sys/gnu/dts/arm/socfpga_arria5_socdk.dts | 85 -- sys/gnu/dts/arm/socfpga_cyclone5.dtsi | 55 -- sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts | 90 -- sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts | 70 -- sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts | 50 -- sys/gnu/dts/arm/socfpga_vt.dts | 90 -- .../include/dt-bindings/clock/alphascale,asm9260.h | 97 --- .../include/dt-bindings/clock/lsi,axm5516-clks.h | 36 - .../dts/include/dt-bindings/clock/marvell,mmp2.h | 74 -- .../dts/include/dt-bindings/clock/marvell,pxa168.h | 57 -- .../dts/include/dt-bindings/clock/marvell,pxa910.h | 54 -- .../dts/include/dt-bindings/clock/maxim,max77686.h | 23 - .../dts/include/dt-bindings/clock/maxim,max77802.h | 22 - .../include/dt-bindings/clock/qcom,gcc-apq8084.h | 351 -------- .../include/dt-bindings/clock/qcom,gcc-ipq806x.h | 292 ------- .../include/dt-bindings/clock/qcom,gcc-msm8660.h | 276 ------ .../include/dt-bindings/clock/qcom,gcc-msm8960.h | 323 ------- .../include/dt-bindings/clock/qcom,gcc-msm8974.h | 324 ------- .../include/dt-bindings/clock/qcom,lcc-ipq806x.h | 30 - .../include/dt-bindings/clock/qcom,lcc-msm8960.h | 50 -- .../include/dt-bindings/clock/qcom,mmcc-apq8084.h | 183 ---- .../include/dt-bindings/clock/qcom,mmcc-msm8960.h | 145 --- .../include/dt-bindings/clock/qcom,mmcc-msm8974.h | 161 ---- .../dts/include/dt-bindings/clock/rockchip,rk808.h | 11 - .../dt-bindings/clock/samsung,s3c64xx-clock.h | 178 ---- .../dts/include/dt-bindings/iio/qcom,spmi-vadc.h | 119 --- .../include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 142 --- .../include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 44 - .../include/dt-bindings/regulator/maxim,max77802.h | 18 - .../dts/include/dt-bindings/reset/altr,rst-mgr.h | 90 -- .../include/dt-bindings/reset/qcom,gcc-apq8084.h | 109 --- .../include/dt-bindings/reset/qcom,gcc-ipq806x.h | 132 --- .../include/dt-bindings/reset/qcom,gcc-msm8660.h | 134 --- .../include/dt-bindings/reset/qcom,gcc-msm8960.h | 134 --- .../include/dt-bindings/reset/qcom,gcc-msm8974.h | 96 -- .../include/dt-bindings/reset/qcom,mmcc-apq8084.h | 64 -- .../include/dt-bindings/reset/qcom,mmcc-msm8960.h | 101 --- .../include/dt-bindings/reset/qcom,mmcc-msm8974.h | 62 -- sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h | 26 - 79 files changed, 12867 deletions(-) delete mode 100644 sys/gnu/dts/arm/alphascale-asm9260-devkit.dts delete mode 100644 sys/gnu/dts/arm/alphascale-asm9260.dtsi delete mode 100644 sys/gnu/dts/arm/axm5516-amarillo.dts delete mode 100644 sys/gnu/dts/arm/axm55xx.dtsi delete mode 100644 sys/gnu/dts/arm/exynos5250-snow.dts delete mode 100644 sys/gnu/dts/arm/exynos5420-peach-pit.dts delete mode 100644 sys/gnu/dts/arm/exynos5800-peach-pi.dts delete mode 100644 sys/gnu/dts/arm/mmp2-brownstone.dts delete mode 100644 sys/gnu/dts/arm/mmp2.dtsi delete mode 100644 sys/gnu/dts/arm/pxa168-aspenite.dts delete mode 100644 sys/gnu/dts/arm/pxa168.dtsi delete mode 100644 sys/gnu/dts/arm/pxa910-dkb.dts delete mode 100644 sys/gnu/dts/arm/pxa910.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts delete mode 100644 sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts delete mode 100644 sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-apq8064.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts delete mode 100644 sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts delete mode 100644 sys/gnu/dts/arm/qcom-apq8084-mtp.dts delete mode 100644 sys/gnu/dts/arm/qcom-apq8084.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-ipq8064-ap148.dts delete mode 100644 sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-ipq8064.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-msm8660-surf.dts delete mode 100644 sys/gnu/dts/arm/qcom-msm8660.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-msm8960-cdp.dts delete mode 100644 sys/gnu/dts/arm/qcom-msm8960.dtsi delete mode 100644 sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts delete mode 100644 sys/gnu/dts/arm/qcom-msm8974.dtsi delete mode 100644 sys/gnu/dts/arm/s3c6400.dtsi delete mode 100644 sys/gnu/dts/arm/s3c6410-mini6410.dts delete mode 100644 sys/gnu/dts/arm/s3c6410-smdk6410.dts delete mode 100644 sys/gnu/dts/arm/s3c6410.dtsi delete mode 100644 sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi delete mode 100644 sys/gnu/dts/arm/s3c64xx.dtsi delete mode 100644 sys/gnu/dts/arm/socfpga.dtsi delete mode 100644 sys/gnu/dts/arm/socfpga_arria10.dtsi delete mode 100755 sys/gnu/dts/arm/socfpga_arria10_socdk.dts delete mode 100644 sys/gnu/dts/arm/socfpga_arria5.dtsi delete mode 100644 sys/gnu/dts/arm/socfpga_arria5_socdk.dts delete mode 100644 sys/gnu/dts/arm/socfpga_cyclone5.dtsi delete mode 100644 sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts delete mode 100644 sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts delete mode 100644 sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts delete mode 100644 sys/gnu/dts/arm/socfpga_vt.dts delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h delete mode 100644 sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h delete mode 100644 sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h delete mode 100644 sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h delete mode 100644 sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h delete mode 100644 sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h delete mode 100644 sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h delete mode 100644 sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h diff --git a/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts b/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts deleted file mode 100644 index c77e2c9..0000000 --- a/sys/gnu/dts/arm/alphascale-asm9260-devkit.dts +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -/dts-v1/; -#include "alphascale-asm9260.dtsi" - -/ { - model = "Alphascale asm9260 Development Kit"; - compatible = "alphascale,asm9260devkit", "alphascale,asm9260"; -}; diff --git a/sys/gnu/dts/arm/alphascale-asm9260.dtsi b/sys/gnu/dts/arm/alphascale-asm9260.dtsi deleted file mode 100644 index 907fc7b..0000000 --- a/sys/gnu/dts/arm/alphascale-asm9260.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * Licensed under the X11 license or the GPL v2 (or later) - */ - -#include "skeleton.dtsi" -#include - -/ { - interrupt-parent = <&icoll>; - - memory { - device_type = "memory"; - reg = <0x20000000 0x2000000>; - }; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - compatible = "arm,arm926ej-s"; - device_type = "cpu"; - clocks = <&acc CLKID_SYS_CPU>; - }; - }; - - osc24m: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-accuracy = <30000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - acc: clock-controller@80040000 { - compatible = "alphascale,asm9260-clock-controller"; - #clock-cells = <1>; - clocks = <&osc24m>; - reg = <0x80040000 0x204>; - }; - - icoll: interrupt-controller@80054000 { - compatible = "alphascale,asm9260-icoll"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x80054000 0x200>; - }; - - timer0: timer@80088000 { - compatible = "alphascale,asm9260-timer"; - reg = <0x80088000 0x4000>; - clocks = <&acc CLKID_AHB_TIMER0>; - interrupts = <29>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/axm5516-amarillo.dts b/sys/gnu/dts/arm/axm5516-amarillo.dts deleted file mode 100644 index a9d6047..0000000 --- a/sys/gnu/dts/arm/axm5516-amarillo.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* - * arch/arm/boot/dts/axm5516-amarillo.dts - * - * Copyright (C) 2013 LSI - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -/dts-v1/; - -/memreserve/ 0x00000000 0x00400000; - -#include "axm55xx.dtsi" -#include "axm5516-cpus.dtsi" - -/ { - model = "Amarillo AXM5516"; - compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; - - memory { - device_type = "memory"; - reg = <0 0x00000000 0x02 0x00000000>; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/axm55xx.dtsi b/sys/gnu/dts/arm/axm55xx.dtsi deleted file mode 100644 index ea288f0a..0000000 --- a/sys/gnu/dts/arm/axm55xx.dtsi +++ /dev/null @@ -1,204 +0,0 @@ -/* - * arch/arm/boot/dts/axm55xx.dtsi - * - * Copyright (C) 2013 LSI - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include - -#include "skeleton64.dtsi" - -/ { - interrupt-parent = <&gic>; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - timer = &timer0; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clk_ref0: clk_ref0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref1: clk_ref1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clk_ref2: clk_ref2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - clks: clock-controller@2010020000 { - compatible = "lsi,axm5516-clks"; - #clock-cells = <1>; - reg = <0x20 0x10020000 0 0x20000>; - }; - }; - - gic: interrupt-controller@2001001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x20 0x01001000 0 0x1000>, - <0x20 0x01002000 0 0x1000>, - <0x20 0x01004000 0 0x2000>, - <0x20 0x01006000 0 0x2000>; - interrupts = ; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - , - , - , - ; - }; - - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = ; - }; - - soc { - compatible = "simple-bus"; - device_type = "soc"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - ranges; - - syscon: syscon@2010030000 { - compatible = "lsi,axxia-syscon", "syscon"; - reg = <0x20 0x10030000 0 0x2000>; - }; - - reset: reset@2010031000 { - compatible = "lsi,axm55xx-reset"; - syscon = <&syscon>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - serial0: uart@2010080000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10080000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial1: uart@2010081000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10081000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial2: uart@2010082000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10082000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - serial3: uart@2010083000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x20 0x10083000 0 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - timer0: timer@2010091000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x20 0x10091000 0 0x1000>; - interrupts = , - , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "okay"; - }; - - gpio0: gpio@2010092000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10092000 0x00 0x1000>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - gpio1: gpio@2010093000 { - #gpio-cells = <2>; - compatible = "arm,pl061", "arm,primecell"; - gpio-controller; - reg = <0x20 0x10093000 0x00 0x1000>; - interrupts = ; - clocks = <&clks AXXIA_CLK_PER>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - }; - }; -}; - -/* - Local Variables: - mode: C - End: -*/ diff --git a/sys/gnu/dts/arm/exynos5250-snow.dts b/sys/gnu/dts/arm/exynos5250-snow.dts deleted file mode 100644 index b9aeec4..0000000 --- a/sys/gnu/dts/arm/exynos5250-snow.dts +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Google Snow board device tree source - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include -#include "exynos5250.dtsi" - -/ { - model = "Google Snow"; - compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5"; - - aliases { - i2c104 = &i2c_104; - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - chosen { - bootargs = "console=tty1"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; - linux,code = ; - gpio-key,wakeup; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - }; - - vbat: vbat-fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - }; - - i2c-arbitrator { - compatible = "i2c-arb-gpio-challenge"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@12CA0000}>; - - our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; - their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; - slew-delay-us = <10>; - wait-retry-us = <3000>; - wait-free-us = <50000>; - - pinctrl-names = "default"; - pinctrl-0 = <&arb_our_claim &arb_their_claim>; - - /* Use ID 104 as a hint that we're on physical bus 4 */ - i2c_104: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - }; - - cros_ec: embedded-controller { - compatible = "google,cros-ec-i2c"; - reg = <0x1e>; - interrupts = <6 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_irq>; - wakeup-source; - }; - - power-regulator { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - dcdc1 { - ti,enable-ext-control; - }; - dcdc2 { - ti,enable-ext-control; - }; - dcdc3 { - ti,enable-ext-control; - }; - fet1: fet1 { - regulator-name = "vcd_led"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet4 { - regulator-name = "sdcard"; - ti,overcurrent-wait = <3>; - }; - fet5 { - regulator-name = "camout"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - fet6: fet6 { - regulator-name = "lcd_vdd"; - ti,overcurrent-wait = <3>; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - ti,overcurrent-wait = <3>; - }; - ldo1 { - }; - ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; - - i2c@12CD0000 { - ptn3460: lvds-bridge@20 { - compatible = "nxp,ptn3460"; - reg = <0x20>; - powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; - edid-emulation = <5>; - panel = <&panel>; - }; - }; - - sound { - compatible = "google,snow-audio-max98095"; - - samsung,model = "Snow-I2S-MAX98095"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98095>; - }; - - usb3_vbus_reg: regulator-usb3 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_en>; - enable-active-high; - }; - - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; - power-supply = <&fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&fet6>; - backlight = <&backlight>; - }; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; - bridge = <&ptn3460>; -}; - -&ehci { - samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&i2c_0 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - max77686: max77686@09 { - compatible = "maxim,max77686"; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77686_irq>; - wakeup-source; - reg = <0x09>; - #clock-cells = <1>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.8V_LDO_OUT2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - buck6_reg: BUCK6 { - regulator-name = "P1.35V_BUCK_OUT6"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - buck7_reg: BUCK7 { - regulator-name = "P2.0V_BUCK_OUT7"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - }; - - buck8_reg: BUCK8 { - regulator-name = "P2.85V_BUCK_OUT8"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - }; - }; -}; - -&i2c_1 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - trackpad { - reg = <0x67>; - compatible = "cypress,cyapa"; - interrupts = <2 IRQ_TYPE_NONE>; - interrupt-parent = <&gpx1>; - wakeup-source; - }; -}; - -/* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ -&i2c2_bus { - samsung,pin-pud = <0>; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; -}; - -&i2c_3 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_4 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_5 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; -}; - -&i2c_7 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-0 = <&max98095_en>; - pinctrl-names = "default"; - }; -}; - -&i2c_8 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; - cap-mmc-highspeed; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; - wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; - cap-sd-highspeed; -}; - -/* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ -&mmc_3 { - status = "okay"; - num-slots = <1>; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - bus-width = <4>; - cap-sd-highspeed; -}; - -&pinctrl_0 { - power_key_irq: power-key-irq { - samsung,pins = "gpx1-3"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - max98095_en: max98095-en { - samsung,pins = "gpx1-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb3_vbus_en: usb3-vbus-en { - samsung,pins = "gpx2-7"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - max77686_irq: max77686-irq { - samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-5"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_1 { - arb_their_claim: arb-their-claim { - samsung,pins = "gpe0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - arb_our_claim: arb-our-claim { - samsung,pins = "gpf0-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&sd3_bus4 { - samsung,pin-drv = <0>; -}; - -&sd3_clk { - samsung,pin-drv = <0>; -}; - -&sd3_cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; -}; - -&spi_1 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; -}; - -&usbdrd_dwc3 { - dr_mode = "host"; -}; - -&usbdrd_phy { - vbus-supply = <&usb3_vbus_reg>; -}; - -#include "cros-ec-keyboard.dtsi" diff --git a/sys/gnu/dts/arm/exynos5420-peach-pit.dts b/sys/gnu/dts/arm/exynos5420-peach-pit.dts deleted file mode 100644 index c47bb70..0000000 --- a/sys/gnu/dts/arm/exynos5420-peach-pit.dts +++ /dev/null @@ -1,968 +0,0 @@ -/* - * Google Peach Pit Rev 6+ board device tree source - * - * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5420.dtsi" - -/ { - model = "Google Peach Pit Rev 6+"; - - compatible = "google,pit-rev16", - "google,pit-rev15", "google,pit-rev14", - "google,pit-rev13", "google,pit-rev12", - "google,pit-rev11", "google,pit-rev10", - "google,pit-rev9", "google,pit-rev8", - "google,pit-rev7", "google,pit-rev6", - "google,pit", "google,peach","samsung,exynos5420", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - gpio-key,wakeup; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - }; - - memory { - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98090"; - - samsung,model = "Peach-Pit-I2S-MAX98090"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98090>; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b116xw03"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x06>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 0>; - bridge = <&ps8625>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98090: codec@10 { - compatible = "maxim,max98090"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98090_irq>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; - - ps8625: lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; - lane-count = <2>; - panel = <&panel>; - use-external-pwm; - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - - /* Atmel mXT336S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - max98090_irq: max98090-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = <2>; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 0>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&uart_3 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/sys/gnu/dts/arm/exynos5800-peach-pi.dts b/sys/gnu/dts/arm/exynos5800-peach-pi.dts deleted file mode 100644 index 06737c6..0000000 --- a/sys/gnu/dts/arm/exynos5800-peach-pi.dts +++ /dev/null @@ -1,957 +0,0 @@ -/* - * Google Peach Pi Rev 10+ board device tree source - * - * Copyright (c) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -/dts-v1/; -#include -#include -#include -#include -#include -#include "exynos5800.dtsi" - -/ { - model = "Google Peach Pi Rev 10+"; - - compatible = "google,pi-rev16", - "google,pi-rev15", "google,pi-rev14", - "google,pi-rev13", "google,pi-rev12", - "google,pi-rev11", "google,pi-rev10", - "google,pi", "google,peach", "samsung,exynos5800", - "samsung,exynos5"; - - aliases { - /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 1000000 0>; - brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; - default-brightness-level = <7>; - enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - power-supply = <&tps65090_fet1>; - pinctrl-0 = <&pwm0_out>; - pinctrl-names = "default"; - }; - - fixed-rate-clocks { - oscclk { - compatible = "samsung,exynos5420-oscclk"; - clock-frequency = <24000000>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&power_key_irq &lid_irq>; - - power { - label = "Power"; - gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; - linux,code = ; - gpio-key,wakeup; - }; - - lid-switch { - label = "Lid"; - gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; - linux,input-type = <5>; /* EV_SW */ - linux,code = <0>; /* SW_LID */ - debounce-interval = <1>; - gpio-key,wakeup; - }; - - }; - - memory { - reg = <0x20000000 0x80000000>; - }; - - sound { - compatible = "google,snow-audio-max98091"; - - samsung,model = "Peach-Pi-I2S-MAX98091"; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&max98091>; - }; - - usb300_vbus_reg: regulator-usb300 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb300_vbus_en>; - enable-active-high; - }; - - usb301_vbus_reg: regulator-usb301 { - compatible = "regulator-fixed"; - regulator-name = "P5.0V_USB3CON1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gph0 1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb301_vbus_en>; - enable-active-high; - }; - - vbat: fixed-regulator { - compatible = "regulator-fixed"; - regulator-name = "vbat-supply"; - regulator-boot-on; - regulator-always-on; - }; - - panel: panel { - compatible = "auo,b133htn01"; - power-supply = <&tps65090_fet6>; - backlight = <&backlight>; - }; -}; - -&adc { - status = "okay"; - vdd-supply = <&ldo9_reg>; -}; - -&dp { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd_gpio>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 0>; - panel = <&panel>; -}; - -&fimd { - status = "okay"; - samsung,invert-vclk; -}; - -&hdmi { - status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - ddc = <&i2c_2>; - - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; -}; - -&hsi2c_4 { - status = "okay"; - clock-frequency = <400000>; - - max77802: max77802-pmic@9 { - compatible = "maxim,max77802"; - interrupt-parent = <&gpx3>; - interrupts = <1 IRQ_TYPE_NONE>; - pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; - wakeup-source; - reg = <0x9>; - #clock-cells = <1>; - - inb1-supply = <&tps65090_dcdc2>; - inb2-supply = <&tps65090_dcdc1>; - inb3-supply = <&tps65090_dcdc2>; - inb4-supply = <&tps65090_dcdc2>; - inb5-supply = <&tps65090_dcdc1>; - inb6-supply = <&tps65090_dcdc2>; - inb7-supply = <&tps65090_dcdc1>; - inb8-supply = <&tps65090_dcdc1>; - inb9-supply = <&tps65090_dcdc1>; - inb10-supply = <&tps65090_dcdc1>; - - inl1-supply = <&buck5_reg>; - inl2-supply = <&buck7_reg>; - inl3-supply = <&buck9_reg>; - inl4-supply = <&buck9_reg>; - inl5-supply = <&buck9_reg>; - inl6-supply = <&tps65090_dcdc2>; - inl7-supply = <&buck9_reg>; - inl9-supply = <&tps65090_dcdc2>; - inl10-supply = <&buck7_reg>; - - regulators { - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck5_reg: BUCK5 { - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck6_reg: BUCK6 { - regulator-name = "vdd_kfc"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - regulator-boot-on; - regulator-ramp-delay = <12500>; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck7_reg: BUCK7 { - regulator-name = "vdd_1v35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck8_reg: BUCK8 { - regulator-name = "vdd_emmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - buck9_reg: BUCK9 { - regulator-name = "vdd_2v"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - buck10_reg: BUCK10 { - regulator-name = "vdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - ldo1_reg: LDO1 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo2_reg: LDO2 { - regulator-name = "vdd_1v2_2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo3_reg: LDO3 { - regulator-name = "vdd_1v8_3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - vqmmc_sdcard: ldo4_reg: LDO4 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo5_reg: LDO5 { - regulator-name = "vdd_1v8_5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo6_reg: LDO6 { - regulator-name = "vdd_1v8_6"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo7_reg: LDO7 { - regulator-name = "vdd_1v8_7"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo8_reg: LDO8 { - regulator-name = "vdd_ldo8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo9_reg: LDO9 { - regulator-name = "vdd_ldo9"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo10_reg: LDO10 { - regulator-name = "vdd_ldo10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo11_reg: LDO11 { - regulator-name = "vdd_ldo11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo12_reg: LDO12 { - regulator-name = "vdd_ldo12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-on-in-suspend; - regulator-mode = ; - }; - }; - - ldo14_reg: LDO14 { - regulator-name = "vdd_ldo14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo15_reg: LDO15 { - regulator-name = "vdd_ldo15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo17_reg: LDO17 { - regulator-name = "vdd_g3ds"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo18_reg: LDO18 { - regulator-name = "ldo_18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo19_reg: LDO19 { - regulator-name = "ldo_19"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo20_reg: LDO20 { - regulator-name = "ldo_20"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo21_reg: LDO21 { - regulator-name = "ldo_21"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo23_reg: LDO23 { - regulator-name = "ldo_23"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - ldo24_reg: LDO24 { - regulator-name = "ldo_24"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo25_reg: LDO25 { - regulator-name = "ldo_25"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo26_reg: LDO26 { - regulator-name = "ldo_26"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo27_reg: LDO27 { - regulator-name = "ldo_27"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - ldo28_reg: LDO28 { - regulator-name = "ldo_28"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo29_reg: LDO29 { - regulator-name = "ldo_29"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo30_reg: LDO30 { - regulator-name = "vdd_mifs"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - ldo32_reg: LDO32 { - regulator-name = "ldo_32"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo33_reg: LDO33 { - regulator-name = "ldo_33"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo34_reg: LDO34 { - regulator-name = "ldo_34"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo35_reg: LDO35 { - regulator-name = "ldo_35"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - }; -}; - -&hsi2c_7 { - status = "okay"; - clock-frequency = <400000>; - - max98091: codec@10 { - compatible = "maxim,max98091"; - reg = <0x10>; - interrupts = <2 0>; - interrupt-parent = <&gpx0>; - pinctrl-names = "default"; - pinctrl-0 = <&max98091_irq>; - }; - - light-sensor@44 { - compatible = "isil,isl29018"; - reg = <0x44>; - vcc-supply = <&tps65090_fet5>; - }; -}; - -&hsi2c_8 { - status = "okay"; - clock-frequency = <333000>; - /* Atmel mXT540S */ - trackpad@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpx1>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - pinctrl-names = "default"; - pinctrl-0 = <&trackpad_irq>; - linux,gpio-keymap = ; /* GPIO 3 */ - }; -}; - -&hsi2c_9 { - status = "okay"; - clock-frequency = <400000>; - - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - - /* Unused irq; but still need to configure the pins */ - pinctrl-names = "default"; - pinctrl-0 = <&tpm_irq>; - }; -}; - -&i2c_2 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; -}; - -&i2s0 { - status = "okay"; -}; - -&mmc_0 { - status = "okay"; - num-slots = <1>; - broken-cd; - mmc-hs200-1_8v; - cap-mmc-highspeed; - non-removable; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <0 4>; - samsung,dw-mshc-ddr-timing = <0 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - bus-width = <8>; -}; - -&mmc_2 { - status = "okay"; - num-slots = <1>; - cap-sd-highspeed; - card-detect-delay = <200>; - clock-frequency = <400000000>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - bus-width = <4>; -}; - - -&pinctrl_0 { - pinctrl-names = "default"; - pinctrl-0 = <&mask_tpm_reset>; - - max98091_irq: max98091-irq { - samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { - samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - samsung,pin-val = <0>; - }; - - tpm_irq: tpm-irq { - samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - trackpad_irq: trackpad-irq { - samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - power_key_irq: power-key-irq { - samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - ec_irq: ec-irq { - samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - dp_hpd_gpio: dp_hpd_gpio { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - max77802_irq: max77802-irq { - samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - lid_irq: lid-irq { - samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - - pmic_dvs_1: pmic-dvs-1 { - samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = <2>; - }; - - /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { - samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; - }; - - usb300_vbus_en: usb300-vbus-en { - samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb301_vbus_en: usb301-vbus-en { - samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - pmic_selb: pmic-selb { - samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", - "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; -}; - -&rtc { - status = "okay"; - clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; - clock-names = "rtc", "rtc_src"; -}; - -&spi_2 { - status = "okay"; - num-cs = <1>; - samsung,spi-src-clk = <0>; - cs-gpios = <&gpb1 2 0>; - - cros_ec: cros-ec@0 { - compatible = "google,cros-ec-spi"; - interrupt-parent = <&gpx1>; - interrupts = <5 0>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_spi_cs &ec_irq>; - reg = <0>; - spi-max-frequency = <3125000>; - - controller-data { - samsung,spi-feedback-delay = <1>; - }; - - i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - #address-cells = <1>; - #size-cells = <0>; - google,remote-bus = <0>; - - battery: sbs-battery@b { - compatible = "sbs,sbs-battery"; - reg = <0xb>; - sbs,poll-retry-count = <1>; - sbs,i2c-retry-count = <2>; - }; - - power-regulator@48 { - compatible = "ti,tps65090"; - reg = <0x48>; - - /* - * Config irq to disable internal pulls - * even though we run in polling mode. - */ - pinctrl-names = "default"; - pinctrl-0 = <&tps65090_irq>; - - vsys1-supply = <&vbat>; - vsys2-supply = <&vbat>; - vsys3-supply = <&vbat>; - infet1-supply = <&vbat>; - infet2-supply = <&tps65090_dcdc1>; - infet3-supply = <&tps65090_dcdc2>; - infet4-supply = <&tps65090_dcdc2>; - infet5-supply = <&tps65090_dcdc2>; - infet6-supply = <&tps65090_dcdc2>; - infet7-supply = <&tps65090_dcdc1>; - vsys-l1-supply = <&vbat>; - vsys-l2-supply = <&vbat>; - - regulators { - tps65090_dcdc1: dcdc1 { - ti,enable-ext-control; - }; - tps65090_dcdc2: dcdc2 { - ti,enable-ext-control; - }; - tps65090_dcdc3: dcdc3 { - ti,enable-ext-control; - }; - tps65090_fet1: fet1 { - regulator-name = "vcd_led"; - }; - tps65090_fet2: fet2 { - regulator-name = "video_mid"; - regulator-always-on; - }; - tps65090_fet3: fet3 { - regulator-name = "wwan_r"; - regulator-always-on; - }; - tps65090_fet4: fet4 { - regulator-name = "sdcard"; - regulator-always-on; - }; - tps65090_fet5: fet5 { - regulator-name = "camout"; - regulator-always-on; - }; - tps65090_fet6: fet6 { - regulator-name = "lcd_vdd"; - }; - tps65090_fet7: fet7 { - regulator-name = "video_mid_1a"; - regulator-always-on; - }; - tps65090_ldo1: ldo1 { - }; - tps65090_ldo2: ldo2 { - }; - }; - - charger { - compatible = "ti,tps65090-charger"; - }; - }; - }; - }; -}; - -&uart_3 { - status = "okay"; -}; - -&usbdrd_dwc3_0 { - dr_mode = "host"; -}; - -&usbdrd_dwc3_1 { - dr_mode = "host"; -}; - -&usbdrd_phy0 { - vbus-supply = <&usb300_vbus_reg>; -}; - -&usbdrd_phy1 { - vbus-supply = <&usb301_vbus_reg>; -}; - -/* - * Use longest HW watchdog in SoC (32 seconds) since the hardware - * watchdog provides no debugging information (compared to soft/hard - * lockup detectors) and so should be last resort. - */ -&watchdog { - timeout-sec = <32>; -}; - -#include "cros-ec-keyboard.dtsi" -#include "cros-adc-thermistors.dtsi" diff --git a/sys/gnu/dts/arm/mmp2-brownstone.dts b/sys/gnu/dts/arm/mmp2-brownstone.dts deleted file mode 100644 index 350208c..0000000 --- a/sys/gnu/dts/arm/mmp2-brownstone.dts +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "mmp2.dtsi" - -/ { - model = "Marvell MMP2 Brownstone Development Board"; - compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2"; - - chosen { - bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x08000000>; - }; - - soc { - apb@d4000000 { - uart3: uart@d4018000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - pmic: max8925@3c { - compatible = "maxium,max8925"; - reg = <0x3c>; - interrupts = <1>; - interrupt-parent = <&intcmux4>; - interrupt-controller; - #interrupt-cells = <1>; - maxim,tsc-irq = <0>; - - regulators { - SDV1 { - regulator-min-microvolt = <637500>; - regulator-max-microvolt = <1425000>; - regulator-boot-on; - regulator-always-on; - }; - SDV2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2225000>; - regulator-boot-on; - regulator-always-on; - }; - SDV3 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - }; - LDO11 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO15 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO16 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO17 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO18 { - regulator-min-microvolt = <650000>; - regulator-max-microvolt = <2250000>; - regulator-boot-on; - regulator-always-on; - }; - LDO19 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO20 { - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3900000>; - regulator-boot-on; - regulator-always-on; - }; - }; - backlight { - maxim,max8925-dual-string = <0>; - }; - charger { - batt-detect = <0>; - topoff-threshold = <1>; - fast-charge = <7>; - no-temp-support = <0>; - no-insert-detect = <0>; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/mmp2.dtsi b/sys/gnu/dts/arm/mmp2.dtsi deleted file mode 100644 index 766bbb8..0000000 --- a/sys/gnu/dts/arm/mmp2.dtsi +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp2-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - intcmux4: interrupt-controller@d4282150 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <4>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x150 0x4>, <0x168 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux5: interrupt-controller@d4282154 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <5>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x154 0x4>, <0x16c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - mrvl,clr-mfp-irq = <1>; - }; - - intcmux9: interrupt-controller@d4282180 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <9>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x180 0x4>, <0x17c 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <3>; - }; - - intcmux17: interrupt-controller@d4282158 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <17>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x158 0x4>, <0x170 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <5>; - }; - - intcmux35: interrupt-controller@d428215c { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <35>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x15c 0x4>, <0x174 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <15>; - }; - - intcmux51: interrupt-controller@d4282160 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <51>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x160 0x4>, <0x178 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - - intcmux55: interrupt-controller@d4282188 { - compatible = "mrvl,mmp2-mux-intc"; - interrupts = <55>; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x188 0x4>, <0x184 0x4>; - reg-names = "mux status", "mux mask"; - mrvl,intc-nr-irqs = <2>; - }; - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - uart1: uart@d4030000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4030000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks MMP2_CLK_UART0>; - resets = <&soc_clocks MMP2_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks MMP2_CLK_UART1>; - resets = <&soc_clocks MMP2_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <24>; - clocks = <&soc_clocks MMP2_CLK_UART2>; - resets = <&soc_clocks MMP2_CLK_UART2>; - status = "disabled"; - }; - - uart4: uart@d4016000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4016000 0x1000>; - interrupts = <46>; - clocks = <&soc_clocks MMP2_CLK_UART3>; - resets = <&soc_clocks MMP2_CLK_UART3>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp2-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks MMP2_CLK_GPIO>; - resets = <&soc_clocks MMP2_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - - gcb4: gpio@d4019104 { - reg = <0xd4019104 0x4>; - }; - - gcb5: gpio@d4019108 { - reg = <0xd4019108 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks MMP2_CLK_TWSI0>; - resets = <&soc_clocks MMP2_CLK_TWSI0>; - #address-cells = <1>; - #size-cells = <0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks MMP2_CLK_TWSI1>; - resets = <&soc_clocks MMP2_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <1 0>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - interrupt-parent = <&intcmux5>; - clocks = <&soc_clocks MMP2_CLK_RTC>; - resets = <&soc_clocks MMP2_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,mmp2-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa168-aspenite.dts b/sys/gnu/dts/arm/pxa168-aspenite.dts deleted file mode 100644 index 0a988b3..0000000 --- a/sys/gnu/dts/arm/pxa168-aspenite.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "pxa168.dtsi" - -/ { - model = "Marvell PXA168 Aspenite Development Board"; - compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x04000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa168.dtsi b/sys/gnu/dts/arm/pxa168.dtsi deleted file mode 100644 index b899e25..0000000 --- a/sys/gnu/dts/arm/pxa168.dtsi +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA168_CLK_UART0>; - resets = <&soc_clocks PXA168_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA168_CLK_UART1>; - resets = <&soc_clocks PXA168_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4026000 0x1000>; - interrupts = <29>; - clocks = <&soc_clocks PXA168_CLK_UART2>; - resets = <&soc_clocks PXA168_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - clocks = <&soc_clocks PXA168_CLK_GPIO>; - resets = <&soc_clocks PXA168_CLK_GPIO>; - interrupt-names = "gpio_mux"; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA168_CLK_TWSI0>; - resets = <&soc_clocks PXA168_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi"; - reg = <0xd4025000 0x1000>; - interrupts = <58>; - clocks = <&soc_clocks PXA168_CLK_TWSI1>; - resets = <&soc_clocks PXA168_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA168_CLK_RTC>; - resets = <&soc_clocks PXA168_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa168-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>; - reg-names = "mpmu", "apmu", "apbc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa910-dkb.dts b/sys/gnu/dts/arm/pxa910-dkb.dts deleted file mode 100644 index c82f281..0000000 --- a/sys/gnu/dts/arm/pxa910-dkb.dts +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -/dts-v1/; -#include "pxa910.dtsi" - -/ { - model = "Marvell PXA910 DKB Development Board"; - compatible = "mrvl,pxa910-dkb", "mrvl,pxa910"; - - chosen { - bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on"; - }; - - memory { - reg = <0x00000000 0x10000000>; - }; - - soc { - apb@d4000000 { - uart1: uart@d4017000 { - status = "okay"; - }; - twsi1: i2c@d4011000 { - status = "okay"; - - pmic: 88pm860x@34 { - compatible = "marvell,88pm860x"; - reg = <0x34>; - interrupts = <4>; - interrupt-parent = <&intc>; - interrupt-controller; - #interrupt-cells = <1>; - - marvell,88pm860x-irq-read-clr; - marvell,88pm860x-slave-addr = <0x11>; - - regulators { - BUCK1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - BUCK3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; - }; - LDO2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO5 { - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-boot-on; - regulator-always-on; - }; - LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO10 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - LDO12 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO13 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - LDO14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - rtc { - marvell,88pm860x-vrtc = <1>; - }; - touch { - marvell,88pm860x-gpadc-prebias = <1>; - marvell,88pm860x-gpadc-slot-cycle = <1>; - marvell,88pm860x-tsi-prebias = <6>; - marvell,88pm860x-pen-prebias = <16>; - marvell,88pm860x-pen-prechg = <2>; - marvell,88pm860x-resistor-X = <300>; - }; - backlights { - backlight-0 { - marvell,88pm860x-iset = <4>; - marvell,88pm860x-pwm = <3>; - }; - backlight-2 { - }; - }; - leds { - led0-red { - marvell,88pm860x-iset = <12>; - }; - led0-green { - marvell,88pm860x-iset = <12>; - }; - led0-blue { - marvell,88pm860x-iset = <12>; - }; - }; - }; - }; - rtc: rtc@d4010000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/pxa910.dtsi b/sys/gnu/dts/arm/pxa910.dtsi deleted file mode 100644 index 0868f67..0000000 --- a/sys/gnu/dts/arm/pxa910.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (C) 2012 Marvell Technology Group Ltd. - * Author: Haojian Zhuang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * publishhed by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - i2c0 = &twsi1; - i2c1 = &twsi2; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - L2: l2-cache { - compatible = "marvell,tauros2-cache"; - marvell,tauros2-cache-features = <0x3>; - }; - - axi@d4200000 { /* AXI */ - compatible = "mrvl,axi-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4200000 0x00200000>; - ranges; - - intc: interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - mrvl,intc-nr-irqs = <64>; - }; - - }; - - apb@d4000000 { /* APB */ - compatible = "mrvl,apb-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4000000 0x00200000>; - ranges; - - timer0: timer@d4014000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4014000 0x100>; - interrupts = <13>; - }; - - timer1: timer@d4016000 { - compatible = "mrvl,mmp-timer"; - reg = <0xd4016000 0x100>; - interrupts = <29>; - status = "disabled"; - }; - - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4017000 0x1000>; - interrupts = <27>; - clocks = <&soc_clocks PXA910_CLK_UART0>; - resets = <&soc_clocks PXA910_CLK_UART0>; - status = "disabled"; - }; - - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4018000 0x1000>; - interrupts = <28>; - clocks = <&soc_clocks PXA910_CLK_UART1>; - resets = <&soc_clocks PXA910_CLK_UART1>; - status = "disabled"; - }; - - uart3: uart@d4036000 { - compatible = "mrvl,mmp-uart"; - reg = <0xd4036000 0x1000>; - interrupts = <59>; - clocks = <&soc_clocks PXA910_CLK_UART2>; - resets = <&soc_clocks PXA910_CLK_UART2>; - status = "disabled"; - }; - - gpio@d4019000 { - compatible = "marvell,mmp-gpio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xd4019000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <49>; - interrupt-names = "gpio_mux"; - clocks = <&soc_clocks PXA910_CLK_GPIO>; - resets = <&soc_clocks PXA910_CLK_GPIO>; - interrupt-controller; - #interrupt-cells = <1>; - ranges; - - gcb0: gpio@d4019000 { - reg = <0xd4019000 0x4>; - }; - - gcb1: gpio@d4019004 { - reg = <0xd4019004 0x4>; - }; - - gcb2: gpio@d4019008 { - reg = <0xd4019008 0x4>; - }; - - gcb3: gpio@d4019100 { - reg = <0xd4019100 0x4>; - }; - }; - - twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4011000 0x1000>; - interrupts = <7>; - clocks = <&soc_clocks PXA910_CLK_TWSI0>; - resets = <&soc_clocks PXA910_CLK_TWSI0>; - mrvl,i2c-fast-mode; - status = "disabled"; - }; - - twsi2: i2c@d4037000 { - compatible = "mrvl,mmp-twsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xd4037000 0x1000>; - interrupts = <54>; - clocks = <&soc_clocks PXA910_CLK_TWSI1>; - resets = <&soc_clocks PXA910_CLK_TWSI1>; - status = "disabled"; - }; - - rtc: rtc@d4010000 { - compatible = "mrvl,mmp-rtc"; - reg = <0xd4010000 0x1000>; - interrupts = <5 6>; - interrupt-names = "rtc 1Hz", "rtc alarm"; - clocks = <&soc_clocks PXA910_CLK_RTC>; - resets = <&soc_clocks PXA910_CLK_RTC>; - status = "disabled"; - }; - }; - - soc_clocks: clocks{ - compatible = "marvell,pxa910-clock"; - reg = <0xd4050000 0x1000>, - <0xd4282800 0x400>, - <0xd4015000 0x1000>, - <0xd403b000 0x1000>; - reg-names = "mpmu", "apmu", "apbc", "apbcp"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts b/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts deleted file mode 100644 index 5d75666..0000000 --- a/sys/gnu/dts/arm/qcom-apq8064-cm-qs600.dts +++ /dev/null @@ -1,59 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" - -/ { - model = "CompuLab CM-QS600"; - compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; - - soc { - pinctrl@800000 { - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@50 { - compatible = "24c02"; - reg = <0x50>; - pagesize = <32>; - }; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts b/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts deleted file mode 100644 index e641001..0000000 --- a/sys/gnu/dts/arm/qcom-apq8064-ifc6410.dts +++ /dev/null @@ -1,71 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include - -/ { - model = "Qualcomm APQ8064/IFC6410"; - compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; - - soc { - pinctrl@800000 { - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = ; - - i2c@12460000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - }; - }; - }; - - gsbi@16600000 { - status = "ok"; - qcom,mode = ; - serial@16640000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; - }; - /* WLAN */ - sdcc4: sdcc@121c0000 { - status = "okay"; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi b/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi deleted file mode 100644 index 935c394..0000000 --- a/sys/gnu/dts/arm/qcom-apq8064-v2.0.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "qcom-apq8064.dtsi" diff --git a/sys/gnu/dts/arm/qcom-apq8064.dtsi b/sys/gnu/dts/arm/qcom-apq8064.dtsi deleted file mode 100644 index b3154c0..0000000 --- a/sys/gnu/dts/arm/qcom-apq8064.dtsi +++ /dev/null @@ -1,353 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include -#include -#include - -/ { - model = "Qualcomm APQ8064"; - compatible = "qcom,apq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - }; - - cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - tlmm_pinmux: pinctrl@800000 { - compatible = "qcom,apq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&ps_hold>; - - sdc4_gpios: sdc4-gpios { - pios { - pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "sdc4"; - }; - }; - - ps_hold: ps_hold { - mux { - pins = "gpio78"; - function = "ps_hold"; - }; - }; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - acc2: clock-controller@20a8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; - }; - - acc3: clock-controller@20b8000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw2: regulator@20a9000 { - compatible = "qcom,saw2"; - reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw3: regulator@20b9000 { - compatible = "qcom,saw2"; - reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi1: gsbi@12440000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12440000 0x100>; - clocks = <&gcc GSBI1_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - i2c1: i2c@12460000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x12460000 0x1000>; - interrupts = <0 194 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi2: gsbi@12480000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - i2c2: i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = <0 196 IRQ_TYPE_NONE>; - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi7: gsbi@16600000 { - status = "disabled"; - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16600000 0x100>; - clocks = <&gcc GSBI7_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - serial@16640000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16640000 0x1000>, - <0x16600000 0x1000>; - interrupts = <0 158 0x0>; - clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-apq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mmcc: clock-controller@4000000 { - compatible = "qcom,mmcc-apq8064"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - sdcc1bam:dma@12402000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12402000 0x8000>; - interrupts = <0 98 0>; - clocks = <&gcc SDC1_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc3bam:dma@12182000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x12182000 0x8000>; - interrupts = <0 96 0>; - clocks = <&gcc SDC3_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - sdcc4bam:dma@121c2000{ - compatible = "qcom,bam-v1.3.0"; - reg = <0x121c2000 0x8000>; - interrupts = <0 95 0>; - clocks = <&gcc SDC4_H_CLK>; - clock-names = "bam_clk"; - #dma-cells = <1>; - qcom,ee = <0>; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; - dma-names = "tx", "rx"; - }; - - sdcc4: sdcc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - vmmc-supply = <&vsdcc_fixed>; - vqmmc-supply = <&vsdcc_fixed>; - dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&sdc4_gpios>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts b/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts deleted file mode 100644 index 4737049..0000000 --- a/sys/gnu/dts/arm/qcom-apq8074-dragonboard.dts +++ /dev/null @@ -1,66 +0,0 @@ -#include "qcom-msm8974.dtsi" - -/ { - model = "Qualcomm APQ8074 Dragonboard"; - compatible = "qcom,apq8074-dragonboard", "qcom,apq8074"; - - soc { - serial@f991e000 { - status = "ok"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "ok"; - }; - - sdhci@f98a4900 { - cd-gpios = <&msmgpio 62 0x1>; - bus-width = <4>; - }; - - - pinctrl@fd510000 { - i2c11_pins: i2c11 { - mux { - pins = "gpio83", "gpio84"; - function = "blsp_i2c11"; - }; - }; - - spi8_default: spi8_default { - mosi { - pins = "gpio45"; - function = "blsp_spi8"; - }; - miso { - pins = "gpio46"; - function = "blsp_spi8"; - }; - cs { - pins = "gpio47"; - function = "blsp_spi8"; - }; - clk { - pins = "gpio48"; - function = "blsp_spi8"; - }; - }; - }; - - i2c@f9967000 { - status = "okay"; - clock-frequency = <200000>; - pinctrl-0 = <&i2c11_pins>; - pinctrl-names = "default"; - - eeprom: eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; - read-only; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts b/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts deleted file mode 100644 index c9ff108..0000000 --- a/sys/gnu/dts/arm/qcom-apq8084-ifc6540.dts +++ /dev/null @@ -1,23 +0,0 @@ -#include "qcom-apq8084.dtsi" - -/ { - model = "Qualcomm APQ8084/IFC6540"; - compatible = "qcom,apq8084-ifc6540", "qcom,apq8084"; - - soc { - serial@f995e000 { - status = "okay"; - }; - - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; - }; - - sdhci@f98a4900 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084-mtp.dts b/sys/gnu/dts/arm/qcom-apq8084-mtp.dts deleted file mode 100644 index 8ecec58..0000000 --- a/sys/gnu/dts/arm/qcom-apq8084-mtp.dts +++ /dev/null @@ -1,12 +0,0 @@ -#include "qcom-apq8084.dtsi" - -/ { - model = "Qualcomm APQ 8084-MTP"; - compatible = "qcom,apq8084-mtp", "qcom,apq8084"; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-apq8084.dtsi b/sys/gnu/dts/arm/qcom-apq8084.dtsi deleted file mode 100644 index 1f130bc..0000000 --- a/sys/gnu/dts/arm/qcom-apq8084.dtsi +++ /dev/null @@ -1,230 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" - -#include -#include - -/ { - model = "Qualcomm APQ 8084"; - compatible = "qcom,apq8084"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <0>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <1>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <2>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <3>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - }; - - L2: l2-cache { - compatible = "qcom,arch-cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw_l2: regulator@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, - <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-apq8084"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - }; - - serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = <0 114 0x0>; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts b/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts deleted file mode 100644 index 55b2910..0000000 --- a/sys/gnu/dts/arm/qcom-ipq8064-ap148.dts +++ /dev/null @@ -1,93 +0,0 @@ -#include "qcom-ipq8064-v1.0.dtsi" - -/ { - model = "Qualcomm IPQ8064/AP148"; - compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - rsvd@41200000 { - reg = <0x41200000 0x300000>; - no-map; - }; - }; - - soc { - pinmux@800000 { - i2c4_pins: i2c4_pinmux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - bias-disable; - }; - - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; - }; - }; - - gsbi@16300000 { - qcom,mode = ; - status = "ok"; - serial@16340000 { - status = "ok"; - }; - - i2c4: i2c@16380000 { - status = "ok"; - - clock-frequency = <200000>; - - pinctrl-0 = <&i2c4_pins>; - pinctrl-names = "default"; - }; - }; - - gsbi5: gsbi@1a200000 { - qcom,mode = ; - status = "ok"; - - spi4: spi@1a280000 { - status = "ok"; - spi-max-frequency = <50000000>; - - pinctrl-0 = <&spi_pins>; - pinctrl-names = "default"; - - cs-gpios = <&qcom_pinmux 20 0>; - - flash: m25p80@0 { - compatible = "s25fl256s1"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <50000000>; - reg = <0>; - - partition@0 { - label = "rootfs"; - reg = <0x0 0x1000000>; - }; - - partition@1 { - label = "scratch"; - reg = <0x1000000 0x1000000>; - }; - }; - }; - }; - - sata-phy@1b400000 { - status = "ok"; - }; - - sata@29000000 { - status = "ok"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi b/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi deleted file mode 100644 index 7093b07..0000000 --- a/sys/gnu/dts/arm/qcom-ipq8064-v1.0.dtsi +++ /dev/null @@ -1 +0,0 @@ -#include "qcom-ipq8064.dtsi" diff --git a/sys/gnu/dts/arm/qcom-ipq8064.dtsi b/sys/gnu/dts/arm/qcom-ipq8064.dtsi deleted file mode 100644 index cb225da..0000000 --- a/sys/gnu/dts/arm/qcom-ipq8064.dtsi +++ /dev/null @@ -1,283 +0,0 @@ -/dts-v1/; - -#include "skeleton.dtsi" -#include -#include - -/ { - model = "Qualcomm IPQ8064"; - compatible = "qcom,ipq8064"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - nss@40000000 { - reg = <0x40000000 0x1000000>; - no-map; - }; - - smem@41000000 { - reg = <0x41000000 0x200000>; - no-map; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - }; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x12480000 0x100>; - clocks = <&gcc GSBI2_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - serial@12490000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x12490000 0x1000>, - <0x12480000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@124a0000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x124a0000 0x1000>; - interrupts = <0 196 0>; - - clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - }; - - gsbi4: gsbi@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = <0 152 0x0>; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gsbi5: gsbi@1a200000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x1a200000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - serial@1a240000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x1a240000 0x1000>, - <0x1a200000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - i2c@1a280000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - - spi@1a280000 { - compatible = "qcom,spi-qup-v1.1.1"; - reg = <0x1a280000 0x1000>; - interrupts = <0 155 0>; - - clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sata_phy: sata-phy@1b400000 { - compatible = "qcom,ipq806x-sata-phy"; - reg = <0x1b400000 0x200>; - - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - - #phy-cells = <0>; - status = "disabled"; - }; - - sata@29000000 { - compatible = "qcom,ipq806x-ahci", "generic-ahci"; - reg = <0x29000000 0x180>; - - interrupts = <0 209 0x0>; - - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", - "rxoob", "pmalive"; - - assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; - - phys = <&sata_phy>; - phy-names = "sata-phy"; - status = "disabled"; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x00500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-ipq8064"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8660-surf.dts b/sys/gnu/dts/arm/qcom-msm8660-surf.dts deleted file mode 100644 index e0883c3..0000000 --- a/sys/gnu/dts/arm/qcom-msm8660-surf.dts +++ /dev/null @@ -1,58 +0,0 @@ -#include - -#include "qcom-msm8660.dtsi" - -/ { - model = "Qualcomm MSM8660 SURF"; - compatible = "qcom,msm8660-surf", "qcom,msm8660"; - - soc { - gsbi@19c00000 { - status = "ok"; - qcom,mode = ; - serial@19c40000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - }; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_FN_F1) - MATRIX_KEY(0, 1, KEY_UP) - MATRIX_KEY(0, 2, KEY_LEFT) - MATRIX_KEY(0, 3, KEY_VOLUMEUP) - MATRIX_KEY(1, 0, KEY_FN_F2) - MATRIX_KEY(1, 1, KEY_RIGHT) - MATRIX_KEY(1, 2, KEY_DOWN) - MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) - MATRIX_KEY(2, 3, KEY_ENTER) - MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) - MATRIX_KEY(4, 1, KEY_UP) - MATRIX_KEY(4, 2, KEY_LEFT) - MATRIX_KEY(4, 3, KEY_HOME) - MATRIX_KEY(4, 4, KEY_FN_F3) - MATRIX_KEY(5, 0, KEY_CAMERA) - MATRIX_KEY(5, 1, KEY_RIGHT) - MATRIX_KEY(5, 2, KEY_DOWN) - MATRIX_KEY(5, 3, KEY_BACK) - MATRIX_KEY(5, 4, KEY_MENU) - >; - keypad,num-rows = <6>; - keypad,num-columns = <5>; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8660.dtsi b/sys/gnu/dts/arm/qcom-msm8660.dtsi deleted file mode 100644 index 0affd61..0000000 --- a/sys/gnu/dts/arm/qcom-msm8660.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include -#include -#include - -/ { - model = "Qualcomm MSM8660"; - compatible = "qcom,msm8660"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - compatible = "qcom,scorpion"; - enable-method = "qcom,gcc-msm8660"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2080000 { - compatible = "qcom,msm-8660-qgic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = < 0x02080000 0x1000 >, - < 0x02081000 0x1000 >; - }; - - timer@2000000 { - compatible = "qcom,scss-timer", "qcom,msm-timer"; - interrupts = <1 0 0x301>, - <1 1 0x301>, - <1 2 0x301>; - reg = <0x02000000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x40000>; - }; - - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - reg = <0x00800000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - ngpio = <173>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8660"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - gsbi12: gsbi@19c00000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x19c00000 0x100>; - clocks = <&gcc GSBI12_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - serial@19c40000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x19c40000 0x1000>, - <0x19c00000 0x1000>; - interrupts = <0 195 0x0>; - clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8058"; - interrupt-parent = <&msmgpio>; - interrupts = <88 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8058-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8058-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@11d { - compatible = "qcom,pm8058-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - - vibrator@4a { - compatible = "qcom,pm8058-vib"; - reg = <0x4a>; - }; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <48000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; - -}; diff --git a/sys/gnu/dts/arm/qcom-msm8960-cdp.dts b/sys/gnu/dts/arm/qcom-msm8960-cdp.dts deleted file mode 100644 index 7f70fae..0000000 --- a/sys/gnu/dts/arm/qcom-msm8960-cdp.dts +++ /dev/null @@ -1,43 +0,0 @@ -#include - -#include "qcom-msm8960.dtsi" - -/ { - model = "Qualcomm MSM8960 CDP"; - compatible = "qcom,msm8960-cdp", "qcom,msm8960"; - - soc { - gsbi@16400000 { - status = "ok"; - qcom,mode = ; - serial@16440000 { - status = "ok"; - }; - }; - - amba { - /* eMMC */ - sdcc1: sdcc@12400000 { - status = "okay"; - }; - - /* External micro SD card */ - sdcc3: sdcc@12180000 { - status = "okay"; - }; - }; - }; -}; - -&pmicintc { - keypad@148 { - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8960.dtsi b/sys/gnu/dts/arm/qcom-msm8960.dtsi deleted file mode 100644 index e1b0d5c..0000000 --- a/sys/gnu/dts/arm/qcom-msm8960.dtsi +++ /dev/null @@ -1,242 +0,0 @@ -/dts-v1/; - -/include/ "skeleton.dtsi" - -#include -#include -#include - -/ { - model = "Qualcomm MSM8960"; - compatible = "qcom,msm8960"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = <1 14 0x304>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v1"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 10 0x304>; - qcom,no-pc-write; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; - }; - - timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; - interrupts = <1 1 0x301>, - <1 2 0x301>, - <1 3 0x301>; - reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; - cpu-offset = <0x80000>; - }; - - msmgpio: gpio@800000 { - compatible = "qcom,msm-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpio = <150>; - interrupts = <0 16 0x4>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x800000 0x4000>; - }; - - gcc: clock-controller@900000 { - compatible = "qcom,gcc-msm8960"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0x900000 0x4000>; - }; - - clock-controller@4000000 { - compatible = "qcom,mmcc-msm8960"; - reg = <0x4000000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - acc0: clock-controller@2088000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02088000 0x1000>, <0x02008000 0x1000>; - }; - - acc1: clock-controller@2098000 { - compatible = "qcom,kpss-acc-v1"; - reg = <0x02098000 0x1000>, <0x02008000 0x1000>; - }; - - saw0: regulator@2089000 { - compatible = "qcom,saw2"; - reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - saw1: regulator@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - - gsbi5: gsbi@16400000 { - compatible = "qcom,gsbi-v1.0.0"; - reg = <0x16400000 0x100>; - clocks = <&gcc GSBI5_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - serial@16440000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts = <0 154 0x0>; - clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - }; - - qcom,ssbi@500000 { - compatible = "qcom,ssbi"; - reg = <0x500000 0x1000>; - qcom,controller-type = "pmic-arbiter"; - - pmicintc: pmic@0 { - compatible = "qcom,pm8921"; - interrupt-parent = <&msmgpio>; - interrupts = <104 8>; - #interrupt-cells = <2>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicintc>; - interrupts = <50 1>, <51 1>; - debounce = <15625>; - pull-up; - }; - - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 1>, <75 1>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - - rtc@11d { - compatible = "qcom,pm8921-rtc"; - interrupt-parent = <&pmicintc>; - interrupts = <39 1>; - reg = <0x11d>; - allow-set-time; - }; - }; - }; - - rng@1a500000 { - compatible = "qcom,prng"; - reg = <0x1a500000 0x200>; - clocks = <&gcc PRNG_CLK>; - clock-names = "core"; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - sdcc1: sdcc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; - non-removable; - cap-sd-highspeed; - cap-mmc-highspeed; - vmmc-supply = <&vsdcc_fixed>; - }; - - sdcc3: sdcc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <192000000>; - no-1-8-v; - vmmc-supply = <&vsdcc_fixed>; - }; - }; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts b/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts deleted file mode 100644 index cccc21b..0000000 --- a/sys/gnu/dts/arm/qcom-msm8974-sony-xperia-honami.dts +++ /dev/null @@ -1,17 +0,0 @@ -#include "qcom-msm8974.dtsi" - -/ { - model = "Sony Xperia Z1"; - compatible = "sony,xperia-honami", "qcom,msm8974"; - - memory@0 { - reg = <0 0x40000000>, <0x40000000 0x40000000>; - device_type = "memory"; - }; -}; - -&soc { - serial@f991e000 { - status = "ok"; - }; -}; diff --git a/sys/gnu/dts/arm/qcom-msm8974.dtsi b/sys/gnu/dts/arm/qcom-msm8974.dtsi deleted file mode 100644 index e265ec1..0000000 --- a/sys/gnu/dts/arm/qcom-msm8974.dtsi +++ /dev/null @@ -1,251 +0,0 @@ -/dts-v1/; - -#include -#include -#include "skeleton.dtsi" - -/ { - model = "Qualcomm MSM8974"; - compatible = "qcom,msm8974"; - interrupt-parent = <&intc>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - interrupts = <1 9 0xf04>; - - cpu@0 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - }; - - cpu@1 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - }; - - cpu@2 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <2>; - next-level-cache = <&L2>; - qcom,acc = <&acc2>; - }; - - cpu@3 { - compatible = "qcom,krait"; - enable-method = "qcom,kpss-acc-v2"; - device_type = "cpu"; - reg = <3>; - next-level-cache = <&L2>; - qcom,acc = <&acc3>; - }; - - L2: l2-cache { - compatible = "cache"; - cache-level = <2>; - qcom,saw = <&saw_l2>; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = <1 7 0xf04>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <19200000>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw_l2: regulator@f9012000 { - compatible = "qcom,saw2"; - reg = <0xf9012000 0x1000>; - regulator; - }; - - acc0: clock-controller@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; - }; - - acc1: clock-controller@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; - }; - - acc2: clock-controller@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; - }; - - acc3: clock-controller@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0xfc400000 0x4000>; - }; - - mmcc: clock-controller@fd8c0000 { - compatible = "qcom,mmcc-msm8974"; - #clock-cells = <1>; - #reset-cells = <1>; - reg = <0xfd8c0000 0x6000>; - }; - - serial@f991e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf991e000 0x1000>; - interrupts = <0 108 0x0>; - clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 123 0>, <0 138 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - interrupts = <0 125 0>, <0 221 0>; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - rng@f9bff000 { - compatible = "qcom,prng"; - reg = <0xf9bff000 0x200>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8974-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 208 0>; - }; - - blsp_i2c11: i2c@f9967000 { - status = "disable"; - compatible = "qcom,i2c-qup-v2.1.1"; - reg = <0xf9967000 0x1000>; - interrupts = <0 105 IRQ_TYPE_NONE>; - clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6400.dtsi b/sys/gnu/dts/arm/s3c6400.dtsi deleted file mode 100644 index a7d1c8e..0000000 --- a/sys/gnu/dts/arm/s3c6400.dtsi +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6410-mini6410.dts b/sys/gnu/dts/arm/s3c6410-mini6410.dts deleted file mode 100644 index a25debb..0000000 --- a/sys/gnu/dts/arm/s3c6410-mini6410.dts +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Samsung's S3C6410 based Mini6410 board device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for FriendlyARM Mini6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "FriendlyARM Mini6410 board based on S3C6410"; - compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x10000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - davicom,no-eeprom; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys>; - autorepeat; - - button-k1 { - label = "K1"; - gpios = <&gpn 0 GPIO_ACTIVE_LOW>; - linux,code = <2>; - debounce-interval = <20>; - }; - - button-k2 { - label = "K2"; - gpios = <&gpn 1 GPIO_ACTIVE_LOW>; - linux,code = <3>; - debounce-interval = <20>; - }; - - button-k3 { - label = "K3"; - gpios = <&gpn 2 GPIO_ACTIVE_LOW>; - linux,code = <4>; - debounce-interval = <20>; - }; - - button-k4 { - label = "K4"; - gpios = <&gpn 3 GPIO_ACTIVE_LOW>; - linux,code = <5>; - debounce-interval = <20>; - }; - - button-k5 { - label = "K5"; - gpios = <&gpn 4 GPIO_ACTIVE_LOW>; - linux,code = <6>; - debounce-interval = <20>; - }; - - button-k6 { - label = "K6"; - gpios = <&gpn 5 GPIO_ACTIVE_LOW>; - linux,code = <7>; - debounce-interval = <20>; - }; - - button-k7 { - label = "K7"; - gpios = <&gpl 11 GPIO_ACTIVE_LOW>; - linux,code = <8>; - debounce-interval = <20>; - }; - - button-k8 { - label = "K8"; - gpios = <&gpl 12 GPIO_ACTIVE_LOW>; - linux,code = <9>; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_leds>; - - led-1 { - label = "LED1"; - gpios = <&gpk 4 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-2 { - label = "LED2"; - gpios = <&gpk 5 GPIO_ACTIVE_LOW>; - linux,default-trigger = "mmc0"; - }; - - led-3 { - label = "LED3"; - gpios = <&gpk 6 GPIO_ACTIVE_LOW>; - }; - - led-4 { - label = "LED4"; - gpios = <&gpk 7 GPIO_ACTIVE_LOW>; - }; - }; - - buzzer { - compatible = "pwm-beeper"; - pwms = <&pwm 0 1000000 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_out>; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; - -&pinctrl0 { - gpio_leds: gpio-leds { - samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = ; - }; - - gpio_keys: gpio-keys { - samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", - "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = ; - }; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_bus>; - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c6410-smdk6410.dts b/sys/gnu/dts/arm/s3c6410-smdk6410.dts deleted file mode 100644 index ecf35ec..0000000 --- a/sys/gnu/dts/arm/s3c6410-smdk6410.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Samsung S3C6410 based SMDK6410 board device tree source. - * - * Copyright (c) 2013 Tomasz Figa - * - * Device tree source file for SAMSUNG SMDK6410 board which is based on - * Samsung's S3C6410 SoC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/dts-v1/; - -#include -#include - -#include "s3c6410.dtsi" - -/ { - model = "SAMSUNG SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; - - memory { - reg = <0x50000000 0x8000000>; - }; - - chosen { - bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - - srom-cs1@18000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x18000000 0x8000000>; - ranges; - - ethernet@18000000 { - compatible = "smsc,lan9115"; - reg = <0x18000000 0x10000>; - interrupt-parent = <&gpn>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,force-internal-phy; - }; - }; -}; - -&sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; - bus-width = <4>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/s3c6410.dtsi b/sys/gnu/dts/arm/s3c6410.dtsi deleted file mode 100644 index eb4226b..0000000 --- a/sys/gnu/dts/arm/s3c6410.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Samsung's S3C6410 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410 - * based board files can include this file and provide values for board specfic - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6410 SoC. As device tree coverage for S3C6410 increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6410"; - - aliases { - i2c1 = &i2c1; - }; -}; - -&vic0 { - valid-mask = <0xffffff7f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6410-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; - - i2c1: i2c@7f00f000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f00f000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <5>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; -}; diff --git a/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi b/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi deleted file mode 100644 index b1197d8..0000000 --- a/sys/gnu/dts/arm/s3c64xx-pinctrl.dtsi +++ /dev/null @@ -1,687 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - pin control-related definitions - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are - * listed as device tree nodes in this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 2 - -&pinctrl0 { - /* - * Pin banks - */ - - gpa: gpa { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpb: gpb { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpc: gpc { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpd: gpd { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpe: gpe { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpi: gpi { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpm: gpm { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpn: gpn { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpo: gpo { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpp: gpp { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpq: gpq { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data { - samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - uart2_data: uart2-data { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - uart3_data: uart3-data { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - ext_dma_0: ext-dma-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - ext_dma_1: ext-dma-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - irda_data_0: irda-data-0 { - samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - irda_data_1: irda-data-1 { - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - irda_sdbw: irda-sdbw { - samsung,pins = "gpb-4"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - i2c0_bus: i2c0-bus { - samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - i2c1_bus: i2c1-bus { - /* S3C6410-only */ - samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <6>; - samsung,pin-pud = ; - }; - - spi0_bus: spi0-bus { - samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - spi0_cs: spi0-cs { - samsung,pins = "gpc-3"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - spi1_bus: spi1-bus { - samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - spi1_cs: spi1-cs { - samsung,pins = "gpc-7"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd0_cmd: sd0-cmd { - samsung,pins = "gpg-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd0_clk: sd0-clk { - samsung,pins = "gpg-0"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd0_bus1: sd0-bus1 { - samsung,pins = "gpg-2"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd0_bus4: sd0-bus4 { - samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd0_cd: sd0-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_cmd: sd1-cmd { - samsung,pins = "gph-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_clk: sd1-clk { - samsung,pins = "gph-0"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_bus1: sd1-bus1 { - samsung,pins = "gph-2"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_bus4: sd1-bus4 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_bus8: sd1-bus8 { - samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", - "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - sd1_cd: sd1-cd { - samsung,pins = "gpg-6"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - sd2_cmd: sd2-cmd { - samsung,pins = "gpc-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - sd2_clk: sd2-clk { - samsung,pins = "gpc-5"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - sd2_bus1: sd2-bus1 { - samsung,pins = "gph-6"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - sd2_bus4: sd2-bus4 { - samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - i2s0_bus: i2s0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - i2s0_cdclk: i2s0-cdclk { - samsung,pins = "gpd-1"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - i2s1_bus: i2s1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - i2s1_cdclk: i2s1-cdclk { - samsung,pins = "gpe-1"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - i2s2_bus: i2s2-bus { - /* S3C6410-only */ - samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", - "gph-8", "gph-9"; - samsung,pin-function = <5>; - samsung,pin-pud = ; - }; - - i2s2_cdclk: i2s2-cdclk { - /* S3C6410-only */ - samsung,pins = "gph-7"; - samsung,pin-function = <5>; - samsung,pin-pud = ; - }; - - pcm0_bus: pcm0-bus { - samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - pcm0_extclk: pcm0-extclk { - samsung,pins = "gpd-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - pcm1_bus: pcm1-bus { - samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - pcm1_extclk: pcm1-extclk { - samsung,pins = "gpe-1"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - ac97_bus_0: ac97-bus-0 { - samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - ac97_bus_1: ac97-bus-1 { - samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - cam_port: cam-port { - samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", - "gpf-5", "gpf-6", "gpf-7", "gpf-8", - "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - cam_rst: cam-rst { - samsung,pins = "gpf-3"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - cam_field: cam-field { - /* S3C6410-only */ - samsung,pins = "gpb-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - pwm_extclk: pwm-extclk { - samsung,pins = "gpf-13"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - pwm0_out: pwm0-out { - samsung,pins = "gpf-14"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - pwm1_out: pwm1-out { - samsung,pins = "gpf-15"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - clkout0: clkout-0 { - samsung,pins = "gpf-14"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col0_0: keypad-col0-0 { - samsung,pins = "gph-0"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col1_0: keypad-col1-0 { - samsung,pins = "gph-1"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col2_0: keypad-col2-0 { - samsung,pins = "gph-2"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col3_0: keypad-col3-0 { - samsung,pins = "gph-3"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col4_0: keypad-col4-0 { - samsung,pins = "gph-4"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col5_0: keypad-col5-0 { - samsung,pins = "gph-5"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col6_0: keypad-col6-0 { - samsung,pins = "gph-6"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col7_0: keypad-col7-0 { - samsung,pins = "gph-7"; - samsung,pin-function = <4>; - samsung,pin-pud = ; - }; - - keypad_col0_1: keypad-col0-1 { - samsung,pins = "gpl-0"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col1_1: keypad-col1-1 { - samsung,pins = "gpl-1"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col2_1: keypad-col2-1 { - samsung,pins = "gpl-2"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col3_1: keypad-col3-1 { - samsung,pins = "gpl-3"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col4_1: keypad-col4-1 { - samsung,pins = "gpl-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col5_1: keypad-col5-1 { - samsung,pins = "gpl-5"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col6_1: keypad-col6-1 { - samsung,pins = "gpl-6"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_col7_1: keypad-col7-1 { - samsung,pins = "gpl-7"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row0_0: keypad-row0-0 { - samsung,pins = "gpk-8"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row1_0: keypad-row1-0 { - samsung,pins = "gpk-9"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row2_0: keypad-row2-0 { - samsung,pins = "gpk-10"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row3_0: keypad-row3-0 { - samsung,pins = "gpk-11"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row4_0: keypad-row4-0 { - samsung,pins = "gpk-12"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row5_0: keypad-row5-0 { - samsung,pins = "gpk-13"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row6_0: keypad-row6-0 { - samsung,pins = "gpk-14"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row7_0: keypad-row7-0 { - samsung,pins = "gpk-15"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row0_1: keypad-row0-1 { - samsung,pins = "gpn-0"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row1_1: keypad-row1-1 { - samsung,pins = "gpn-1"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row2_1: keypad-row2-1 { - samsung,pins = "gpn-2"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row3_1: keypad-row3-1 { - samsung,pins = "gpn-3"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row4_1: keypad-row4-1 { - samsung,pins = "gpn-4"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row5_1: keypad-row5-1 { - samsung,pins = "gpn-5"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row6_1: keypad-row6-1 { - samsung,pins = "gpn-6"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - keypad_row7_1: keypad-row7-1 { - samsung,pins = "gpn-7"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; - - lcd_ctrl: lcd-ctrl { - samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - lcd_data16: lcd-data-width16 { - samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", - "gpi-7", "gpi-10", "gpi-11", "gpi-12", - "gpi-13", "gpi-14", "gpi-15", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - lcd_data18: lcd-data-width18 { - samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", - "gpi-6", "gpi-7", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-2", "gpj-3", "gpj-4", "gpj-5", - "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - lcd_data24: lcd-data-width24 { - samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", - "gpi-4", "gpi-5", "gpi-6", "gpi-7", - "gpi-8", "gpi-9", "gpi-10", "gpi-11", - "gpi-12", "gpi-13", "gpi-14", "gpi-15", - "gpj-0", "gpj-1", "gpj-2", "gpj-3", - "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; - samsung,pin-pud = ; - }; - - hsi_bus: hsi-bus { - samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", - "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <3>; - samsung,pin-pud = ; - }; -}; diff --git a/sys/gnu/dts/arm/s3c64xx.dtsi b/sys/gnu/dts/arm/s3c64xx.dtsi deleted file mode 100644 index 0ccb414..0000000 --- a/sys/gnu/dts/arm/s3c64xx.dtsi +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Samsung's S3C64xx SoC series common device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C64xx SoC series device nodes are listed in this file. - * Particular SoCs from S3C64xx series can include this file and provide - * values for SoCs specfic bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional - * nodes can be added to this file. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include "skeleton.dtsi" -#include - -/ { - aliases { - i2c0 = &i2c0; - pinctrl0 = &pinctrl0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; - reg = <0x0>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - vic0: interrupt-controller@71200000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71200000 0x1000>; - #interrupt-cells = <1>; - }; - - vic1: interrupt-controller@71300000 { - compatible = "arm,pl192-vic"; - interrupt-controller; - reg = <0x71300000 0x1000>; - #interrupt-cells = <1>; - }; - - sdhci0: sdhci@7c200000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c200000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <24>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks SCLK_MMC0>; - status = "disabled"; - }; - - sdhci1: sdhci@7c300000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c300000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <25>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks SCLK_MMC1>; - status = "disabled"; - }; - - sdhci2: sdhci@7c400000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x7c400000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <17>; - clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>, - <&clocks SCLK_MMC2>; - status = "disabled"; - }; - - watchdog: watchdog@7e004000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x7e004000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <26>; - clock-names = "watchdog"; - clocks = <&clocks PCLK_WDT>; - status = "disabled"; - }; - - i2c0: i2c@7f004000 { - compatible = "samsung,s3c2440-i2c"; - reg = <0x7f004000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <18>; - clock-names = "i2c"; - clocks = <&clocks PCLK_IIC0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@7f005000 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005000 0x100>; - interrupt-parent = <&vic1>; - interrupts = <5>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart1: serial@7f005400 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005400 0x100>; - interrupt-parent = <&vic1>; - interrupts = <6>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart2: serial@7f005800 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005800 0x100>; - interrupt-parent = <&vic1>; - interrupts = <7>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - uart3: serial@7f005c00 { - compatible = "samsung,s3c6400-uart"; - reg = <0x7f005c00 0x100>; - interrupt-parent = <&vic1>; - interrupts = <8>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - pwm: pwm@7f006000 { - compatible = "samsung,s3c6400-pwm"; - reg = <0x7f006000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <23>, <24>, <25>, <27>, <28>; - clock-names = "timers"; - clocks = <&clocks PCLK_PWM>; - samsung,pwm-outputs = <0>, <1>; - #pwm-cells = <3>; - }; - - pinctrl0: pinctrl@7f008000 { - compatible = "samsung,s3c64xx-pinctrl"; - reg = <0x7f008000 0x1000>; - interrupt-parent = <&vic1>; - interrupts = <21>; - - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - - wakeup-interrupt-controller { - compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; - }; - }; - }; -}; - -#include "s3c64xx-pinctrl.dtsi" diff --git a/sys/gnu/dts/arm/socfpga.dtsi b/sys/gnu/dts/arm/socfpga.dtsi deleted file mode 100644 index 252c3d1..0000000 --- a/sys/gnu/dts/arm/socfpga.dtsi +++ /dev/null @@ -1,782 +0,0 @@ -/* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "skeleton.dtsi" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - intc: intc@fffed000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xfffed000 0x1000>, - <0xfffec100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffe01000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffe01000 0x1000>; - interrupts = <0 104 4>, - <0 105 4>, - <0 106 4>, - <0 107 4>, - <0 108 4>, - <0 109 4>, - <0 110 4>, - <0 111 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - clocks = <&l4_main_clk>; - clock-names = "apb_pclk"; - }; - }; - - can0: can@ffc00000 { - compatible = "bosch,d_can"; - reg = <0xffc00000 0x1000>; - interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; - clocks = <&can0_clk>; - status = "disabled"; - }; - - can1: can@ffc01000 { - compatible = "bosch,d_can"; - reg = <0xffc01000 0x1000>; - interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; - clocks = <&can1_clk>; - status = "disabled"; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc2: osc2 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_periph_ref_clk: f2s_periph_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_sdram_ref_clk: f2s_sdram_ref_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - reg = <0x40>; - - mpuclk: mpuclk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe0 0 9>; - reg = <0x48>; - }; - - mainclk: mainclk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe4 0 9>; - reg = <0x4C>; - }; - - dbg_base_clk: dbg_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - div-reg = <0xe8 0 9>; - reg = <0x50>; - }; - - main_qspi_clk: main_qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x54>; - }; - - main_nand_sdmmc_clk: main_nand_sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x58>; - }; - - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&main_pll>; - reg = <0x5C>; - }; - }; - - periph_pll: periph_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; - reg = <0x80>; - - emac0_clk: emac0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x88>; - }; - - emac1_clk: emac1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x8C>; - }; - - per_qspi_clk: per_qsi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x90>; - }; - - per_nand_mmc_clk: per_nand_mmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x94>; - }; - - per_base_clk: per_base_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x98>; - }; - - h2f_usr1_clk: h2f_usr1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&periph_pll>; - reg = <0x9C>; - }; - }; - - sdram_pll: sdram_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; - reg = <0xC0>; - - ddr_dqs_clk: ddr_dqs_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xC8>; - }; - - ddr_2x_dqs_clk: ddr_2x_dqs_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xCC>; - }; - - ddr_dq_clk: ddr_dq_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD0>; - }; - - h2f_usr2_clk: h2f_usr2_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&sdram_pll>; - reg = <0xD4>; - }; - }; - - mpu_periph_clk: mpu_periph_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <4>; - }; - - mpu_l2_ram_clk: mpu_l2_ram_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mpuclk>; - fixed-divider = <2>; - }; - - l4_main_clk: l4_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - clk-gate = <0x60 0>; - }; - - l3_main_clk: l3_main_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-perip-clk"; - clocks = <&mainclk>; - fixed-divider = <1>; - }; - - l3_mp_clk: l3_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 0 2>; - clk-gate = <0x60 1>; - }; - - l3_sp_clk: l3_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>; - div-reg = <0x64 2 2>; - }; - - l4_mp_clk: l4_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 4 3>; - clk-gate = <0x60 2>; - }; - - l4_sp_clk: l4_sp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&mainclk>, <&per_base_clk>; - div-reg = <0x64 7 3>; - clk-gate = <0x60 3>; - }; - - dbg_at_clk: dbg_at_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 0 2>; - clk-gate = <0x60 4>; - }; - - dbg_clk: dbg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x68 2 2>; - clk-gate = <0x60 5>; - }; - - dbg_trace_clk: dbg_trace_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - div-reg = <0x6C 0 3>; - clk-gate = <0x60 6>; - }; - - dbg_timer_clk: dbg_timer_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&dbg_base_clk>; - clk-gate = <0x60 7>; - }; - - cfg_clk: cfg_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 8>; - }; - - h2f_user0_clk: h2f_user0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&cfg_h2f_usr0_clk>; - clk-gate = <0x60 9>; - }; - - emac_0_clk: emac_0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac0_clk>; - clk-gate = <0xa0 0>; - }; - - emac_1_clk: emac_1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&emac1_clk>; - clk-gate = <0xa0 1>; - }; - - usb_mp_clk: usb_mp_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 2>; - div-reg = <0xa4 0 3>; - }; - - spi_m_clk: spi_m_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 3>; - div-reg = <0xa4 3 3>; - }; - - can0_clk: can0_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 4>; - div-reg = <0xa4 6 3>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 5>; - div-reg = <0xa4 9 3>; - }; - - gpio_db_clk: gpio_db_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&per_base_clk>; - clk-gate = <0xa0 6>; - div-reg = <0xa8 0 24>; - }; - - h2f_user1_clk: h2f_user1_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&h2f_usr1_clk>; - clk-gate = <0xa0 7>; - }; - - sdmmc_clk: sdmmc_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 8>; - clk-phase = <0 135>; - }; - - nand_x_clk: nand_x_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 9>; - }; - - nand_clk: nand_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; - clk-gate = <0xa0 10>; - fixed-divider = <4>; - }; - - qspi_clk: qspi_clk { - #clock-cells = <0>; - compatible = "altr,socfpga-gate-clk"; - clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; - clk-gate = <0xa0 11>; - }; - }; - }; - - gmac0: ethernet@ff700000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 0>; - reg = <0xff700000 0x2000>; - interrupts = <0 115 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac0_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - status = "disabled"; - }; - - gmac1: ethernet@ff702000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x60 2>; - reg = <0xff702000 0x2000>; - interrupts = <0 120 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ - clocks = <&emac1_clk>; - clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; - snps,multicast-filter-bins = <256>; - snps,perfect-filter-entries = <128>; - status = "disabled"; - }; - - i2c0: i2c@ffc04000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc04000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 158 0x4>; - status = "disabled"; - }; - - i2c1: i2c@ffc05000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc05000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 159 0x4>; - status = "disabled"; - }; - - i2c2: i2c@ffc06000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc06000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 160 0x4>; - status = "disabled"; - }; - - i2c3: i2c@ffc07000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc07000 0x1000>; - clocks = <&l4_sp_clk>; - interrupts = <0 161 0x4>; - status = "disabled"; - }; - - gpio0: gpio@ff708000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff708000 0x1000>; - clocks = <&per_base_clk>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 164 4>; - }; - }; - - gpio1: gpio@ff709000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff709000 0x1000>; - clocks = <&per_base_clk>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 165 4>; - }; - }; - - gpio2: gpio@ff70a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xff70a000 0x1000>; - clocks = <&per_base_clk>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 166 4>; - }; - }; - - sdr: sdr@ffc25000 { - compatible = "syscon"; - reg = <0xffc25000 0x1000>; - }; - - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; - - L2: l2-cache@fffef000 { - compatible = "arm,pl310-cache"; - reg = <0xfffef000 0x1000>; - interrupts = <0 38 0x04>; - cache-unified; - cache-level = <2>; - arm,tag-latency = <1 1 1>; - arm,data-latency = <2 1 1>; - }; - - mmc: dwmmc0@ff704000 { - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff704000 0x1000>; - interrupts = <0 139 4>; - fifo-depth = <0x400>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&l4_mp_clk>, <&sdmmc_clk>; - clock-names = "biu", "ciu"; - }; - - ocram: sram@ffff0000 { - compatible = "mmio-sram"; - reg = <0xffff0000 0x10000>; - }; - - spi0: spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - status = "disabled"; - }; - - spi1: spi@fff01000 { - compatible = "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfff01000 0x1000>; - interrupts = <0 156 4>; - num-cs = <4>; - clocks = <&spi_m_clk>; - status = "disabled"; - }; - - /* Local timer */ - timer@fffec600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xfffec600 0x100>; - interrupts = <1 13 0xf04>; - clocks = <&mpu_periph_clk>; - }; - - timer0: timer0@ffc08000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 167 4>; - reg = <0xffc08000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer1: timer1@ffc09000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 168 4>; - reg = <0xffc09000 0x1000>; - clocks = <&l4_sp_clk>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 169 4>; - reg = <0xffd00000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - }; - - timer3: timer3@ffd01000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffd01000 0x1000>; - clocks = <&osc1>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x1000>; - interrupts = <0 162 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - }; - - uart1: serial1@ffc03000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc03000 0x1000>; - interrupts = <0 163 4>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&l4_sp_clk>; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 125 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 128 4>; - clocks = <&usb_mp_clk>; - clock-names = "otg"; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd02000 { - compatible = "snps,dw-wdt"; - reg = <0xffd02000 0x1000>; - interrupts = <0 171 4>; - clocks = <&osc1>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd03000 { - compatible = "snps,dw-wdt"; - reg = <0xffd03000 0x1000>; - interrupts = <0 172 4>; - clocks = <&osc1>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd08000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd08000 0x4000>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10.dtsi b/sys/gnu/dts/arm/socfpga_arria10.dtsi deleted file mode 100644 index 8a05c47..0000000 --- a/sys/gnu/dts/arm/socfpga_arria10.dtsi +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -#include "skeleton.dtsi" -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - serial0 = &uart0; - serial1 = &uart1; - timer0 = &timer0; - timer1 = &timer1; - timer2 = &timer2; - timer3 = &timer3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <0>; - next-level-cache = <&L2>; - }; - cpu@1 { - compatible = "arm,cortex-a9"; - device_type = "cpu"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - intc: intc@ffffd000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xffffd000 0x1000>, - <0xffffc100 0x100>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@ffda1000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda1000 0x1000>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, - <0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 85 IRQ_TYPE_LEVEL_HIGH>, - <0 86 IRQ_TYPE_LEVEL_HIGH>, - <0 87 IRQ_TYPE_LEVEL_HIGH>, - <0 88 IRQ_TYPE_LEVEL_HIGH>, - <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - }; - - clkmgr@ffd04000 { - compatible = "altr,clk-mgr"; - reg = <0xffd04000 0x1000>; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - main_pll: main_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - }; - - periph_pll: periph_pll { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "altr,socfpga-pll-clock"; - clocks = <&osc1>; - }; - }; - }; - - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - /* Filled in by bootloader */ - mac-address = [00 00 00 00 00 00]; - status = "disabled"; - }; - - gpio0: gpio@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02900 0x100>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02a00 0x100>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <29>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio2: gpio@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc02b00 0x100>; - status = "disabled"; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <27>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - i2c0: i2c@ffc02200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02200 0x100>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c1: i2c@ffc02300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02300 0x100>; - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c2: i2c@ffc02400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02400 0x100>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c3: i2c@ffc02500 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02500 0x100>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - i2c4: i2c@ffc02600 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02600 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - L2: l2-cache@fffff000 { - compatible = "arm,pl310-cache"; - reg = <0xfffff000 0x1000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; - cache-unified; - cache-level = <2>; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; - fifo-depth = <0x400>; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - rst: rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x100>; - }; - - sysmgr: sysmgr@ffd06000 { - compatible = "altr,sys-mgr", "syscon"; - reg = <0xffd06000 0x300>; - }; - - /* Local timer */ - timer@ffffc600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0xffffc600 0x100>; - interrupts = <1 13 0xf04>; - }; - - timer0: timer0@ffc02700 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02700 0x100>; - }; - - timer1: timer1@ffc02800 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffc02800 0x100>; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd00000 0x100>; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xffd01000 0x100>; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0xffff>; - interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0xffff>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria10_socdk.dts b/sys/gnu/dts/arm/socfpga_arria10_socdk.dts deleted file mode 100755 index 3015ce8..0000000 --- a/sys/gnu/dts/arm/socfpga_arria10_socdk.dts +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2014 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -#include "socfpga_arria10.dtsi" - -/ { - model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200 rootwait"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - serial0@ffc02000 { - status = "okay"; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria5.dtsi b/sys/gnu/dts/arm/socfpga_arria5.dtsi deleted file mode 100644 index 1907cc6..0000000 --- a/sys/gnu/dts/arm/socfpga_arria5.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; diff --git a/sys/gnu/dts/arm/socfpga_arria5_socdk.dts b/sys/gnu/dts/arm/socfpga_arria5_socdk.dts deleted file mode 100644 index ccaf417..0000000 --- a/sys/gnu/dts/arm/socfpga_arria5_socdk.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_arria5.dtsi" - -/ { - model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi b/sys/gnu/dts/arm/socfpga_cyclone5.dtsi deleted file mode 100644 index 06db951..0000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5.dtsi +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -/* First 4KB has trampoline code for secondary cores. */ -/memreserve/ 0x00000000 0x0001000; -#include "socfpga.dtsi" - -/ { - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; - - mmc0: dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd080c4>; - }; - }; -}; - -&watchdog0 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts b/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts deleted file mode 100644 index 258865d..0000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_socdk.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - regulator_3_3v: 3-3-v-regulator { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - - rtc@68 { - compatible = "dallas,ds1339"; - reg = <0x68>; - }; -}; - -&mmc0 { - cd-gpios = <&portb 18 0>; - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts b/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts deleted file mode 100644 index 16ea6f5..0000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_sockit.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2013 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "Terasic SoCkit"; - compatible = "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; - - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; - }; - - regulator_3_3v: vcc3p3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VCC3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&gmac1 { - status = "okay"; - phy-mode = "rgmii"; - - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txen-skew-ps = <0>; - txc-skew-ps = <2600>; - rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; -}; - -&mmc0 { - vmmc-supply = <®ulator_3_3v>; - vqmmc-supply = <®ulator_3_3v>; -}; - -&usb1 { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts b/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts deleted file mode 100644 index a1814b4..0000000 --- a/sys/gnu/dts/arm/socfpga_cyclone5_socrates.dts +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2014 Steffen Trumtrar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "socfpga_cyclone5.dtsi" - -/ { - model = "EBV SOCrates"; - compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,115200"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1GB */ - }; -}; - -&gmac1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - rtc: rtc@68 { - compatible = "stm,m41t82"; - reg = <0x68>; - }; -}; - -&mmc { - status = "okay"; -}; diff --git a/sys/gnu/dts/arm/socfpga_vt.dts b/sys/gnu/dts/arm/socfpga_vt.dts deleted file mode 100644 index f9345e0..0000000 --- a/sys/gnu/dts/arm/socfpga_vt.dts +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/dts-v1/; -#include "socfpga.dtsi" - -/ { - model = "Altera SOCFPGA VT"; - compatible = "altr,socfpga-vt", "altr,socfpga"; - - chosen { - bootargs = "console=ttyS0,57600"; - }; - - memory { - name = "memory"; - device_type = "memory"; - reg = <0x0 0x40000000>; /* 1 GB */ - }; - - soc { - clkmgr@ffd04000 { - clocks { - osc1 { - clock-frequency = <10000000>; - }; - }; - }; - - dwmmc0@ff704000 { - num-slots = <1>; - broken-cd; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - }; - - ethernet@ff700000 { - phy-mode = "gmii"; - status = "okay"; - }; - - timer0@ffc08000 { - clock-frequency = <7000000>; - }; - - timer1@ffc09000 { - clock-frequency = <7000000>; - }; - - timer2@ffd00000 { - clock-frequency = <7000000>; - }; - - timer3@ffd01000 { - clock-frequency = <7000000>; - }; - - serial0@ffc02000 { - clock-frequency = <7372800>; - }; - - serial1@ffc03000 { - clock-frequency = <7372800>; - }; - - sysmgr@ffd08000 { - cpu1-start-addr = <0xffd08010>; - }; - }; -}; - -&gmac0 { - status = "okay"; - phy-mode = "gmii"; -}; diff --git a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h b/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h deleted file mode 100644 index 04e8db2..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/alphascale,asm9260.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright 2014 Oleksij Rempel - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_ASM9260_H -#define _DT_BINDINGS_CLK_ASM9260_H - -/* ahb gate */ -#define CLKID_AHB_ROM 0 -#define CLKID_AHB_RAM 1 -#define CLKID_AHB_GPIO 2 -#define CLKID_AHB_MAC 3 -#define CLKID_AHB_EMI 4 -#define CLKID_AHB_USB0 5 -#define CLKID_AHB_USB1 6 -#define CLKID_AHB_DMA0 7 -#define CLKID_AHB_DMA1 8 -#define CLKID_AHB_UART0 9 -#define CLKID_AHB_UART1 10 -#define CLKID_AHB_UART2 11 -#define CLKID_AHB_UART3 12 -#define CLKID_AHB_UART4 13 -#define CLKID_AHB_UART5 14 -#define CLKID_AHB_UART6 15 -#define CLKID_AHB_UART7 16 -#define CLKID_AHB_UART8 17 -#define CLKID_AHB_UART9 18 -#define CLKID_AHB_I2S0 19 -#define CLKID_AHB_I2C0 20 -#define CLKID_AHB_I2C1 21 -#define CLKID_AHB_SSP0 22 -#define CLKID_AHB_IOCONFIG 23 -#define CLKID_AHB_WDT 24 -#define CLKID_AHB_CAN0 25 -#define CLKID_AHB_CAN1 26 -#define CLKID_AHB_MPWM 27 -#define CLKID_AHB_SPI0 28 -#define CLKID_AHB_SPI1 29 -#define CLKID_AHB_QEI 30 -#define CLKID_AHB_QUADSPI0 31 -#define CLKID_AHB_CAMIF 32 -#define CLKID_AHB_LCDIF 33 -#define CLKID_AHB_TIMER0 34 -#define CLKID_AHB_TIMER1 35 -#define CLKID_AHB_TIMER2 36 -#define CLKID_AHB_TIMER3 37 -#define CLKID_AHB_IRQ 38 -#define CLKID_AHB_RTC 39 -#define CLKID_AHB_NAND 40 -#define CLKID_AHB_ADC0 41 -#define CLKID_AHB_LED 42 -#define CLKID_AHB_DAC0 43 -#define CLKID_AHB_LCD 44 -#define CLKID_AHB_I2S1 45 -#define CLKID_AHB_MAC1 46 - -/* devider */ -#define CLKID_SYS_CPU 47 -#define CLKID_SYS_AHB 48 -#define CLKID_SYS_I2S0M 49 -#define CLKID_SYS_I2S0S 50 -#define CLKID_SYS_I2S1M 51 -#define CLKID_SYS_I2S1S 52 -#define CLKID_SYS_UART0 53 -#define CLKID_SYS_UART1 54 -#define CLKID_SYS_UART2 55 -#define CLKID_SYS_UART3 56 -#define CLKID_SYS_UART4 56 -#define CLKID_SYS_UART5 57 -#define CLKID_SYS_UART6 58 -#define CLKID_SYS_UART7 59 -#define CLKID_SYS_UART8 60 -#define CLKID_SYS_UART9 61 -#define CLKID_SYS_SPI0 62 -#define CLKID_SYS_SPI1 63 -#define CLKID_SYS_QUADSPI 64 -#define CLKID_SYS_SSP0 65 -#define CLKID_SYS_NAND 66 -#define CLKID_SYS_TRACE 67 -#define CLKID_SYS_CAMM 68 -#define CLKID_SYS_WDT 69 -#define CLKID_SYS_CLKOUT 70 -#define CLKID_SYS_MAC 71 -#define CLKID_SYS_LCD 72 -#define CLKID_SYS_ADCANA 73 - -#define MAX_CLKS 74 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h b/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h deleted file mode 100644 index beb41ac..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/lsi,axm5516-clks.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2014 LSI Corporation - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - */ - -#ifndef _DT_BINDINGS_CLK_AXM5516_H -#define _DT_BINDINGS_CLK_AXM5516_H - -#define AXXIA_CLK_FAB_PLL 0 -#define AXXIA_CLK_CPU_PLL 1 -#define AXXIA_CLK_SYS_PLL 2 -#define AXXIA_CLK_SM0_PLL 3 -#define AXXIA_CLK_SM1_PLL 4 -#define AXXIA_CLK_FAB_DIV 5 -#define AXXIA_CLK_SYS_DIV 6 -#define AXXIA_CLK_NRCP_DIV 7 -#define AXXIA_CLK_CPU0_DIV 8 -#define AXXIA_CLK_CPU1_DIV 9 -#define AXXIA_CLK_CPU2_DIV 10 -#define AXXIA_CLK_CPU3_DIV 11 -#define AXXIA_CLK_PER_DIV 12 -#define AXXIA_CLK_MMC_DIV 13 -#define AXXIA_CLK_FAB 14 -#define AXXIA_CLK_SYS 15 -#define AXXIA_CLK_NRCP 16 -#define AXXIA_CLK_CPU0 17 -#define AXXIA_CLK_CPU1 18 -#define AXXIA_CLK_CPU2 19 -#define AXXIA_CLK_CPU3 20 -#define AXXIA_CLK_PER 21 -#define AXXIA_CLK_MMC 22 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h deleted file mode 100644 index 591f7fb..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,mmp2.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef __DTS_MARVELL_MMP2_CLOCK_H -#define __DTS_MARVELL_MMP2_CLOCK_H - -/* fixed clocks and plls */ -#define MMP2_CLK_CLK32 1 -#define MMP2_CLK_VCTCXO 2 -#define MMP2_CLK_PLL1 3 -#define MMP2_CLK_PLL1_2 8 -#define MMP2_CLK_PLL1_4 9 -#define MMP2_CLK_PLL1_8 10 -#define MMP2_CLK_PLL1_16 11 -#define MMP2_CLK_PLL1_3 12 -#define MMP2_CLK_PLL1_6 13 -#define MMP2_CLK_PLL1_12 14 -#define MMP2_CLK_PLL1_20 15 -#define MMP2_CLK_PLL2 16 -#define MMP2_CLK_PLL2_2 17 -#define MMP2_CLK_PLL2_4 18 -#define MMP2_CLK_PLL2_8 19 -#define MMP2_CLK_PLL2_16 20 -#define MMP2_CLK_PLL2_3 21 -#define MMP2_CLK_PLL2_6 22 -#define MMP2_CLK_PLL2_12 23 -#define MMP2_CLK_VCTCXO_2 24 -#define MMP2_CLK_VCTCXO_4 25 -#define MMP2_CLK_UART_PLL 26 -#define MMP2_CLK_USB_PLL 27 - -/* apb periphrals */ -#define MMP2_CLK_TWSI0 60 -#define MMP2_CLK_TWSI1 61 -#define MMP2_CLK_TWSI2 62 -#define MMP2_CLK_TWSI3 63 -#define MMP2_CLK_TWSI4 64 -#define MMP2_CLK_TWSI5 65 -#define MMP2_CLK_GPIO 66 -#define MMP2_CLK_KPC 67 -#define MMP2_CLK_RTC 68 -#define MMP2_CLK_PWM0 69 -#define MMP2_CLK_PWM1 70 -#define MMP2_CLK_PWM2 71 -#define MMP2_CLK_PWM3 72 -#define MMP2_CLK_UART0 73 -#define MMP2_CLK_UART1 74 -#define MMP2_CLK_UART2 75 -#define MMP2_CLK_UART3 76 -#define MMP2_CLK_SSP0 77 -#define MMP2_CLK_SSP1 78 -#define MMP2_CLK_SSP2 79 -#define MMP2_CLK_SSP3 80 - -/* axi periphrals */ -#define MMP2_CLK_SDH0 101 -#define MMP2_CLK_SDH1 102 -#define MMP2_CLK_SDH2 103 -#define MMP2_CLK_SDH3 104 -#define MMP2_CLK_USB 105 -#define MMP2_CLK_DISP0 106 -#define MMP2_CLK_DISP0_MUX 107 -#define MMP2_CLK_DISP0_SPHY 108 -#define MMP2_CLK_DISP1 109 -#define MMP2_CLK_DISP1_MUX 110 -#define MMP2_CLK_CCIC_ARBITER 111 -#define MMP2_CLK_CCIC0 112 -#define MMP2_CLK_CCIC0_MIX 113 -#define MMP2_CLK_CCIC0_PHY 114 -#define MMP2_CLK_CCIC0_SPHY 115 -#define MMP2_CLK_CCIC1 116 -#define MMP2_CLK_CCIC1_MIX 117 -#define MMP2_CLK_CCIC1_PHY 118 -#define MMP2_CLK_CCIC1_SPHY 119 - -#define MMP2_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h deleted file mode 100644 index 79630b9..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa168.h +++ /dev/null @@ -1,57 +0,0 @@ -#ifndef __DTS_MARVELL_PXA168_CLOCK_H -#define __DTS_MARVELL_PXA168_CLOCK_H - -/* fixed clocks and plls */ -#define PXA168_CLK_CLK32 1 -#define PXA168_CLK_VCTCXO 2 -#define PXA168_CLK_PLL1 3 -#define PXA168_CLK_PLL1_2 8 -#define PXA168_CLK_PLL1_4 9 -#define PXA168_CLK_PLL1_8 10 -#define PXA168_CLK_PLL1_16 11 -#define PXA168_CLK_PLL1_6 12 -#define PXA168_CLK_PLL1_12 13 -#define PXA168_CLK_PLL1_24 14 -#define PXA168_CLK_PLL1_48 15 -#define PXA168_CLK_PLL1_96 16 -#define PXA168_CLK_PLL1_13 17 -#define PXA168_CLK_PLL1_13_1_5 18 -#define PXA168_CLK_PLL1_2_1_5 19 -#define PXA168_CLK_PLL1_3_16 20 -#define PXA168_CLK_UART_PLL 27 - -/* apb periphrals */ -#define PXA168_CLK_TWSI0 60 -#define PXA168_CLK_TWSI1 61 -#define PXA168_CLK_TWSI2 62 -#define PXA168_CLK_TWSI3 63 -#define PXA168_CLK_GPIO 64 -#define PXA168_CLK_KPC 65 -#define PXA168_CLK_RTC 66 -#define PXA168_CLK_PWM0 67 -#define PXA168_CLK_PWM1 68 -#define PXA168_CLK_PWM2 69 -#define PXA168_CLK_PWM3 70 -#define PXA168_CLK_UART0 71 -#define PXA168_CLK_UART1 72 -#define PXA168_CLK_UART2 73 -#define PXA168_CLK_SSP0 74 -#define PXA168_CLK_SSP1 75 -#define PXA168_CLK_SSP2 76 -#define PXA168_CLK_SSP3 77 -#define PXA168_CLK_SSP4 78 - -/* axi periphrals */ -#define PXA168_CLK_DFC 100 -#define PXA168_CLK_SDH0 101 -#define PXA168_CLK_SDH1 102 -#define PXA168_CLK_SDH2 103 -#define PXA168_CLK_USB 104 -#define PXA168_CLK_SPH 105 -#define PXA168_CLK_DISP0 106 -#define PXA168_CLK_CCIC0 107 -#define PXA168_CLK_CCIC0_PHY 108 -#define PXA168_CLK_CCIC0_SPHY 109 - -#define PXA168_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h b/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h deleted file mode 100644 index 719cffb..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/marvell,pxa910.h +++ /dev/null @@ -1,54 +0,0 @@ -#ifndef __DTS_MARVELL_PXA910_CLOCK_H -#define __DTS_MARVELL_PXA910_CLOCK_H - -/* fixed clocks and plls */ -#define PXA910_CLK_CLK32 1 -#define PXA910_CLK_VCTCXO 2 -#define PXA910_CLK_PLL1 3 -#define PXA910_CLK_PLL1_2 8 -#define PXA910_CLK_PLL1_4 9 -#define PXA910_CLK_PLL1_8 10 -#define PXA910_CLK_PLL1_16 11 -#define PXA910_CLK_PLL1_6 12 -#define PXA910_CLK_PLL1_12 13 -#define PXA910_CLK_PLL1_24 14 -#define PXA910_CLK_PLL1_48 15 -#define PXA910_CLK_PLL1_96 16 -#define PXA910_CLK_PLL1_13 17 -#define PXA910_CLK_PLL1_13_1_5 18 -#define PXA910_CLK_PLL1_2_1_5 19 -#define PXA910_CLK_PLL1_3_16 20 -#define PXA910_CLK_UART_PLL 27 - -/* apb periphrals */ -#define PXA910_CLK_TWSI0 60 -#define PXA910_CLK_TWSI1 61 -#define PXA910_CLK_TWSI2 62 -#define PXA910_CLK_TWSI3 63 -#define PXA910_CLK_GPIO 64 -#define PXA910_CLK_KPC 65 -#define PXA910_CLK_RTC 66 -#define PXA910_CLK_PWM0 67 -#define PXA910_CLK_PWM1 68 -#define PXA910_CLK_PWM2 69 -#define PXA910_CLK_PWM3 70 -#define PXA910_CLK_UART0 71 -#define PXA910_CLK_UART1 72 -#define PXA910_CLK_UART2 73 -#define PXA910_CLK_SSP0 74 -#define PXA910_CLK_SSP1 75 - -/* axi periphrals */ -#define PXA910_CLK_DFC 100 -#define PXA910_CLK_SDH0 101 -#define PXA910_CLK_SDH1 102 -#define PXA910_CLK_SDH2 103 -#define PXA910_CLK_USB 104 -#define PXA910_CLK_SPH 105 -#define PXA910_CLK_DISP0 106 -#define PXA910_CLK_CCIC0 107 -#define PXA910_CLK_CCIC0_PHY 108 -#define PXA910_CLK_CCIC0_SPHY 109 - -#define PXA910_NR_CLKS 200 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h deleted file mode 100644 index 7b28b09..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77686.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77686 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77686_CLK_AP 0 -#define MAX77686_CLK_CP 1 -#define MAX77686_CLK_PMIC 2 - -/* Total number of clocks. */ -#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 997312e..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h deleted file mode 100644 index 2c0da56..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-apq8084.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H -#define _DT_BINDINGS_CLK_APQ_GCC_8084_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define GPLL1 2 -#define GPLL1_VOTE 3 -#define GPLL2 4 -#define GPLL2_VOTE 5 -#define GPLL3 6 -#define GPLL3_VOTE 7 -#define GPLL4 8 -#define GPLL4_VOTE 9 -#define CONFIG_NOC_CLK_SRC 10 -#define PERIPH_NOC_CLK_SRC 11 -#define SYSTEM_NOC_CLK_SRC 12 -#define BLSP_UART_SIM_CLK_SRC 13 -#define QDSS_TSCTR_CLK_SRC 14 -#define UFS_AXI_CLK_SRC 15 -#define RPM_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define BIMC_DDR_CLK_SRC 19 -#define USB30_MASTER_CLK_SRC 20 -#define USB30_SEC_MASTER_CLK_SRC 21 -#define USB_HSIC_AHB_CLK_SRC 22 -#define MMSS_BIMC_GFX_CLK_SRC 23 -#define QDSS_STM_CLK_SRC 24 -#define ACC_CLK_SRC 25 -#define SEC_CTRL_CLK_SRC 26 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38 -#define BLSP1_UART1_APPS_CLK_SRC 39 -#define BLSP1_UART2_APPS_CLK_SRC 40 -#define BLSP1_UART3_APPS_CLK_SRC 41 -#define BLSP1_UART4_APPS_CLK_SRC 42 -#define BLSP1_UART5_APPS_CLK_SRC 43 -#define BLSP1_UART6_APPS_CLK_SRC 44 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56 -#define BLSP2_UART1_APPS_CLK_SRC 57 -#define BLSP2_UART2_APPS_CLK_SRC 58 -#define BLSP2_UART3_APPS_CLK_SRC 59 -#define BLSP2_UART4_APPS_CLK_SRC 60 -#define BLSP2_UART5_APPS_CLK_SRC 61 -#define BLSP2_UART6_APPS_CLK_SRC 62 -#define CE1_CLK_SRC 63 -#define CE2_CLK_SRC 64 -#define CE3_CLK_SRC 65 -#define GP1_CLK_SRC 66 -#define GP2_CLK_SRC 67 -#define GP3_CLK_SRC 68 -#define PDM2_CLK_SRC 69 -#define QDSS_TRACECLKIN_CLK_SRC 70 -#define RBCPR_CLK_SRC 71 -#define SATA_ASIC0_CLK_SRC 72 -#define SATA_PMALIVE_CLK_SRC 73 -#define SATA_RX_CLK_SRC 74 -#define SATA_RX_OOB_CLK_SRC 75 -#define SDCC1_APPS_CLK_SRC 76 -#define SDCC2_APPS_CLK_SRC 77 -#define SDCC3_APPS_CLK_SRC 78 -#define SDCC4_APPS_CLK_SRC 79 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80 -#define SPMI_AHB_CLK_SRC 81 -#define SPMI_SER_CLK_SRC 82 -#define TSIF_REF_CLK_SRC 83 -#define USB30_MOCK_UTMI_CLK_SRC 84 -#define USB30_SEC_MOCK_UTMI_CLK_SRC 85 -#define USB_HS_SYSTEM_CLK_SRC 86 -#define USB_HSIC_CLK_SRC 87 -#define USB_HSIC_IO_CAL_CLK_SRC 88 -#define USB_HSIC_MOCK_UTMI_CLK_SRC 89 -#define USB_HSIC_SYSTEM_CLK_SRC 90 -#define GCC_BAM_DMA_AHB_CLK 91 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92 -#define DDR_CLK_SRC 93 -#define GCC_BIMC_CFG_AHB_CLK 94 -#define GCC_BIMC_CLK 95 -#define GCC_BIMC_KPSS_AXI_CLK 96 -#define GCC_BIMC_SLEEP_CLK 97 -#define GCC_BIMC_SYSNOC_AXI_CLK 98 -#define GCC_BIMC_XO_CLK 99 -#define GCC_BLSP1_AHB_CLK 100 -#define GCC_BLSP1_SLEEP_CLK 101 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113 -#define GCC_BLSP1_UART1_APPS_CLK 114 -#define GCC_BLSP1_UART1_SIM_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_UART2_SIM_CLK 117 -#define GCC_BLSP1_UART3_APPS_CLK 118 -#define GCC_BLSP1_UART3_SIM_CLK 119 -#define GCC_BLSP1_UART4_APPS_CLK 120 -#define GCC_BLSP1_UART4_SIM_CLK 121 -#define GCC_BLSP1_UART5_APPS_CLK 122 -#define GCC_BLSP1_UART5_SIM_CLK 123 -#define GCC_BLSP1_UART6_APPS_CLK 124 -#define GCC_BLSP1_UART6_SIM_CLK 125 -#define GCC_BLSP2_AHB_CLK 126 -#define GCC_BLSP2_SLEEP_CLK 127 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139 -#define GCC_BLSP2_UART1_APPS_CLK 140 -#define GCC_BLSP2_UART1_SIM_CLK 141 -#define GCC_BLSP2_UART2_APPS_CLK 142 -#define GCC_BLSP2_UART2_SIM_CLK 143 -#define GCC_BLSP2_UART3_APPS_CLK 144 -#define GCC_BLSP2_UART3_SIM_CLK 145 -#define GCC_BLSP2_UART4_APPS_CLK 146 -#define GCC_BLSP2_UART4_SIM_CLK 147 -#define GCC_BLSP2_UART5_APPS_CLK 148 -#define GCC_BLSP2_UART5_SIM_CLK 149 -#define GCC_BLSP2_UART6_APPS_CLK 150 -#define GCC_BLSP2_UART6_SIM_CLK 151 -#define GCC_BOOT_ROM_AHB_CLK 152 -#define GCC_CE1_AHB_CLK 153 -#define GCC_CE1_AXI_CLK 154 -#define GCC_CE1_CLK 155 -#define GCC_CE2_AHB_CLK 156 -#define GCC_CE2_AXI_CLK 157 -#define GCC_CE2_CLK 158 -#define GCC_CE3_AHB_CLK 159 -#define GCC_CE3_AXI_CLK 160 -#define GCC_CE3_CLK 161 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168 -#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169 -#define GCC_CFG_NOC_AHB_CLK 170 -#define GCC_CFG_NOC_DDR_CFG_CLK 171 -#define GCC_CFG_NOC_RPM_AHB_CLK 172 -#define GCC_COPSS_SMMU_AHB_CLK 173 -#define GCC_COPSS_SMMU_AXI_CLK 174 -#define GCC_DCD_XO_CLK 175 -#define GCC_BIMC_DDR_CH0_CLK 176 -#define GCC_BIMC_DDR_CH1_CLK 177 -#define GCC_BIMC_DDR_CPLL0_CLK 178 -#define GCC_BIMC_DDR_CPLL1_CLK 179 -#define GCC_BIMC_GFX_CLK 180 -#define GCC_DDR_DIM_CFG_CLK 181 -#define GCC_DDR_DIM_SLEEP_CLK 182 -#define GCC_DEHR_CLK 183 -#define GCC_AHB_CLK 184 -#define GCC_IM_SLEEP_CLK 185 -#define GCC_XO_CLK 186 -#define GCC_XO_DIV4_CLK 187 -#define GCC_GP1_CLK 188 -#define GCC_GP2_CLK 189 -#define GCC_GP3_CLK 190 -#define GCC_IMEM_AXI_CLK 191 -#define GCC_IMEM_CFG_AHB_CLK 192 -#define GCC_KPSS_AHB_CLK 193 -#define GCC_KPSS_AXI_CLK 194 -#define GCC_LPASS_MPORT_AXI_CLK 195 -#define GCC_LPASS_Q6_AXI_CLK 196 -#define GCC_LPASS_SWAY_CLK 197 -#define GCC_MMSS_BIMC_GFX_CLK 198 -#define GCC_MMSS_NOC_AT_CLK 199 -#define GCC_MMSS_NOC_CFG_AHB_CLK 200 -#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 202 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 203 -#define GCC_MPM_AHB_CLK 204 -#define GCC_MSG_RAM_AHB_CLK 205 -#define GCC_NOC_CONF_XPU_AHB_CLK 206 -#define GCC_PDM2_CLK 207 -#define GCC_PDM_AHB_CLK 208 -#define GCC_PDM_XO4_CLK 209 -#define GCC_PERIPH_NOC_AHB_CLK 210 -#define GCC_PERIPH_NOC_AT_CLK 211 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 212 -#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214 -#define GCC_PERIPH_XPU_AHB_CLK 215 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220 -#define GCC_PRNG_AHB_CLK 221 -#define GCC_QDSS_AT_CLK 222 -#define GCC_QDSS_CFG_AHB_CLK 223 -#define GCC_QDSS_DAP_AHB_CLK 224 -#define GCC_QDSS_DAP_CLK 225 -#define GCC_QDSS_ETR_USB_CLK 226 -#define GCC_QDSS_STM_CLK 227 -#define GCC_QDSS_TRACECLKIN_CLK 228 -#define GCC_QDSS_TSCTR_DIV16_CLK 229 -#define GCC_QDSS_TSCTR_DIV2_CLK 230 -#define GCC_QDSS_TSCTR_DIV3_CLK 231 -#define GCC_QDSS_TSCTR_DIV4_CLK 232 -#define GCC_QDSS_TSCTR_DIV8_CLK 233 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234 -#define GCC_RBCPR_AHB_CLK 235 -#define GCC_RBCPR_CLK 236 -#define GCC_RPM_BUS_AHB_CLK 237 -#define GCC_RPM_PROC_HCLK 238 -#define GCC_RPM_SLEEP_CLK 239 -#define GCC_RPM_TIMER_CLK 240 -#define GCC_SATA_ASIC0_CLK 241 -#define GCC_SATA_AXI_CLK 242 -#define GCC_SATA_CFG_AHB_CLK 243 -#define GCC_SATA_PMALIVE_CLK 244 -#define GCC_SATA_RX_CLK 245 -#define GCC_SATA_RX_OOB_CLK 246 -#define GCC_SDCC1_AHB_CLK 247 -#define GCC_SDCC1_APPS_CLK 248 -#define GCC_SDCC1_CDCCAL_FF_CLK 249 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250 -#define GCC_SDCC2_AHB_CLK 251 -#define GCC_SDCC2_APPS_CLK 252 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253 -#define GCC_SDCC3_AHB_CLK 254 -#define GCC_SDCC3_APPS_CLK 255 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256 -#define GCC_SDCC4_AHB_CLK 257 -#define GCC_SDCC4_APPS_CLK 258 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259 -#define GCC_SEC_CTRL_ACC_CLK 260 -#define GCC_SEC_CTRL_AHB_CLK 261 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262 -#define GCC_SEC_CTRL_CLK 263 -#define GCC_SEC_CTRL_SENSE_CLK 264 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265 -#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266 -#define GCC_SPDM_BIMC_CY_CLK 267 -#define GCC_SPDM_CFG_AHB_CLK 268 -#define GCC_SPDM_DEBUG_CY_CLK 269 -#define GCC_SPDM_FF_CLK 270 -#define GCC_SPDM_MSTR_AHB_CLK 271 -#define GCC_SPDM_PNOC_CY_CLK 272 -#define GCC_SPDM_RPM_CY_CLK 273 -#define GCC_SPDM_SNOC_CY_CLK 274 -#define GCC_SPMI_AHB_CLK 275 -#define GCC_SPMI_CNOC_AHB_CLK 276 -#define GCC_SPMI_SER_CLK 277 -#define GCC_SPSS_AHB_CLK 278 -#define GCC_SNOC_CNOC_AHB_CLK 279 -#define GCC_SNOC_PNOC_AHB_CLK 280 -#define GCC_SYS_NOC_AT_CLK 281 -#define GCC_SYS_NOC_AXI_CLK 282 -#define GCC_SYS_NOC_KPSS_AHB_CLK 283 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284 -#define GCC_SYS_NOC_UFS_AXI_CLK 285 -#define GCC_SYS_NOC_USB3_AXI_CLK 286 -#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287 -#define GCC_TCSR_AHB_CLK 288 -#define GCC_TLMM_AHB_CLK 289 -#define GCC_TLMM_CLK 290 -#define GCC_TSIF_AHB_CLK 291 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292 -#define GCC_TSIF_REF_CLK 293 -#define GCC_UFS_AHB_CLK 294 -#define GCC_UFS_AXI_CLK 295 -#define GCC_UFS_RX_CFG_CLK 296 -#define GCC_UFS_RX_SYMBOL_0_CLK 297 -#define GCC_UFS_RX_SYMBOL_1_CLK 298 -#define GCC_UFS_TX_CFG_CLK 299 -#define GCC_UFS_TX_SYMBOL_0_CLK 300 -#define GCC_UFS_TX_SYMBOL_1_CLK 301 -#define GCC_USB2A_PHY_SLEEP_CLK 302 -#define GCC_USB2B_PHY_SLEEP_CLK 303 -#define GCC_USB30_MASTER_CLK 304 -#define GCC_USB30_MOCK_UTMI_CLK 305 -#define GCC_USB30_SLEEP_CLK 306 -#define GCC_USB30_SEC_MASTER_CLK 307 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 308 -#define GCC_USB30_SEC_SLEEP_CLK 309 -#define GCC_USB_HS_AHB_CLK 310 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311 -#define GCC_USB_HS_SYSTEM_CLK 312 -#define GCC_USB_HSIC_AHB_CLK 313 -#define GCC_USB_HSIC_CLK 314 -#define GCC_USB_HSIC_IO_CAL_CLK 315 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316 -#define GCC_USB_HSIC_MOCK_UTMI_CLK 317 -#define GCC_USB_HSIC_SYSTEM_CLK 318 -#define PCIE_0_AUX_CLK_SRC 319 -#define PCIE_0_PIPE_CLK_SRC 320 -#define PCIE_1_AUX_CLK_SRC 321 -#define PCIE_1_PIPE_CLK_SRC 322 -#define GCC_PCIE_0_AUX_CLK 323 -#define GCC_PCIE_0_CFG_AHB_CLK 324 -#define GCC_PCIE_0_MSTR_AXI_CLK 325 -#define GCC_PCIE_0_PIPE_CLK 326 -#define GCC_PCIE_0_SLV_AXI_CLK 327 -#define GCC_PCIE_1_AUX_CLK 328 -#define GCC_PCIE_1_CFG_AHB_CLK 329 -#define GCC_PCIE_1_MSTR_AXI_CLK 330 -#define GCC_PCIE_1_PIPE_CLK 331 -#define GCC_PCIE_1_SLV_AXI_CLK 332 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h deleted file mode 100644 index 04fb29a..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H -#define _DT_BINDINGS_CLK_GCC_IPQ806X_H - -#define AFAB_CLK_SRC 0 -#define QDSS_STM_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define AFAB_CORE_CLK 4 -#define SCSS_XO_SRC_CLK 5 -#define AFAB_EBI1_CH0_A_CLK 6 -#define AFAB_EBI1_CH1_A_CLK 7 -#define AFAB_AXI_S0_FCLK 8 -#define AFAB_AXI_S1_FCLK 9 -#define AFAB_AXI_S2_FCLK 10 -#define AFAB_AXI_S3_FCLK 11 -#define AFAB_AXI_S4_FCLK 12 -#define SFAB_CORE_CLK 13 -#define SFAB_AXI_S0_FCLK 14 -#define SFAB_AXI_S1_FCLK 15 -#define SFAB_AXI_S2_FCLK 16 -#define SFAB_AXI_S3_FCLK 17 -#define SFAB_AXI_S4_FCLK 18 -#define SFAB_AXI_S5_FCLK 19 -#define SFAB_AHB_S0_FCLK 20 -#define SFAB_AHB_S1_FCLK 21 -#define SFAB_AHB_S2_FCLK 22 -#define SFAB_AHB_S3_FCLK 23 -#define SFAB_AHB_S4_FCLK 24 -#define SFAB_AHB_S5_FCLK 25 -#define SFAB_AHB_S6_FCLK 26 -#define SFAB_AHB_S7_FCLK 27 -#define QDSS_AT_CLK_SRC 28 -#define QDSS_AT_CLK 29 -#define QDSS_TRACECLKIN_CLK_SRC 30 -#define QDSS_TRACECLKIN_CLK 31 -#define QDSS_TSCTR_CLK_SRC 32 -#define QDSS_TSCTR_CLK 33 -#define SFAB_ADM0_M0_A_CLK 34 -#define SFAB_ADM0_M1_A_CLK 35 -#define SFAB_ADM0_M2_H_CLK 36 -#define ADM0_CLK 37 -#define ADM0_PBUS_CLK 38 -#define IMEM0_A_CLK 39 -#define QDSS_H_CLK 40 -#define PCIE_A_CLK 41 -#define PCIE_AUX_CLK 42 -#define PCIE_H_CLK 43 -#define PCIE_PHY_CLK 44 -#define SFAB_CLK_SRC 45 -#define SFAB_LPASS_Q6_A_CLK 46 -#define SFAB_AFAB_M_A_CLK 47 -#define AFAB_SFAB_M0_A_CLK 48 -#define AFAB_SFAB_M1_A_CLK 49 -#define SFAB_SATA_S_H_CLK 50 -#define DFAB_CLK_SRC 51 -#define DFAB_CLK 52 -#define SFAB_DFAB_M_A_CLK 53 -#define DFAB_SFAB_M_A_CLK 54 -#define DFAB_SWAY0_H_CLK 55 -#define DFAB_SWAY1_H_CLK 56 -#define DFAB_ARB0_H_CLK 57 -#define DFAB_ARB1_H_CLK 58 -#define PPSS_H_CLK 59 -#define PPSS_PROC_CLK 60 -#define PPSS_TIMER0_CLK 61 -#define PPSS_TIMER1_CLK 62 -#define PMEM_A_CLK 63 -#define DMA_BAM_H_CLK 64 -#define SIC_H_CLK 65 -#define SPS_TIC_H_CLK 66 -#define CFPB_2X_CLK_SRC 67 -#define CFPB_CLK 68 -#define CFPB0_H_CLK 69 -#define CFPB1_H_CLK 70 -#define CFPB2_H_CLK 71 -#define SFAB_CFPB_M_H_CLK 72 -#define CFPB_MASTER_H_CLK 73 -#define SFAB_CFPB_S_H_CLK 74 -#define CFPB_SPLITTER_H_CLK 75 -#define TSIF_H_CLK 76 -#define TSIF_INACTIVITY_TIMERS_CLK 77 -#define TSIF_REF_SRC 78 -#define TSIF_REF_CLK 79 -#define CE1_H_CLK 80 -#define CE1_CORE_CLK 81 -#define CE1_SLEEP_CLK 82 -#define CE2_H_CLK 83 -#define CE2_CORE_CLK 84 -#define SFPB_H_CLK_SRC 85 -#define SFPB_H_CLK 86 -#define SFAB_SFPB_M_H_CLK 87 -#define SFAB_SFPB_S_H_CLK 88 -#define RPM_PROC_CLK 89 -#define RPM_BUS_H_CLK 90 -#define RPM_SLEEP_CLK 91 -#define RPM_TIMER_CLK 92 -#define RPM_MSG_RAM_H_CLK 93 -#define PMIC_ARB0_H_CLK 94 -#define PMIC_ARB1_H_CLK 95 -#define PMIC_SSBI2_SRC 96 -#define PMIC_SSBI2_CLK 97 -#define SDC1_H_CLK 98 -#define SDC2_H_CLK 99 -#define SDC3_H_CLK 100 -#define SDC4_H_CLK 101 -#define SDC1_SRC 102 -#define SDC1_CLK 103 -#define SDC2_SRC 104 -#define SDC2_CLK 105 -#define SDC3_SRC 106 -#define SDC3_CLK 107 -#define SDC4_SRC 108 -#define SDC4_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HSIC_H_CLK 113 -#define USB_HSIC_XCVR_SRC 114 -#define USB_HSIC_XCVR_CLK 115 -#define USB_HSIC_SYSTEM_CLK_SRC 116 -#define USB_HSIC_SYSTEM_CLK 117 -#define CFPB0_C0_H_CLK 118 -#define CFPB0_D0_H_CLK 119 -#define CFPB0_C1_H_CLK 120 -#define CFPB0_D1_H_CLK 121 -#define USB_FS1_H_CLK 122 -#define USB_FS1_XCVR_SRC 123 -#define USB_FS1_XCVR_CLK 124 -#define USB_FS1_SYSTEM_CLK 125 -#define GSBI_COMMON_SIM_SRC 126 -#define GSBI1_H_CLK 127 -#define GSBI2_H_CLK 128 -#define GSBI3_H_CLK 129 -#define GSBI4_H_CLK 130 -#define GSBI5_H_CLK 131 -#define GSBI6_H_CLK 132 -#define GSBI7_H_CLK 133 -#define GSBI1_QUP_SRC 134 -#define GSBI1_QUP_CLK 135 -#define GSBI2_QUP_SRC 136 -#define GSBI2_QUP_CLK 137 -#define GSBI3_QUP_SRC 138 -#define GSBI3_QUP_CLK 139 -#define GSBI4_QUP_SRC 140 -#define GSBI4_QUP_CLK 141 -#define GSBI5_QUP_SRC 142 -#define GSBI5_QUP_CLK 143 -#define GSBI6_QUP_SRC 144 -#define GSBI6_QUP_CLK 145 -#define GSBI7_QUP_SRC 146 -#define GSBI7_QUP_CLK 147 -#define GSBI1_UART_SRC 148 -#define GSBI1_UART_CLK 149 -#define GSBI2_UART_SRC 150 -#define GSBI2_UART_CLK 151 -#define GSBI3_UART_SRC 152 -#define GSBI3_UART_CLK 153 -#define GSBI4_UART_SRC 154 -#define GSBI4_UART_CLK 155 -#define GSBI5_UART_SRC 156 -#define GSBI5_UART_CLK 157 -#define GSBI6_UART_SRC 158 -#define GSBI6_UART_CLK 159 -#define GSBI7_UART_SRC 160 -#define GSBI7_UART_CLK 161 -#define GSBI1_SIM_CLK 162 -#define GSBI2_SIM_CLK 163 -#define GSBI3_SIM_CLK 164 -#define GSBI4_SIM_CLK 165 -#define GSBI5_SIM_CLK 166 -#define GSBI6_SIM_CLK 167 -#define GSBI7_SIM_CLK 168 -#define USB_HSIC_HSIC_CLK_SRC 169 -#define USB_HSIC_HSIC_CLK 170 -#define USB_HSIC_HSIO_CAL_CLK 171 -#define SPDM_CFG_H_CLK 172 -#define SPDM_MSTR_H_CLK 173 -#define SPDM_FF_CLK_SRC 174 -#define SPDM_FF_CLK 175 -#define SEC_CTRL_CLK 176 -#define SEC_CTRL_ACC_CLK_SRC 177 -#define SEC_CTRL_ACC_CLK 178 -#define TLMM_H_CLK 179 -#define TLMM_CLK 180 -#define SATA_H_CLK 181 -#define SATA_CLK_SRC 182 -#define SATA_RXOOB_CLK 183 -#define SATA_PMALIVE_CLK 184 -#define SATA_PHY_REF_CLK 185 -#define SATA_A_CLK 186 -#define SATA_PHY_CFG_CLK 187 -#define TSSC_CLK_SRC 188 -#define TSSC_CLK 189 -#define PDM_SRC 190 -#define PDM_CLK 191 -#define GP0_SRC 192 -#define GP0_CLK 193 -#define GP1_SRC 194 -#define GP1_CLK 195 -#define GP2_SRC 196 -#define GP2_CLK 197 -#define MPM_CLK 198 -#define EBI1_CLK_SRC 199 -#define EBI1_CH0_CLK 200 -#define EBI1_CH1_CLK 201 -#define EBI1_2X_CLK 202 -#define EBI1_CH0_DQ_CLK 203 -#define EBI1_CH1_DQ_CLK 204 -#define EBI1_CH0_CA_CLK 205 -#define EBI1_CH1_CA_CLK 206 -#define EBI1_XO_CLK 207 -#define SFAB_SMPSS_S_H_CLK 208 -#define PRNG_SRC 209 -#define PRNG_CLK 210 -#define PXO_SRC 211 -#define SPDM_CY_PORT0_CLK 212 -#define SPDM_CY_PORT1_CLK 213 -#define SPDM_CY_PORT2_CLK 214 -#define SPDM_CY_PORT3_CLK 215 -#define SPDM_CY_PORT4_CLK 216 -#define SPDM_CY_PORT5_CLK 217 -#define SPDM_CY_PORT6_CLK 218 -#define SPDM_CY_PORT7_CLK 219 -#define PLL0 220 -#define PLL0_VOTE 221 -#define PLL3 222 -#define PLL3_VOTE 223 -#define PLL4_VOTE 225 -#define PLL8 226 -#define PLL8_VOTE 227 -#define PLL9 228 -#define PLL10 229 -#define PLL11 230 -#define PLL12 231 -#define PLL14 232 -#define PLL14_VOTE 233 -#define PLL18 234 -#define CE5_SRC 235 -#define CE5_H_CLK 236 -#define CE5_CORE_CLK 237 -#define CE3_SLEEP_CLK 238 -#define SFAB_AHB_S8_FCLK 239 -#define SPDM_CY_PORT8_CLK 246 -#define PCIE_ALT_REF_SRC 247 -#define PCIE_ALT_REF_CLK 248 -#define PCIE_1_A_CLK 249 -#define PCIE_1_AUX_CLK 250 -#define PCIE_1_H_CLK 251 -#define PCIE_1_PHY_CLK 252 -#define PCIE_1_ALT_REF_SRC 253 -#define PCIE_1_ALT_REF_CLK 254 -#define PCIE_2_A_CLK 255 -#define PCIE_2_AUX_CLK 256 -#define PCIE_2_H_CLK 257 -#define PCIE_2_PHY_CLK 258 -#define PCIE_2_ALT_REF_SRC 259 -#define PCIE_2_ALT_REF_CLK 260 -#define EBI2_CLK 261 -#define USB30_SLEEP_CLK 262 -#define USB30_UTMI_SRC 263 -#define USB30_0_UTMI_CLK 264 -#define USB30_1_UTMI_CLK 265 -#define USB30_MASTER_SRC 266 -#define USB30_0_MASTER_CLK 267 -#define USB30_1_MASTER_CLK 268 -#define GMAC_CORE1_CLK_SRC 269 -#define GMAC_CORE2_CLK_SRC 270 -#define GMAC_CORE3_CLK_SRC 271 -#define GMAC_CORE4_CLK_SRC 272 -#define GMAC_CORE1_CLK 273 -#define GMAC_CORE2_CLK 274 -#define GMAC_CORE3_CLK 275 -#define GMAC_CORE4_CLK 276 -#define UBI32_CORE1_CLK_SRC 277 -#define UBI32_CORE2_CLK_SRC 278 -#define UBI32_CORE1_CLK 279 -#define UBI32_CORE2_CLK 280 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h deleted file mode 100644 index 67665f6..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8660.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H -#define _DT_BINDINGS_CLK_MSM_GCC_8660_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SCSS_A_CLK 2 -#define SCSS_H_CLK 3 -#define SCSS_XO_SRC_CLK 4 -#define AFAB_EBI1_CH0_A_CLK 5 -#define AFAB_EBI1_CH1_A_CLK 6 -#define AFAB_AXI_S0_FCLK 7 -#define AFAB_AXI_S1_FCLK 8 -#define AFAB_AXI_S2_FCLK 9 -#define AFAB_AXI_S3_FCLK 10 -#define AFAB_AXI_S4_FCLK 11 -#define SFAB_CORE_CLK 12 -#define SFAB_AXI_S0_FCLK 13 -#define SFAB_AXI_S1_FCLK 14 -#define SFAB_AXI_S2_FCLK 15 -#define SFAB_AXI_S3_FCLK 16 -#define SFAB_AXI_S4_FCLK 17 -#define SFAB_AHB_S0_FCLK 18 -#define SFAB_AHB_S1_FCLK 19 -#define SFAB_AHB_S2_FCLK 20 -#define SFAB_AHB_S3_FCLK 21 -#define SFAB_AHB_S4_FCLK 22 -#define SFAB_AHB_S5_FCLK 23 -#define SFAB_AHB_S6_FCLK 24 -#define SFAB_ADM0_M0_A_CLK 25 -#define SFAB_ADM0_M1_A_CLK 26 -#define SFAB_ADM0_M2_A_CLK 27 -#define ADM0_CLK 28 -#define ADM0_PBUS_CLK 29 -#define SFAB_ADM1_M0_A_CLK 30 -#define SFAB_ADM1_M1_A_CLK 31 -#define SFAB_ADM1_M2_A_CLK 32 -#define MMFAB_ADM1_M3_A_CLK 33 -#define ADM1_CLK 34 -#define ADM1_PBUS_CLK 35 -#define IMEM0_A_CLK 36 -#define MAHB0_CLK 37 -#define SFAB_LPASS_Q6_A_CLK 38 -#define SFAB_AFAB_M_A_CLK 39 -#define AFAB_SFAB_M0_A_CLK 40 -#define AFAB_SFAB_M1_A_CLK 41 -#define DFAB_CLK_SRC 42 -#define DFAB_CLK 43 -#define DFAB_CORE_CLK 44 -#define SFAB_DFAB_M_A_CLK 45 -#define DFAB_SFAB_M_A_CLK 46 -#define DFAB_SWAY0_H_CLK 47 -#define DFAB_SWAY1_H_CLK 48 -#define DFAB_ARB0_H_CLK 49 -#define DFAB_ARB1_H_CLK 50 -#define PPSS_H_CLK 51 -#define PPSS_PROC_CLK 52 -#define PPSS_TIMER0_CLK 53 -#define PPSS_TIMER1_CLK 54 -#define PMEM_A_CLK 55 -#define DMA_BAM_H_CLK 56 -#define SIC_H_CLK 57 -#define SPS_TIC_H_CLK 58 -#define SLIMBUS_H_CLK 59 -#define SLIMBUS_XO_SRC_CLK 60 -#define CFPB_2X_CLK_SRC 61 -#define CFPB_CLK 62 -#define CFPB0_H_CLK 63 -#define CFPB1_H_CLK 64 -#define CFPB2_H_CLK 65 -#define EBI2_2X_CLK 66 -#define EBI2_CLK 67 -#define SFAB_CFPB_M_H_CLK 68 -#define CFPB_MASTER_H_CLK 69 -#define SFAB_CFPB_S_HCLK 70 -#define CFPB_SPLITTER_H_CLK 71 -#define TSIF_H_CLK 72 -#define TSIF_INACTIVITY_TIMERS_CLK 73 -#define TSIF_REF_SRC 74 -#define TSIF_REF_CLK 75 -#define CE1_H_CLK 76 -#define CE2_H_CLK 77 -#define SFPB_H_CLK_SRC 78 -#define SFPB_H_CLK 79 -#define SFAB_SFPB_M_H_CLK 80 -#define SFAB_SFPB_S_H_CLK 81 -#define RPM_PROC_CLK 82 -#define RPM_BUS_H_CLK 83 -#define RPM_SLEEP_CLK 84 -#define RPM_TIMER_CLK 85 -#define MODEM_AHB1_H_CLK 86 -#define MODEM_AHB2_H_CLK 87 -#define RPM_MSG_RAM_H_CLK 88 -#define SC_H_CLK 89 -#define SC_A_CLK 90 -#define PMIC_ARB0_H_CLK 91 -#define PMIC_ARB1_H_CLK 92 -#define PMIC_SSBI2_SRC 93 -#define PMIC_SSBI2_CLK 94 -#define SDC1_H_CLK 95 -#define SDC2_H_CLK 96 -#define SDC3_H_CLK 97 -#define SDC4_H_CLK 98 -#define SDC5_H_CLK 99 -#define SDC1_SRC 100 -#define SDC2_SRC 101 -#define SDC3_SRC 102 -#define SDC4_SRC 103 -#define SDC5_SRC 104 -#define SDC1_CLK 105 -#define SDC2_CLK 106 -#define SDC3_CLK 107 -#define SDC4_CLK 108 -#define SDC5_CLK 109 -#define USB_HS1_H_CLK 110 -#define USB_HS1_XCVR_SRC 111 -#define USB_HS1_XCVR_CLK 112 -#define USB_HS2_H_CLK 113 -#define USB_HS2_XCVR_SRC 114 -#define USB_HS2_XCVR_CLK 115 -#define USB_FS1_H_CLK 116 -#define USB_FS1_XCVR_FS_SRC 117 -#define USB_FS1_XCVR_FS_CLK 118 -#define USB_FS1_SYSTEM_CLK 119 -#define USB_FS2_H_CLK 120 -#define USB_FS2_XCVR_FS_SRC 121 -#define USB_FS2_XCVR_FS_CLK 122 -#define USB_FS2_SYSTEM_CLK 123 -#define GSBI_COMMON_SIM_SRC 124 -#define GSBI1_H_CLK 125 -#define GSBI2_H_CLK 126 -#define GSBI3_H_CLK 127 -#define GSBI4_H_CLK 128 -#define GSBI5_H_CLK 129 -#define GSBI6_H_CLK 130 -#define GSBI7_H_CLK 131 -#define GSBI8_H_CLK 132 -#define GSBI9_H_CLK 133 -#define GSBI10_H_CLK 134 -#define GSBI11_H_CLK 135 -#define GSBI12_H_CLK 136 -#define GSBI1_UART_SRC 137 -#define GSBI1_UART_CLK 138 -#define GSBI2_UART_SRC 139 -#define GSBI2_UART_CLK 140 -#define GSBI3_UART_SRC 141 -#define GSBI3_UART_CLK 142 -#define GSBI4_UART_SRC 143 -#define GSBI4_UART_CLK 144 -#define GSBI5_UART_SRC 145 -#define GSBI5_UART_CLK 146 -#define GSBI6_UART_SRC 147 -#define GSBI6_UART_CLK 148 -#define GSBI7_UART_SRC 149 -#define GSBI7_UART_CLK 150 -#define GSBI8_UART_SRC 151 -#define GSBI8_UART_CLK 152 -#define GSBI9_UART_SRC 153 -#define GSBI9_UART_CLK 154 -#define GSBI10_UART_SRC 155 -#define GSBI10_UART_CLK 156 -#define GSBI11_UART_SRC 157 -#define GSBI11_UART_CLK 158 -#define GSBI12_UART_SRC 159 -#define GSBI12_UART_CLK 160 -#define GSBI1_QUP_SRC 161 -#define GSBI1_QUP_CLK 162 -#define GSBI2_QUP_SRC 163 -#define GSBI2_QUP_CLK 164 -#define GSBI3_QUP_SRC 165 -#define GSBI3_QUP_CLK 166 -#define GSBI4_QUP_SRC 167 -#define GSBI4_QUP_CLK 168 -#define GSBI5_QUP_SRC 169 -#define GSBI5_QUP_CLK 170 -#define GSBI6_QUP_SRC 171 -#define GSBI6_QUP_CLK 172 -#define GSBI7_QUP_SRC 173 -#define GSBI7_QUP_CLK 174 -#define GSBI8_QUP_SRC 175 -#define GSBI8_QUP_CLK 176 -#define GSBI9_QUP_SRC 177 -#define GSBI9_QUP_CLK 178 -#define GSBI10_QUP_SRC 179 -#define GSBI10_QUP_CLK 180 -#define GSBI11_QUP_SRC 181 -#define GSBI11_QUP_CLK 182 -#define GSBI12_QUP_SRC 183 -#define GSBI12_QUP_CLK 184 -#define GSBI1_SIM_CLK 185 -#define GSBI2_SIM_CLK 186 -#define GSBI3_SIM_CLK 187 -#define GSBI4_SIM_CLK 188 -#define GSBI5_SIM_CLK 189 -#define GSBI6_SIM_CLK 190 -#define GSBI7_SIM_CLK 191 -#define GSBI8_SIM_CLK 192 -#define GSBI9_SIM_CLK 193 -#define GSBI10_SIM_CLK 194 -#define GSBI11_SIM_CLK 195 -#define GSBI12_SIM_CLK 196 -#define SPDM_CFG_H_CLK 197 -#define SPDM_MSTR_H_CLK 198 -#define SPDM_FF_CLK_SRC 199 -#define SPDM_FF_CLK 200 -#define SEC_CTRL_CLK 201 -#define SEC_CTRL_ACC_CLK_SRC 202 -#define SEC_CTRL_ACC_CLK 203 -#define TLMM_H_CLK 204 -#define TLMM_CLK 205 -#define MARM_CLK_SRC 206 -#define MARM_CLK 207 -#define MAHB1_SRC 208 -#define MAHB1_CLK 209 -#define SFAB_MSS_S_H_CLK 210 -#define MAHB2_SRC 211 -#define MAHB2_CLK 212 -#define MSS_MODEM_CLK_SRC 213 -#define MSS_MODEM_CXO_CLK 214 -#define MSS_SLP_CLK 215 -#define MSS_SYS_REF_CLK 216 -#define TSSC_CLK_SRC 217 -#define TSSC_CLK 218 -#define PDM_SRC 219 -#define PDM_CLK 220 -#define GP0_SRC 221 -#define GP0_CLK 222 -#define GP1_SRC 223 -#define GP1_CLK 224 -#define GP2_SRC 225 -#define GP2_CLK 226 -#define PMEM_CLK 227 -#define MPM_CLK 228 -#define EBI1_ASFAB_SRC 229 -#define EBI1_CLK_SRC 230 -#define EBI1_CH0_CLK 231 -#define EBI1_CH1_CLK 232 -#define SFAB_SMPSS_S_H_CLK 233 -#define PRNG_SRC 234 -#define PRNG_CLK 235 -#define PXO_SRC 236 -#define LPASS_CXO_CLK 237 -#define LPASS_PXO_CLK 238 -#define SPDM_CY_PORT0_CLK 239 -#define SPDM_CY_PORT1_CLK 240 -#define SPDM_CY_PORT2_CLK 241 -#define SPDM_CY_PORT3_CLK 242 -#define SPDM_CY_PORT4_CLK 243 -#define SPDM_CY_PORT5_CLK 244 -#define SPDM_CY_PORT6_CLK 245 -#define SPDM_CY_PORT7_CLK 246 -#define PLL0 247 -#define PLL0_VOTE 248 -#define PLL5 249 -#define PLL6 250 -#define PLL6_VOTE 251 -#define PLL8 252 -#define PLL8_VOTE 253 -#define PLL9 254 -#define PLL10 255 -#define PLL11 256 -#define PLL12 257 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h deleted file mode 100644 index 7d20eed..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H -#define _DT_BINDINGS_CLK_MSM_GCC_8960_H - -#define AFAB_CLK_SRC 0 -#define AFAB_CORE_CLK 1 -#define SFAB_MSS_Q6_SW_A_CLK 2 -#define SFAB_MSS_Q6_FW_A_CLK 3 -#define QDSS_STM_CLK 4 -#define SCSS_A_CLK 5 -#define SCSS_H_CLK 6 -#define SCSS_XO_SRC_CLK 7 -#define AFAB_EBI1_CH0_A_CLK 8 -#define AFAB_EBI1_CH1_A_CLK 9 -#define AFAB_AXI_S0_FCLK 10 -#define AFAB_AXI_S1_FCLK 11 -#define AFAB_AXI_S2_FCLK 12 -#define AFAB_AXI_S3_FCLK 13 -#define AFAB_AXI_S4_FCLK 14 -#define SFAB_CORE_CLK 15 -#define SFAB_AXI_S0_FCLK 16 -#define SFAB_AXI_S1_FCLK 17 -#define SFAB_AXI_S2_FCLK 18 -#define SFAB_AXI_S3_FCLK 19 -#define SFAB_AXI_S4_FCLK 20 -#define SFAB_AHB_S0_FCLK 21 -#define SFAB_AHB_S1_FCLK 22 -#define SFAB_AHB_S2_FCLK 23 -#define SFAB_AHB_S3_FCLK 24 -#define SFAB_AHB_S4_FCLK 25 -#define SFAB_AHB_S5_FCLK 26 -#define SFAB_AHB_S6_FCLK 27 -#define SFAB_AHB_S7_FCLK 28 -#define QDSS_AT_CLK_SRC 29 -#define QDSS_AT_CLK 30 -#define QDSS_TRACECLKIN_CLK_SRC 31 -#define QDSS_TRACECLKIN_CLK 32 -#define QDSS_TSCTR_CLK_SRC 33 -#define QDSS_TSCTR_CLK 34 -#define SFAB_ADM0_M0_A_CLK 35 -#define SFAB_ADM0_M1_A_CLK 36 -#define SFAB_ADM0_M2_H_CLK 37 -#define ADM0_CLK 38 -#define ADM0_PBUS_CLK 39 -#define MSS_XPU_CLK 40 -#define IMEM0_A_CLK 41 -#define QDSS_H_CLK 42 -#define PCIE_A_CLK 43 -#define PCIE_AUX_CLK 44 -#define PCIE_PHY_REF_CLK 45 -#define PCIE_H_CLK 46 -#define SFAB_CLK_SRC 47 -#define MAHB0_CLK 48 -#define Q6SW_CLK_SRC 49 -#define Q6SW_CLK 50 -#define Q6FW_CLK_SRC 51 -#define Q6FW_CLK 52 -#define SFAB_MSS_M_A_CLK 53 -#define SFAB_USB3_M_A_CLK 54 -#define SFAB_LPASS_Q6_A_CLK 55 -#define SFAB_AFAB_M_A_CLK 56 -#define AFAB_SFAB_M0_A_CLK 57 -#define AFAB_SFAB_M1_A_CLK 58 -#define SFAB_SATA_S_H_CLK 59 -#define DFAB_CLK_SRC 60 -#define DFAB_CLK 61 -#define SFAB_DFAB_M_A_CLK 62 -#define DFAB_SFAB_M_A_CLK 63 -#define DFAB_SWAY0_H_CLK 64 -#define DFAB_SWAY1_H_CLK 65 -#define DFAB_ARB0_H_CLK 66 -#define DFAB_ARB1_H_CLK 67 -#define PPSS_H_CLK 68 -#define PPSS_PROC_CLK 69 -#define PPSS_TIMER0_CLK 70 -#define PPSS_TIMER1_CLK 71 -#define PMEM_A_CLK 72 -#define DMA_BAM_H_CLK 73 -#define SIC_H_CLK 74 -#define SPS_TIC_H_CLK 75 -#define SLIMBUS_H_CLK 76 -#define SLIMBUS_XO_SRC_CLK 77 -#define CFPB_2X_CLK_SRC 78 -#define CFPB_CLK 79 -#define CFPB0_H_CLK 80 -#define CFPB1_H_CLK 81 -#define CFPB2_H_CLK 82 -#define SFAB_CFPB_M_H_CLK 83 -#define CFPB_MASTER_H_CLK 84 -#define SFAB_CFPB_S_H_CLK 85 -#define CFPB_SPLITTER_H_CLK 86 -#define TSIF_H_CLK 87 -#define TSIF_INACTIVITY_TIMERS_CLK 88 -#define TSIF_REF_SRC 89 -#define TSIF_REF_CLK 90 -#define CE1_H_CLK 91 -#define CE1_CORE_CLK 92 -#define CE1_SLEEP_CLK 93 -#define CE2_H_CLK 94 -#define CE2_CORE_CLK 95 -#define SFPB_H_CLK_SRC 97 -#define SFPB_H_CLK 98 -#define SFAB_SFPB_M_H_CLK 99 -#define SFAB_SFPB_S_H_CLK 100 -#define RPM_PROC_CLK 101 -#define RPM_BUS_H_CLK 102 -#define RPM_SLEEP_CLK 103 -#define RPM_TIMER_CLK 104 -#define RPM_MSG_RAM_H_CLK 105 -#define PMIC_ARB0_H_CLK 106 -#define PMIC_ARB1_H_CLK 107 -#define PMIC_SSBI2_SRC 108 -#define PMIC_SSBI2_CLK 109 -#define SDC1_H_CLK 110 -#define SDC2_H_CLK 111 -#define SDC3_H_CLK 112 -#define SDC4_H_CLK 113 -#define SDC5_H_CLK 114 -#define SDC1_SRC 115 -#define SDC2_SRC 116 -#define SDC3_SRC 117 -#define SDC4_SRC 118 -#define SDC5_SRC 119 -#define SDC1_CLK 120 -#define SDC2_CLK 121 -#define SDC3_CLK 122 -#define SDC4_CLK 123 -#define SDC5_CLK 124 -#define DFAB_A2_H_CLK 125 -#define USB_HS1_H_CLK 126 -#define USB_HS1_XCVR_SRC 127 -#define USB_HS1_XCVR_CLK 128 -#define USB_HSIC_H_CLK 129 -#define USB_HSIC_XCVR_FS_SRC 130 -#define USB_HSIC_XCVR_FS_CLK 131 -#define USB_HSIC_SYSTEM_CLK_SRC 132 -#define USB_HSIC_SYSTEM_CLK 133 -#define CFPB0_C0_H_CLK 134 -#define CFPB0_C1_H_CLK 135 -#define CFPB0_D0_H_CLK 136 -#define CFPB0_D1_H_CLK 137 -#define USB_FS1_H_CLK 138 -#define USB_FS1_XCVR_FS_SRC 139 -#define USB_FS1_XCVR_FS_CLK 140 -#define USB_FS1_SYSTEM_CLK 141 -#define USB_FS2_H_CLK 142 -#define USB_FS2_XCVR_FS_SRC 143 -#define USB_FS2_XCVR_FS_CLK 144 -#define USB_FS2_SYSTEM_CLK 145 -#define GSBI_COMMON_SIM_SRC 146 -#define GSBI1_H_CLK 147 -#define GSBI2_H_CLK 148 -#define GSBI3_H_CLK 149 -#define GSBI4_H_CLK 150 -#define GSBI5_H_CLK 151 -#define GSBI6_H_CLK 152 -#define GSBI7_H_CLK 153 -#define GSBI8_H_CLK 154 -#define GSBI9_H_CLK 155 -#define GSBI10_H_CLK 156 -#define GSBI11_H_CLK 157 -#define GSBI12_H_CLK 158 -#define GSBI1_UART_SRC 159 -#define GSBI1_UART_CLK 160 -#define GSBI2_UART_SRC 161 -#define GSBI2_UART_CLK 162 -#define GSBI3_UART_SRC 163 -#define GSBI3_UART_CLK 164 -#define GSBI4_UART_SRC 165 -#define GSBI4_UART_CLK 166 -#define GSBI5_UART_SRC 167 -#define GSBI5_UART_CLK 168 -#define GSBI6_UART_SRC 169 -#define GSBI6_UART_CLK 170 -#define GSBI7_UART_SRC 171 -#define GSBI7_UART_CLK 172 -#define GSBI8_UART_SRC 173 -#define GSBI8_UART_CLK 174 -#define GSBI9_UART_SRC 175 -#define GSBI9_UART_CLK 176 -#define GSBI10_UART_SRC 177 -#define GSBI10_UART_CLK 178 -#define GSBI11_UART_SRC 179 -#define GSBI11_UART_CLK 180 -#define GSBI12_UART_SRC 181 -#define GSBI12_UART_CLK 182 -#define GSBI1_QUP_SRC 183 -#define GSBI1_QUP_CLK 184 -#define GSBI2_QUP_SRC 185 -#define GSBI2_QUP_CLK 186 -#define GSBI3_QUP_SRC 187 -#define GSBI3_QUP_CLK 188 -#define GSBI4_QUP_SRC 189 -#define GSBI4_QUP_CLK 190 -#define GSBI5_QUP_SRC 191 -#define GSBI5_QUP_CLK 192 -#define GSBI6_QUP_SRC 193 -#define GSBI6_QUP_CLK 194 -#define GSBI7_QUP_SRC 195 -#define GSBI7_QUP_CLK 196 -#define GSBI8_QUP_SRC 197 -#define GSBI8_QUP_CLK 198 -#define GSBI9_QUP_SRC 199 -#define GSBI9_QUP_CLK 200 -#define GSBI10_QUP_SRC 201 -#define GSBI10_QUP_CLK 202 -#define GSBI11_QUP_SRC 203 -#define GSBI11_QUP_CLK 204 -#define GSBI12_QUP_SRC 205 -#define GSBI12_QUP_CLK 206 -#define GSBI1_SIM_CLK 207 -#define GSBI2_SIM_CLK 208 -#define GSBI3_SIM_CLK 209 -#define GSBI4_SIM_CLK 210 -#define GSBI5_SIM_CLK 211 -#define GSBI6_SIM_CLK 212 -#define GSBI7_SIM_CLK 213 -#define GSBI8_SIM_CLK 214 -#define GSBI9_SIM_CLK 215 -#define GSBI10_SIM_CLK 216 -#define GSBI11_SIM_CLK 217 -#define GSBI12_SIM_CLK 218 -#define USB_HSIC_HSIC_CLK_SRC 219 -#define USB_HSIC_HSIC_CLK 220 -#define USB_HSIC_HSIO_CAL_CLK 221 -#define SPDM_CFG_H_CLK 222 -#define SPDM_MSTR_H_CLK 223 -#define SPDM_FF_CLK_SRC 224 -#define SPDM_FF_CLK 225 -#define SEC_CTRL_CLK 226 -#define SEC_CTRL_ACC_CLK_SRC 227 -#define SEC_CTRL_ACC_CLK 228 -#define TLMM_H_CLK 229 -#define TLMM_CLK 230 -#define SFAB_MSS_S_H_CLK 231 -#define MSS_SLP_CLK 232 -#define MSS_Q6SW_JTAG_CLK 233 -#define MSS_Q6FW_JTAG_CLK 234 -#define MSS_S_H_CLK 235 -#define MSS_CXO_SRC_CLK 236 -#define SATA_H_CLK 237 -#define SATA_CLK_SRC 238 -#define SATA_RXOOB_CLK 239 -#define SATA_PMALIVE_CLK 240 -#define SATA_PHY_REF_CLK 241 -#define TSSC_CLK_SRC 242 -#define TSSC_CLK 243 -#define PDM_SRC 244 -#define PDM_CLK 245 -#define GP0_SRC 246 -#define GP0_CLK 247 -#define GP1_SRC 248 -#define GP1_CLK 249 -#define GP2_SRC 250 -#define GP2_CLK 251 -#define MPM_CLK 252 -#define EBI1_CLK_SRC 253 -#define EBI1_CH0_CLK 254 -#define EBI1_CH1_CLK 255 -#define EBI1_2X_CLK 256 -#define EBI1_CH0_DQ_CLK 257 -#define EBI1_CH1_DQ_CLK 258 -#define EBI1_CH0_CA_CLK 259 -#define EBI1_CH1_CA_CLK 260 -#define EBI1_XO_CLK 261 -#define SFAB_SMPSS_S_H_CLK 262 -#define PRNG_SRC 263 -#define PRNG_CLK 264 -#define PXO_SRC 265 -#define LPASS_CXO_CLK 266 -#define LPASS_PXO_CLK 267 -#define SPDM_CY_PORT0_CLK 268 -#define SPDM_CY_PORT1_CLK 269 -#define SPDM_CY_PORT2_CLK 270 -#define SPDM_CY_PORT3_CLK 271 -#define SPDM_CY_PORT4_CLK 272 -#define SPDM_CY_PORT5_CLK 273 -#define SPDM_CY_PORT6_CLK 274 -#define SPDM_CY_PORT7_CLK 275 -#define PLL0 276 -#define PLL0_VOTE 277 -#define PLL3 278 -#define PLL3_VOTE 279 -#define PLL4_VOTE 280 -#define PLL5 281 -#define PLL5_VOTE 282 -#define PLL6 283 -#define PLL6_VOTE 284 -#define PLL7_VOTE 285 -#define PLL8 286 -#define PLL8_VOTE 287 -#define PLL9 288 -#define PLL10 289 -#define PLL11 290 -#define PLL12 291 -#define PLL13 292 -#define PLL14 293 -#define PLL14_VOTE 294 -#define USB_HS3_H_CLK 295 -#define USB_HS3_XCVR_SRC 296 -#define USB_HS3_XCVR_CLK 297 -#define USB_HS4_H_CLK 298 -#define USB_HS4_XCVR_SRC 299 -#define USB_HS4_XCVR_CLK 300 -#define SATA_PHY_CFG_CLK 301 -#define SATA_A_CLK 302 -#define CE3_SRC 303 -#define CE3_CORE_CLK 304 -#define CE3_H_CLK 305 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h deleted file mode 100644 index 51e51c8..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-msm8974.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H -#define _DT_BINDINGS_CLK_MSM_GCC_8974_H - -#define GPLL0 0 -#define GPLL0_VOTE 1 -#define CONFIG_NOC_CLK_SRC 2 -#define GPLL2 3 -#define GPLL2_VOTE 4 -#define GPLL3 5 -#define GPLL3_VOTE 6 -#define PERIPH_NOC_CLK_SRC 7 -#define BLSP_UART_SIM_CLK_SRC 8 -#define QDSS_TSCTR_CLK_SRC 9 -#define BIMC_DDR_CLK_SRC 10 -#define SYSTEM_NOC_CLK_SRC 11 -#define GPLL1 12 -#define GPLL1_VOTE 13 -#define RPM_CLK_SRC 14 -#define GCC_BIMC_CLK 15 -#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 -#define KPSS_AHB_CLK_SRC 17 -#define QDSS_AT_CLK_SRC 18 -#define USB30_MASTER_CLK_SRC 19 -#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 -#define QDSS_STM_CLK_SRC 21 -#define ACC_CLK_SRC 22 -#define SEC_CTRL_CLK_SRC 23 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 -#define BLSP1_UART1_APPS_CLK_SRC 36 -#define BLSP1_UART2_APPS_CLK_SRC 37 -#define BLSP1_UART3_APPS_CLK_SRC 38 -#define BLSP1_UART4_APPS_CLK_SRC 39 -#define BLSP1_UART5_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 -#define BLSP2_UART1_APPS_CLK_SRC 54 -#define BLSP2_UART2_APPS_CLK_SRC 55 -#define BLSP2_UART3_APPS_CLK_SRC 56 -#define BLSP2_UART4_APPS_CLK_SRC 57 -#define BLSP2_UART5_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define CE1_CLK_SRC 60 -#define CE2_CLK_SRC 61 -#define GP1_CLK_SRC 62 -#define GP2_CLK_SRC 63 -#define GP3_CLK_SRC 64 -#define PDM2_CLK_SRC 65 -#define QDSS_TRACECLKIN_CLK_SRC 66 -#define RBCPR_CLK_SRC 67 -#define SDCC1_APPS_CLK_SRC 68 -#define SDCC2_APPS_CLK_SRC 69 -#define SDCC3_APPS_CLK_SRC 70 -#define SDCC4_APPS_CLK_SRC 71 -#define SPMI_AHB_CLK_SRC 72 -#define SPMI_SER_CLK_SRC 73 -#define TSIF_REF_CLK_SRC 74 -#define USB30_MOCK_UTMI_CLK_SRC 75 -#define USB_HS_SYSTEM_CLK_SRC 76 -#define USB_HSIC_CLK_SRC 77 -#define USB_HSIC_IO_CAL_CLK_SRC 78 -#define USB_HSIC_SYSTEM_CLK_SRC 79 -#define GCC_BAM_DMA_AHB_CLK 80 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 -#define GCC_BIMC_CFG_AHB_CLK 82 -#define GCC_BIMC_KPSS_AXI_CLK 83 -#define GCC_BIMC_SLEEP_CLK 84 -#define GCC_BIMC_SYSNOC_AXI_CLK 85 -#define GCC_BIMC_XO_CLK 86 -#define GCC_BLSP1_AHB_CLK 87 -#define GCC_BLSP1_SLEEP_CLK 88 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 -#define GCC_BLSP1_UART1_APPS_CLK 101 -#define GCC_BLSP1_UART1_SIM_CLK 102 -#define GCC_BLSP1_UART2_APPS_CLK 103 -#define GCC_BLSP1_UART2_SIM_CLK 104 -#define GCC_BLSP1_UART3_APPS_CLK 105 -#define GCC_BLSP1_UART3_SIM_CLK 106 -#define GCC_BLSP1_UART4_APPS_CLK 107 -#define GCC_BLSP1_UART4_SIM_CLK 108 -#define GCC_BLSP1_UART5_APPS_CLK 109 -#define GCC_BLSP1_UART5_SIM_CLK 110 -#define GCC_BLSP1_UART6_APPS_CLK 111 -#define GCC_BLSP1_UART6_SIM_CLK 112 -#define GCC_BLSP2_AHB_CLK 113 -#define GCC_BLSP2_SLEEP_CLK 114 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP2_UART1_APPS_CLK 127 -#define GCC_BLSP2_UART1_SIM_CLK 128 -#define GCC_BLSP2_UART2_APPS_CLK 129 -#define GCC_BLSP2_UART2_SIM_CLK 130 -#define GCC_BLSP2_UART3_APPS_CLK 131 -#define GCC_BLSP2_UART3_SIM_CLK 132 -#define GCC_BLSP2_UART4_APPS_CLK 133 -#define GCC_BLSP2_UART4_SIM_CLK 134 -#define GCC_BLSP2_UART5_APPS_CLK 135 -#define GCC_BLSP2_UART5_SIM_CLK 136 -#define GCC_BLSP2_UART6_APPS_CLK 137 -#define GCC_BLSP2_UART6_SIM_CLK 138 -#define GCC_BOOT_ROM_AHB_CLK 139 -#define GCC_CE1_AHB_CLK 140 -#define GCC_CE1_AXI_CLK 141 -#define GCC_CE1_CLK 142 -#define GCC_CE2_AHB_CLK 143 -#define GCC_CE2_AXI_CLK 144 -#define GCC_CE2_CLK 145 -#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 -#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 -#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 -#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 -#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 -#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 -#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 -#define GCC_CFG_NOC_AHB_CLK 153 -#define GCC_CFG_NOC_DDR_CFG_CLK 154 -#define GCC_CFG_NOC_RPM_AHB_CLK 155 -#define GCC_BIMC_DDR_CPLL0_CLK 156 -#define GCC_BIMC_DDR_CPLL1_CLK 157 -#define GCC_DDR_DIM_CFG_CLK 158 -#define GCC_DDR_DIM_SLEEP_CLK 159 -#define GCC_DEHR_CLK 160 -#define GCC_AHB_CLK 161 -#define GCC_IM_SLEEP_CLK 162 -#define GCC_XO_CLK 163 -#define GCC_XO_DIV4_CLK 164 -#define GCC_GP1_CLK 165 -#define GCC_GP2_CLK 166 -#define GCC_GP3_CLK 167 -#define GCC_IMEM_AXI_CLK 168 -#define GCC_IMEM_CFG_AHB_CLK 169 -#define GCC_KPSS_AHB_CLK 170 -#define GCC_KPSS_AXI_CLK 171 -#define GCC_LPASS_Q6_AXI_CLK 172 -#define GCC_MMSS_NOC_AT_CLK 173 -#define GCC_MMSS_NOC_CFG_AHB_CLK 174 -#define GCC_OCMEM_NOC_CFG_AHB_CLK 175 -#define GCC_OCMEM_SYS_NOC_AXI_CLK 176 -#define GCC_MPM_AHB_CLK 177 -#define GCC_MSG_RAM_AHB_CLK 178 -#define GCC_MSS_CFG_AHB_CLK 179 -#define GCC_MSS_Q6_BIMC_AXI_CLK 180 -#define GCC_NOC_CONF_XPU_AHB_CLK 181 -#define GCC_PDM2_CLK 182 -#define GCC_PDM_AHB_CLK 183 -#define GCC_PDM_XO4_CLK 184 -#define GCC_PERIPH_NOC_AHB_CLK 185 -#define GCC_PERIPH_NOC_AT_CLK 186 -#define GCC_PERIPH_NOC_CFG_AHB_CLK 187 -#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 -#define GCC_PERIPH_XPU_AHB_CLK 189 -#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 -#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 -#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 -#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 -#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 -#define GCC_PRNG_AHB_CLK 195 -#define GCC_QDSS_AT_CLK 196 -#define GCC_QDSS_CFG_AHB_CLK 197 -#define GCC_QDSS_DAP_AHB_CLK 198 -#define GCC_QDSS_DAP_CLK 199 -#define GCC_QDSS_ETR_USB_CLK 200 -#define GCC_QDSS_STM_CLK 201 -#define GCC_QDSS_TRACECLKIN_CLK 202 -#define GCC_QDSS_TSCTR_DIV16_CLK 203 -#define GCC_QDSS_TSCTR_DIV2_CLK 204 -#define GCC_QDSS_TSCTR_DIV3_CLK 205 -#define GCC_QDSS_TSCTR_DIV4_CLK 206 -#define GCC_QDSS_TSCTR_DIV8_CLK 207 -#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 -#define GCC_RBCPR_AHB_CLK 209 -#define GCC_RBCPR_CLK 210 -#define GCC_RPM_BUS_AHB_CLK 211 -#define GCC_RPM_PROC_HCLK 212 -#define GCC_RPM_SLEEP_CLK 213 -#define GCC_RPM_TIMER_CLK 214 -#define GCC_SDCC1_AHB_CLK 215 -#define GCC_SDCC1_APPS_CLK 216 -#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 -#define GCC_SDCC2_AHB_CLK 218 -#define GCC_SDCC2_APPS_CLK 219 -#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 -#define GCC_SDCC3_AHB_CLK 221 -#define GCC_SDCC3_APPS_CLK 222 -#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 -#define GCC_SDCC4_AHB_CLK 224 -#define GCC_SDCC4_APPS_CLK 225 -#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 -#define GCC_SEC_CTRL_ACC_CLK 227 -#define GCC_SEC_CTRL_AHB_CLK 228 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 -#define GCC_SEC_CTRL_CLK 230 -#define GCC_SEC_CTRL_SENSE_CLK 231 -#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 -#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 -#define GCC_SPDM_BIMC_CY_CLK 234 -#define GCC_SPDM_CFG_AHB_CLK 235 -#define GCC_SPDM_DEBUG_CY_CLK 236 -#define GCC_SPDM_FF_CLK 237 -#define GCC_SPDM_MSTR_AHB_CLK 238 -#define GCC_SPDM_PNOC_CY_CLK 239 -#define GCC_SPDM_RPM_CY_CLK 240 -#define GCC_SPDM_SNOC_CY_CLK 241 -#define GCC_SPMI_AHB_CLK 242 -#define GCC_SPMI_CNOC_AHB_CLK 243 -#define GCC_SPMI_SER_CLK 244 -#define GCC_SNOC_CNOC_AHB_CLK 245 -#define GCC_SNOC_PNOC_AHB_CLK 246 -#define GCC_SYS_NOC_AT_CLK 247 -#define GCC_SYS_NOC_AXI_CLK 248 -#define GCC_SYS_NOC_KPSS_AHB_CLK 249 -#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 -#define GCC_SYS_NOC_USB3_AXI_CLK 251 -#define GCC_TCSR_AHB_CLK 252 -#define GCC_TLMM_AHB_CLK 253 -#define GCC_TLMM_CLK 254 -#define GCC_TSIF_AHB_CLK 255 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 -#define GCC_TSIF_REF_CLK 257 -#define GCC_USB2A_PHY_SLEEP_CLK 258 -#define GCC_USB2B_PHY_SLEEP_CLK 259 -#define GCC_USB30_MASTER_CLK 260 -#define GCC_USB30_MOCK_UTMI_CLK 261 -#define GCC_USB30_SLEEP_CLK 262 -#define GCC_USB_HS_AHB_CLK 263 -#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 -#define GCC_USB_HS_SYSTEM_CLK 265 -#define GCC_USB_HSIC_AHB_CLK 266 -#define GCC_USB_HSIC_CLK 267 -#define GCC_USB_HSIC_IO_CAL_CLK 268 -#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 -#define GCC_USB_HSIC_SYSTEM_CLK 270 -#define GCC_WCSS_GPLL1_CLK_SRC 271 -#define GCC_MMSS_GPLL0_CLK_SRC 272 -#define GCC_LPASS_GPLL0_CLK_SRC 273 -#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 -#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 -#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 -#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 -#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 -#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 -#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 -#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 -#define GCC_MPM_AHB_CLK_SLEEP_ENA 282 -#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 -#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 -#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 -#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 -#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 -#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 -#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 -#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 -#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 -#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 -#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 -#define GCC_TLMM_CLK_SLEEP_ENA 294 -#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 -#define GCC_CE1_CLK_SLEEP_ENA 296 -#define GCC_CE1_AXI_CLK_SLEEP_ENA 297 -#define GCC_CE1_AHB_CLK_SLEEP_ENA 298 -#define GCC_CE2_CLK_SLEEP_ENA 299 -#define GCC_CE2_AXI_CLK_SLEEP_ENA 300 -#define GCC_CE2_AHB_CLK_SLEEP_ENA 301 -#define GPLL4 302 -#define GPLL4_VOTE 303 -#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 -#define GCC_SDCC1_CDCCAL_FF_CLK 305 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h deleted file mode 100644 index 4e944b8..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-ipq806x.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H -#define _DT_BINDINGS_CLK_LCC_IPQ806X_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SPDIF_SRC 9 -#define SPDIF_CLK 10 -#define AHBIX_CLK 11 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h deleted file mode 100644 index 4fb2aa6..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,lcc-msm8960.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H -#define _DT_BINDINGS_CLK_LCC_MSM8960_H - -#define PLL4 0 -#define MI2S_OSR_SRC 1 -#define MI2S_OSR_CLK 2 -#define MI2S_DIV_CLK 3 -#define MI2S_BIT_DIV_CLK 4 -#define MI2S_BIT_CLK 5 -#define PCM_SRC 6 -#define PCM_CLK_OUT 7 -#define PCM_CLK 8 -#define SLIMBUS_SRC 9 -#define AUDIO_SLIMBUS_CLK 10 -#define SPS_SLIMBUS_CLK 11 -#define CODEC_I2S_MIC_OSR_SRC 12 -#define CODEC_I2S_MIC_OSR_CLK 13 -#define CODEC_I2S_MIC_DIV_CLK 14 -#define CODEC_I2S_MIC_BIT_DIV_CLK 15 -#define CODEC_I2S_MIC_BIT_CLK 16 -#define SPARE_I2S_MIC_OSR_SRC 17 -#define SPARE_I2S_MIC_OSR_CLK 18 -#define SPARE_I2S_MIC_DIV_CLK 19 -#define SPARE_I2S_MIC_BIT_DIV_CLK 20 -#define SPARE_I2S_MIC_BIT_CLK 21 -#define CODEC_I2S_SPKR_OSR_SRC 22 -#define CODEC_I2S_SPKR_OSR_CLK 23 -#define CODEC_I2S_SPKR_DIV_CLK 24 -#define CODEC_I2S_SPKR_BIT_DIV_CLK 25 -#define CODEC_I2S_SPKR_BIT_CLK 26 -#define SPARE_I2S_SPKR_OSR_SRC 27 -#define SPARE_I2S_SPKR_OSR_CLK 28 -#define SPARE_I2S_SPKR_DIV_CLK 29 -#define SPARE_I2S_SPKR_BIT_DIV_CLK 30 -#define SPARE_I2S_SPKR_BIT_CLK 31 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h deleted file mode 100644 index d72b5b3..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H -#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define MMPLL4 8 -#define CSI0_CLK_SRC 9 -#define CSI1_CLK_SRC 10 -#define CSI2_CLK_SRC 11 -#define CSI3_CLK_SRC 12 -#define VCODEC0_CLK_SRC 13 -#define VFE0_CLK_SRC 14 -#define VFE1_CLK_SRC 15 -#define MDP_CLK_SRC 16 -#define PCLK0_CLK_SRC 17 -#define PCLK1_CLK_SRC 18 -#define OCMEMNOC_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define JPEG0_CLK_SRC 21 -#define JPEG1_CLK_SRC 22 -#define JPEG2_CLK_SRC 23 -#define EDPPIXEL_CLK_SRC 24 -#define EXTPCLK_CLK_SRC 25 -#define VP_CLK_SRC 26 -#define CCI_CLK_SRC 27 -#define CAMSS_GP0_CLK_SRC 28 -#define CAMSS_GP1_CLK_SRC 29 -#define MCLK0_CLK_SRC 30 -#define MCLK1_CLK_SRC 31 -#define MCLK2_CLK_SRC 32 -#define MCLK3_CLK_SRC 33 -#define CSI0PHYTIMER_CLK_SRC 34 -#define CSI1PHYTIMER_CLK_SRC 35 -#define CSI2PHYTIMER_CLK_SRC 36 -#define CPP_CLK_SRC 37 -#define BYTE0_CLK_SRC 38 -#define BYTE1_CLK_SRC 39 -#define EDPAUX_CLK_SRC 40 -#define EDPLINK_CLK_SRC 41 -#define ESC0_CLK_SRC 42 -#define ESC1_CLK_SRC 43 -#define HDMI_CLK_SRC 44 -#define VSYNC_CLK_SRC 45 -#define MMSS_RBCPR_CLK_SRC 46 -#define RBBMTIMER_CLK_SRC 47 -#define MAPLE_CLK_SRC 48 -#define VDP_CLK_SRC 49 -#define VPU_BUS_CLK_SRC 50 -#define MMSS_CXO_CLK 51 -#define MMSS_SLEEPCLK_CLK 52 -#define AVSYNC_AHB_CLK 53 -#define AVSYNC_EDPPIXEL_CLK 54 -#define AVSYNC_EXTPCLK_CLK 55 -#define AVSYNC_PCLK0_CLK 56 -#define AVSYNC_PCLK1_CLK 57 -#define AVSYNC_VP_CLK 58 -#define CAMSS_AHB_CLK 59 -#define CAMSS_CCI_CCI_AHB_CLK 60 -#define CAMSS_CCI_CCI_CLK 61 -#define CAMSS_CSI0_AHB_CLK 62 -#define CAMSS_CSI0_CLK 63 -#define CAMSS_CSI0PHY_CLK 64 -#define CAMSS_CSI0PIX_CLK 65 -#define CAMSS_CSI0RDI_CLK 66 -#define CAMSS_CSI1_AHB_CLK 67 -#define CAMSS_CSI1_CLK 68 -#define CAMSS_CSI1PHY_CLK 69 -#define CAMSS_CSI1PIX_CLK 70 -#define CAMSS_CSI1RDI_CLK 71 -#define CAMSS_CSI2_AHB_CLK 72 -#define CAMSS_CSI2_CLK 73 -#define CAMSS_CSI2PHY_CLK 74 -#define CAMSS_CSI2PIX_CLK 75 -#define CAMSS_CSI2RDI_CLK 76 -#define CAMSS_CSI3_AHB_CLK 77 -#define CAMSS_CSI3_CLK 78 -#define CAMSS_CSI3PHY_CLK 79 -#define CAMSS_CSI3PIX_CLK 80 -#define CAMSS_CSI3RDI_CLK 81 -#define CAMSS_CSI_VFE0_CLK 82 -#define CAMSS_CSI_VFE1_CLK 83 -#define CAMSS_GP0_CLK 84 -#define CAMSS_GP1_CLK 85 -#define CAMSS_ISPIF_AHB_CLK 86 -#define CAMSS_JPEG_JPEG0_CLK 87 -#define CAMSS_JPEG_JPEG1_CLK 88 -#define CAMSS_JPEG_JPEG2_CLK 89 -#define CAMSS_JPEG_JPEG_AHB_CLK 90 -#define CAMSS_JPEG_JPEG_AXI_CLK 91 -#define CAMSS_MCLK0_CLK 92 -#define CAMSS_MCLK1_CLK 93 -#define CAMSS_MCLK2_CLK 94 -#define CAMSS_MCLK3_CLK 95 -#define CAMSS_MICRO_AHB_CLK 96 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 -#define CAMSS_TOP_AHB_CLK 100 -#define CAMSS_VFE_CPP_AHB_CLK 101 -#define CAMSS_VFE_CPP_CLK 102 -#define CAMSS_VFE_VFE0_CLK 103 -#define CAMSS_VFE_VFE1_CLK 104 -#define CAMSS_VFE_VFE_AHB_CLK 105 -#define CAMSS_VFE_VFE_AXI_CLK 106 -#define MDSS_AHB_CLK 107 -#define MDSS_AXI_CLK 108 -#define MDSS_BYTE0_CLK 109 -#define MDSS_BYTE1_CLK 110 -#define MDSS_EDPAUX_CLK 111 -#define MDSS_EDPLINK_CLK 112 -#define MDSS_EDPPIXEL_CLK 113 -#define MDSS_ESC0_CLK 114 -#define MDSS_ESC1_CLK 115 -#define MDSS_EXTPCLK_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_HDMI_CLK 118 -#define MDSS_MDP_CLK 119 -#define MDSS_MDP_LUT_CLK 120 -#define MDSS_PCLK0_CLK 121 -#define MDSS_PCLK1_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MMSS_RBCPR_AHB_CLK 124 -#define MMSS_RBCPR_CLK 125 -#define MMSS_SPDM_AHB_CLK 126 -#define MMSS_SPDM_AXI_CLK 127 -#define MMSS_SPDM_CSI0_CLK 128 -#define MMSS_SPDM_GFX3D_CLK 129 -#define MMSS_SPDM_JPEG0_CLK 130 -#define MMSS_SPDM_JPEG1_CLK 131 -#define MMSS_SPDM_JPEG2_CLK 132 -#define MMSS_SPDM_MDP_CLK 133 -#define MMSS_SPDM_PCLK0_CLK 134 -#define MMSS_SPDM_PCLK1_CLK 135 -#define MMSS_SPDM_VCODEC0_CLK 136 -#define MMSS_SPDM_VFE0_CLK 137 -#define MMSS_SPDM_VFE1_CLK 138 -#define MMSS_SPDM_RM_AXI_CLK 139 -#define MMSS_SPDM_RM_OCMEMNOC_CLK 140 -#define MMSS_MISC_AHB_CLK 141 -#define MMSS_MMSSNOC_AHB_CLK 142 -#define MMSS_MMSSNOC_BTO_AHB_CLK 143 -#define MMSS_MMSSNOC_AXI_CLK 144 -#define MMSS_S0_AXI_CLK 145 -#define OCMEMCX_AHB_CLK 146 -#define OCMEMCX_OCMEMNOC_CLK 147 -#define OXILI_OCMEMGX_CLK 148 -#define OXILI_GFX3D_CLK 149 -#define OXILI_RBBMTIMER_CLK 150 -#define OXILICX_AHB_CLK 151 -#define VENUS0_AHB_CLK 152 -#define VENUS0_AXI_CLK 153 -#define VENUS0_CORE0_VCODEC_CLK 154 -#define VENUS0_CORE1_VCODEC_CLK 155 -#define VENUS0_OCMEMNOC_CLK 156 -#define VENUS0_VCODEC0_CLK 157 -#define VPU_AHB_CLK 158 -#define VPU_AXI_CLK 159 -#define VPU_BUS_CLK 160 -#define VPU_CXO_CLK 161 -#define VPU_MAPLE_CLK 162 -#define VPU_SLEEP_CLK 163 -#define VPU_VDP_CLK 164 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h deleted file mode 100644 index 85041b2..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H - -#define MMSS_AHB_SRC 0 -#define FAB_AHB_CLK 1 -#define APU_AHB_CLK 2 -#define TV_ENC_AHB_CLK 3 -#define AMP_AHB_CLK 4 -#define DSI2_S_AHB_CLK 5 -#define JPEGD_AHB_CLK 6 -#define GFX2D0_AHB_CLK 7 -#define DSI_S_AHB_CLK 8 -#define DSI2_M_AHB_CLK 9 -#define VPE_AHB_CLK 10 -#define SMMU_AHB_CLK 11 -#define HDMI_M_AHB_CLK 12 -#define VFE_AHB_CLK 13 -#define ROT_AHB_CLK 14 -#define VCODEC_AHB_CLK 15 -#define MDP_AHB_CLK 16 -#define DSI_M_AHB_CLK 17 -#define CSI_AHB_CLK 18 -#define MMSS_IMEM_AHB_CLK 19 -#define IJPEG_AHB_CLK 20 -#define HDMI_S_AHB_CLK 21 -#define GFX3D_AHB_CLK 22 -#define GFX2D1_AHB_CLK 23 -#define MMSS_FPB_CLK 24 -#define MMSS_AXI_SRC 25 -#define MMSS_FAB_CORE 26 -#define FAB_MSP_AXI_CLK 27 -#define JPEGD_AXI_CLK 28 -#define GMEM_AXI_CLK 29 -#define MDP_AXI_CLK 30 -#define MMSS_IMEM_AXI_CLK 31 -#define IJPEG_AXI_CLK 32 -#define GFX3D_AXI_CLK 33 -#define VCODEC_AXI_CLK 34 -#define VFE_AXI_CLK 35 -#define VPE_AXI_CLK 36 -#define ROT_AXI_CLK 37 -#define VCODEC_AXI_A_CLK 38 -#define VCODEC_AXI_B_CLK 39 -#define MM_AXI_S3_FCLK 40 -#define MM_AXI_S2_FCLK 41 -#define MM_AXI_S1_FCLK 42 -#define MM_AXI_S0_FCLK 43 -#define MM_AXI_S2_CLK 44 -#define MM_AXI_S1_CLK 45 -#define MM_AXI_S0_CLK 46 -#define CSI0_SRC 47 -#define CSI0_CLK 48 -#define CSI0_PHY_CLK 49 -#define CSI1_SRC 50 -#define CSI1_CLK 51 -#define CSI1_PHY_CLK 52 -#define CSI2_SRC 53 -#define CSI2_CLK 54 -#define CSI2_PHY_CLK 55 -#define DSI_SRC 56 -#define DSI_CLK 57 -#define CSI_PIX_CLK 58 -#define CSI_RDI_CLK 59 -#define MDP_VSYNC_CLK 60 -#define HDMI_DIV_CLK 61 -#define HDMI_APP_CLK 62 -#define CSI_PIX1_CLK 63 -#define CSI_RDI2_CLK 64 -#define CSI_RDI1_CLK 65 -#define GFX2D0_SRC 66 -#define GFX2D0_CLK 67 -#define GFX2D1_SRC 68 -#define GFX2D1_CLK 69 -#define GFX3D_SRC 70 -#define GFX3D_CLK 71 -#define IJPEG_SRC 72 -#define IJPEG_CLK 73 -#define JPEGD_SRC 74 -#define JPEGD_CLK 75 -#define MDP_SRC 76 -#define MDP_CLK 77 -#define MDP_LUT_CLK 78 -#define DSI2_PIXEL_SRC 79 -#define DSI2_PIXEL_CLK 80 -#define DSI2_SRC 81 -#define DSI2_CLK 82 -#define DSI1_BYTE_SRC 83 -#define DSI1_BYTE_CLK 84 -#define DSI2_BYTE_SRC 85 -#define DSI2_BYTE_CLK 86 -#define DSI1_ESC_SRC 87 -#define DSI1_ESC_CLK 88 -#define DSI2_ESC_SRC 89 -#define DSI2_ESC_CLK 90 -#define ROT_SRC 91 -#define ROT_CLK 92 -#define TV_ENC_CLK 93 -#define TV_DAC_CLK 94 -#define HDMI_TV_CLK 95 -#define MDP_TV_CLK 96 -#define TV_SRC 97 -#define VCODEC_SRC 98 -#define VCODEC_CLK 99 -#define VFE_SRC 100 -#define VFE_CLK 101 -#define VFE_CSI_CLK 102 -#define VPE_SRC 103 -#define VPE_CLK 104 -#define DSI_PIXEL_SRC 105 -#define DSI_PIXEL_CLK 106 -#define CAMCLK0_SRC 107 -#define CAMCLK0_CLK 108 -#define CAMCLK1_SRC 109 -#define CAMCLK1_CLK 110 -#define CAMCLK2_SRC 111 -#define CAMCLK2_CLK 112 -#define CSIPHYTIMER_SRC 113 -#define CSIPHY2_TIMER_CLK 114 -#define CSIPHY1_TIMER_CLK 115 -#define CSIPHY0_TIMER_CLK 116 -#define PLL1 117 -#define PLL2 118 -#define RGB_TV_CLK 119 -#define NPL_TV_CLK 120 -#define VCAP_AHB_CLK 121 -#define VCAP_AXI_CLK 122 -#define VCAP_SRC 123 -#define VCAP_CLK 124 -#define VCAP_NPL_CLK 125 -#define PLL15 126 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h deleted file mode 100644 index 032ed87..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H -#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H - -#define MMSS_AHB_CLK_SRC 0 -#define MMSS_AXI_CLK_SRC 1 -#define MMPLL0 2 -#define MMPLL0_VOTE 3 -#define MMPLL1 4 -#define MMPLL1_VOTE 5 -#define MMPLL2 6 -#define MMPLL3 7 -#define CSI0_CLK_SRC 8 -#define CSI1_CLK_SRC 9 -#define CSI2_CLK_SRC 10 -#define CSI3_CLK_SRC 11 -#define VFE0_CLK_SRC 12 -#define VFE1_CLK_SRC 13 -#define MDP_CLK_SRC 14 -#define GFX3D_CLK_SRC 15 -#define JPEG0_CLK_SRC 16 -#define JPEG1_CLK_SRC 17 -#define JPEG2_CLK_SRC 18 -#define PCLK0_CLK_SRC 19 -#define PCLK1_CLK_SRC 20 -#define VCODEC0_CLK_SRC 21 -#define CCI_CLK_SRC 22 -#define CAMSS_GP0_CLK_SRC 23 -#define CAMSS_GP1_CLK_SRC 24 -#define MCLK0_CLK_SRC 25 -#define MCLK1_CLK_SRC 26 -#define MCLK2_CLK_SRC 27 -#define MCLK3_CLK_SRC 28 -#define CSI0PHYTIMER_CLK_SRC 29 -#define CSI1PHYTIMER_CLK_SRC 30 -#define CSI2PHYTIMER_CLK_SRC 31 -#define CPP_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define EDPAUX_CLK_SRC 35 -#define EDPLINK_CLK_SRC 36 -#define EDPPIXEL_CLK_SRC 37 -#define ESC0_CLK_SRC 38 -#define ESC1_CLK_SRC 39 -#define EXTPCLK_CLK_SRC 40 -#define HDMI_CLK_SRC 41 -#define VSYNC_CLK_SRC 42 -#define MMSS_RBCPR_CLK_SRC 43 -#define CAMSS_CCI_CCI_AHB_CLK 44 -#define CAMSS_CCI_CCI_CLK 45 -#define CAMSS_CSI0_AHB_CLK 46 -#define CAMSS_CSI0_CLK 47 -#define CAMSS_CSI0PHY_CLK 48 -#define CAMSS_CSI0PIX_CLK 49 -#define CAMSS_CSI0RDI_CLK 50 -#define CAMSS_CSI1_AHB_CLK 51 -#define CAMSS_CSI1_CLK 52 -#define CAMSS_CSI1PHY_CLK 53 -#define CAMSS_CSI1PIX_CLK 54 -#define CAMSS_CSI1RDI_CLK 55 -#define CAMSS_CSI2_AHB_CLK 56 -#define CAMSS_CSI2_CLK 57 -#define CAMSS_CSI2PHY_CLK 58 -#define CAMSS_CSI2PIX_CLK 59 -#define CAMSS_CSI2RDI_CLK 60 -#define CAMSS_CSI3_AHB_CLK 61 -#define CAMSS_CSI3_CLK 62 -#define CAMSS_CSI3PHY_CLK 63 -#define CAMSS_CSI3PIX_CLK 64 -#define CAMSS_CSI3RDI_CLK 65 -#define CAMSS_CSI_VFE0_CLK 66 -#define CAMSS_CSI_VFE1_CLK 67 -#define CAMSS_GP0_CLK 68 -#define CAMSS_GP1_CLK 69 -#define CAMSS_ISPIF_AHB_CLK 70 -#define CAMSS_JPEG_JPEG0_CLK 71 -#define CAMSS_JPEG_JPEG1_CLK 72 -#define CAMSS_JPEG_JPEG2_CLK 73 -#define CAMSS_JPEG_JPEG_AHB_CLK 74 -#define CAMSS_JPEG_JPEG_AXI_CLK 75 -#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76 -#define CAMSS_MCLK0_CLK 77 -#define CAMSS_MCLK1_CLK 78 -#define CAMSS_MCLK2_CLK 79 -#define CAMSS_MCLK3_CLK 80 -#define CAMSS_MICRO_AHB_CLK 81 -#define CAMSS_PHY0_CSI0PHYTIMER_CLK 82 -#define CAMSS_PHY1_CSI1PHYTIMER_CLK 83 -#define CAMSS_PHY2_CSI2PHYTIMER_CLK 84 -#define CAMSS_TOP_AHB_CLK 85 -#define CAMSS_VFE_CPP_AHB_CLK 86 -#define CAMSS_VFE_CPP_CLK 87 -#define CAMSS_VFE_VFE0_CLK 88 -#define CAMSS_VFE_VFE1_CLK 89 -#define CAMSS_VFE_VFE_AHB_CLK 90 -#define CAMSS_VFE_VFE_AXI_CLK 91 -#define CAMSS_VFE_VFE_OCMEMNOC_CLK 92 -#define MDSS_AHB_CLK 93 -#define MDSS_AXI_CLK 94 -#define MDSS_BYTE0_CLK 95 -#define MDSS_BYTE1_CLK 96 -#define MDSS_EDPAUX_CLK 97 -#define MDSS_EDPLINK_CLK 98 -#define MDSS_EDPPIXEL_CLK 99 -#define MDSS_ESC0_CLK 100 -#define MDSS_ESC1_CLK 101 -#define MDSS_EXTPCLK_CLK 102 -#define MDSS_HDMI_AHB_CLK 103 -#define MDSS_HDMI_CLK 104 -#define MDSS_MDP_CLK 105 -#define MDSS_MDP_LUT_CLK 106 -#define MDSS_PCLK0_CLK 107 -#define MDSS_PCLK1_CLK 108 -#define MDSS_VSYNC_CLK 109 -#define MMSS_MISC_AHB_CLK 110 -#define MMSS_MMSSNOC_AHB_CLK 111 -#define MMSS_MMSSNOC_BTO_AHB_CLK 112 -#define MMSS_MMSSNOC_AXI_CLK 113 -#define MMSS_S0_AXI_CLK 114 -#define OCMEMCX_AHB_CLK 115 -#define OCMEMCX_OCMEMNOC_CLK 116 -#define OXILI_OCMEMGX_CLK 117 -#define OCMEMNOC_CLK 118 -#define OXILI_GFX3D_CLK 119 -#define OXILICX_AHB_CLK 120 -#define OXILICX_AXI_CLK 121 -#define VENUS0_AHB_CLK 122 -#define VENUS0_AXI_CLK 123 -#define VENUS0_OCMEMNOC_CLK 124 -#define VENUS0_VCODEC0_CLK 125 -#define OCMEMNOC_CLK_SRC 126 -#define SPDM_JPEG0 127 -#define SPDM_JPEG1 128 -#define SPDM_MDP 129 -#define SPDM_AXI 130 -#define SPDM_VCODEC0 131 -#define SPDM_VFE0 132 -#define SPDM_VFE1 133 -#define SPDM_JPEG2 134 -#define SPDM_PCLK1 135 -#define SPDM_GFX3D 136 -#define SPDM_AHB 137 -#define SPDM_PCLK0 138 -#define SPDM_OCMEMNOC 139 -#define SPDM_CSI0 140 -#define SPDM_RM_AXI 141 -#define SPDM_RM_OCMEMNOC 142 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h b/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a87343..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h deleted file mode 100644 index ad95c7f..0000000 --- a/sys/gnu/dts/include/dt-bindings/clock/samsung,s3c64xx-clock.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2013 Tomasz Figa - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Samsung S3C64xx clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H -#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H - -/* - * Let each exported clock get a unique index, which is used on DT-enabled - * platforms to lookup the clock from a clock specifier. These indices are - * therefore considered an ABI and so must not be changed. This implies - * that new clocks should be added either in free spaces between clock groups - * or at the end. - */ - -/* Core clocks. */ -#define CLK27M 1 -#define CLK48M 2 -#define FOUT_APLL 3 -#define FOUT_MPLL 4 -#define FOUT_EPLL 5 -#define ARMCLK 6 -#define HCLKX2 7 -#define HCLK 8 -#define PCLK 9 - -/* HCLK bus clocks. */ -#define HCLK_3DSE 16 -#define HCLK_UHOST 17 -#define HCLK_SECUR 18 -#define HCLK_SDMA1 19 -#define HCLK_SDMA0 20 -#define HCLK_IROM 21 -#define HCLK_DDR1 22 -#define HCLK_MEM1 23 -#define HCLK_MEM0 24 -#define HCLK_USB 25 -#define HCLK_HSMMC2 26 -#define HCLK_HSMMC1 27 -#define HCLK_HSMMC0 28 -#define HCLK_MDP 29 -#define HCLK_DHOST 30 -#define HCLK_IHOST 31 -#define HCLK_DMA1 32 -#define HCLK_DMA0 33 -#define HCLK_JPEG 34 -#define HCLK_CAMIF 35 -#define HCLK_SCALER 36 -#define HCLK_2D 37 -#define HCLK_TV 38 -#define HCLK_POST0 39 -#define HCLK_ROT 40 -#define HCLK_LCD 41 -#define HCLK_TZIC 42 -#define HCLK_INTC 43 -#define HCLK_MFC 44 -#define HCLK_DDR0 45 - -/* PCLK bus clocks. */ -#define PCLK_IIC1 48 -#define PCLK_IIS2 49 -#define PCLK_SKEY 50 -#define PCLK_CHIPID 51 -#define PCLK_SPI1 52 -#define PCLK_SPI0 53 -#define PCLK_HSIRX 54 -#define PCLK_HSITX 55 -#define PCLK_GPIO 56 -#define PCLK_IIC0 57 -#define PCLK_IIS1 58 -#define PCLK_IIS0 59 -#define PCLK_AC97 60 -#define PCLK_TZPC 61 -#define PCLK_TSADC 62 -#define PCLK_KEYPAD 63 -#define PCLK_IRDA 64 -#define PCLK_PCM1 65 -#define PCLK_PCM0 66 -#define PCLK_PWM 67 -#define PCLK_RTC 68 -#define PCLK_WDT 69 -#define PCLK_UART3 70 -#define PCLK_UART2 71 -#define PCLK_UART1 72 -#define PCLK_UART0 73 -#define PCLK_MFC 74 - -/* Special clocks. */ -#define SCLK_UHOST 80 -#define SCLK_MMC2_48 81 -#define SCLK_MMC1_48 82 -#define SCLK_MMC0_48 83 -#define SCLK_MMC2 84 -#define SCLK_MMC1 85 -#define SCLK_MMC0 86 -#define SCLK_SPI1_48 87 -#define SCLK_SPI0_48 88 -#define SCLK_SPI1 89 -#define SCLK_SPI0 90 -#define SCLK_DAC27 91 -#define SCLK_TV27 92 -#define SCLK_SCALER27 93 -#define SCLK_SCALER 94 -#define SCLK_LCD27 95 -#define SCLK_LCD 96 -#define SCLK_FIMC 97 -#define SCLK_POST0_27 98 -#define SCLK_AUDIO2 99 -#define SCLK_POST0 100 -#define SCLK_AUDIO1 101 -#define SCLK_AUDIO0 102 -#define SCLK_SECUR 103 -#define SCLK_IRDA 104 -#define SCLK_UART 105 -#define SCLK_MFC 106 -#define SCLK_CAM 107 -#define SCLK_JPEG 108 -#define SCLK_ONENAND 109 - -/* MEM0 bus clocks - S3C6410-specific. */ -#define MEM0_CFCON 112 -#define MEM0_ONENAND1 113 -#define MEM0_ONENAND0 114 -#define MEM0_NFCON 115 -#define MEM0_SROM 116 - -/* Muxes. */ -#define MOUT_APLL 128 -#define MOUT_MPLL 129 -#define MOUT_EPLL 130 -#define MOUT_MFC 131 -#define MOUT_AUDIO0 132 -#define MOUT_AUDIO1 133 -#define MOUT_UART 134 -#define MOUT_SPI0 135 -#define MOUT_SPI1 136 -#define MOUT_MMC0 137 -#define MOUT_MMC1 138 -#define MOUT_MMC2 139 -#define MOUT_UHOST 140 -#define MOUT_IRDA 141 -#define MOUT_LCD 142 -#define MOUT_SCALER 143 -#define MOUT_DAC27 144 -#define MOUT_TV27 145 -#define MOUT_AUDIO2 146 - -/* Dividers. */ -#define DOUT_MPLL 160 -#define DOUT_SECUR 161 -#define DOUT_CAM 162 -#define DOUT_JPEG 163 -#define DOUT_MFC 164 -#define DOUT_MMC0 165 -#define DOUT_MMC1 166 -#define DOUT_MMC2 167 -#define DOUT_LCD 168 -#define DOUT_SCALER 169 -#define DOUT_UHOST 170 -#define DOUT_SPI0 171 -#define DOUT_SPI1 172 -#define DOUT_AUDIO0 173 -#define DOUT_AUDIO1 174 -#define DOUT_UART 175 -#define DOUT_IRDA 176 -#define DOUT_FIMC 177 -#define DOUT_AUDIO2 178 - -/* Total number of clocks. */ -#define NR_CLKS (DOUT_AUDIO2 + 1) - -#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ diff --git a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h b/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h deleted file mode 100644 index 42121fa..0000000 --- a/sys/gnu/dts/include/dt-bindings/iio/qcom,spmi-vadc.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H -#define _DT_BINDINGS_QCOM_SPMI_VADC_H - -/* Voltage ADC channels */ -#define VADC_USBIN 0x00 -#define VADC_DCIN 0x01 -#define VADC_VCHG_SNS 0x02 -#define VADC_SPARE1_03 0x03 -#define VADC_USB_ID_MV 0x04 -#define VADC_VCOIN 0x05 -#define VADC_VBAT_SNS 0x06 -#define VADC_VSYS 0x07 -#define VADC_DIE_TEMP 0x08 -#define VADC_REF_625MV 0x09 -#define VADC_REF_1250MV 0x0a -#define VADC_CHG_TEMP 0x0b -#define VADC_SPARE1 0x0c -#define VADC_SPARE2 0x0d -#define VADC_GND_REF 0x0e -#define VADC_VDD_VADC 0x0f - -#define VADC_P_MUX1_1_1 0x10 -#define VADC_P_MUX2_1_1 0x11 -#define VADC_P_MUX3_1_1 0x12 -#define VADC_P_MUX4_1_1 0x13 -#define VADC_P_MUX5_1_1 0x14 -#define VADC_P_MUX6_1_1 0x15 -#define VADC_P_MUX7_1_1 0x16 -#define VADC_P_MUX8_1_1 0x17 -#define VADC_P_MUX9_1_1 0x18 -#define VADC_P_MUX10_1_1 0x19 -#define VADC_P_MUX11_1_1 0x1a -#define VADC_P_MUX12_1_1 0x1b -#define VADC_P_MUX13_1_1 0x1c -#define VADC_P_MUX14_1_1 0x1d -#define VADC_P_MUX15_1_1 0x1e -#define VADC_P_MUX16_1_1 0x1f - -#define VADC_P_MUX1_1_3 0x20 -#define VADC_P_MUX2_1_3 0x21 -#define VADC_P_MUX3_1_3 0x22 -#define VADC_P_MUX4_1_3 0x23 -#define VADC_P_MUX5_1_3 0x24 -#define VADC_P_MUX6_1_3 0x25 -#define VADC_P_MUX7_1_3 0x26 -#define VADC_P_MUX8_1_3 0x27 -#define VADC_P_MUX9_1_3 0x28 -#define VADC_P_MUX10_1_3 0x29 -#define VADC_P_MUX11_1_3 0x2a -#define VADC_P_MUX12_1_3 0x2b -#define VADC_P_MUX13_1_3 0x2c -#define VADC_P_MUX14_1_3 0x2d -#define VADC_P_MUX15_1_3 0x2e -#define VADC_P_MUX16_1_3 0x2f - -#define VADC_LR_MUX1_BAT_THERM 0x30 -#define VADC_LR_MUX2_BAT_ID 0x31 -#define VADC_LR_MUX3_XO_THERM 0x32 -#define VADC_LR_MUX4_AMUX_THM1 0x33 -#define VADC_LR_MUX5_AMUX_THM2 0x34 -#define VADC_LR_MUX6_AMUX_THM3 0x35 -#define VADC_LR_MUX7_HW_ID 0x36 -#define VADC_LR_MUX8_AMUX_THM4 0x37 -#define VADC_LR_MUX9_AMUX_THM5 0x38 -#define VADC_LR_MUX10_USB_ID 0x39 -#define VADC_AMUX_PU1 0x3a -#define VADC_AMUX_PU2 0x3b -#define VADC_LR_MUX3_BUF_XO_THERM 0x3c - -#define VADC_LR_MUX1_PU1_BAT_THERM 0x70 -#define VADC_LR_MUX2_PU1_BAT_ID 0x71 -#define VADC_LR_MUX3_PU1_XO_THERM 0x72 -#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73 -#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74 -#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75 -#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76 -#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77 -#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78 -#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79 -#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c - -#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0 -#define VADC_LR_MUX2_PU2_BAT_ID 0xb1 -#define VADC_LR_MUX3_PU2_XO_THERM 0xb2 -#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3 -#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4 -#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5 -#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6 -#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7 -#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8 -#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9 -#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc - -#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0 -#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1 -#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2 -#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3 -#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4 -#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5 -#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6 -#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7 -#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8 -#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 -#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc - -#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h deleted file mode 100644 index fa74d7c..0000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * This header provides constants for the Qualcomm PMIC GPIO binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H - -#define PMIC_GPIO_PULL_UP_30 0 -#define PMIC_GPIO_PULL_UP_1P5 1 -#define PMIC_GPIO_PULL_UP_31P5 2 -#define PMIC_GPIO_PULL_UP_1P5_30 3 - -#define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 -#define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 - -/* - * Note: PM8018 GPIO3 and GPIO4 are supporting - * only S3 and L2 options (1.8V) - */ -#define PM8018_GPIO_L6 0 -#define PM8018_GPIO_L5 1 -#define PM8018_GPIO_S3 2 -#define PM8018_GPIO_L14 3 -#define PM8018_GPIO_L2 4 -#define PM8018_GPIO_L4 5 -#define PM8018_GPIO_VDD 6 - -/* - * Note: PM8038 GPIO7 and GPIO8 are supporting - * only L11 and L4 options (1.8V) - */ -#define PM8038_GPIO_VPH 0 -#define PM8038_GPIO_BB 1 -#define PM8038_GPIO_L11 2 -#define PM8038_GPIO_L15 3 -#define PM8038_GPIO_L4 4 -#define PM8038_GPIO_L3 5 -#define PM8038_GPIO_L17 6 - -#define PM8058_GPIO_VPH 0 -#define PM8058_GPIO_BB 1 -#define PM8058_GPIO_S3 2 -#define PM8058_GPIO_L3 3 -#define PM8058_GPIO_L7 4 -#define PM8058_GPIO_L6 5 -#define PM8058_GPIO_L5 6 -#define PM8058_GPIO_L2 7 - -#define PM8917_GPIO_VPH 0 -#define PM8917_GPIO_S4 2 -#define PM8917_GPIO_L15 3 -#define PM8917_GPIO_L4 4 -#define PM8917_GPIO_L3 5 -#define PM8917_GPIO_L17 6 - -#define PM8921_GPIO_VPH 0 -#define PM8921_GPIO_BB 1 -#define PM8921_GPIO_S4 2 -#define PM8921_GPIO_L15 3 -#define PM8921_GPIO_L4 4 -#define PM8921_GPIO_L3 5 -#define PM8921_GPIO_L17 6 - -/* - * Note: PM8941 gpios from 15 to 18 are supporting - * only S3 and L6 options (1.8V) - */ -#define PM8941_GPIO_VPH 0 -#define PM8941_GPIO_L1 1 -#define PM8941_GPIO_S3 2 -#define PM8941_GPIO_L6 3 - -/* - * Note: PMA8084 gpios from 15 to 18 are supporting - * only S4 and L6 options (1.8V) - */ -#define PMA8084_GPIO_VPH 0 -#define PMA8084_GPIO_L1 1 -#define PMA8084_GPIO_S4 2 -#define PMA8084_GPIO_L6 3 - -/* To be used with "function" */ -#define PMIC_GPIO_FUNC_NORMAL "normal" -#define PMIC_GPIO_FUNC_PAIRED "paired" -#define PMIC_GPIO_FUNC_FUNC1 "func1" -#define PMIC_GPIO_FUNC_FUNC2 "func2" -#define PMIC_GPIO_FUNC_DTEST1 "dtest1" -#define PMIC_GPIO_FUNC_DTEST2 "dtest2" -#define PMIC_GPIO_FUNC_DTEST3 "dtest3" -#define PMIC_GPIO_FUNC_DTEST4 "dtest4" - -#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 - -#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 -#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 - -#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 -#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 - -#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 -#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 -#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 - -#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 -#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 -#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h deleted file mode 100644 index d2c7dab..0000000 --- a/sys/gnu/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This header provides constants for the Qualcomm PMIC's - * Multi-Purpose Pin binding. - */ - -#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H -#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H - -/* power-source */ -#define PM8841_MPP_VPH 0 -#define PM8841_MPP_S3 2 - -#define PM8941_MPP_VPH 0 -#define PM8941_MPP_L1 1 -#define PM8941_MPP_S3 2 -#define PM8941_MPP_L6 3 - -#define PMA8084_MPP_VPH 0 -#define PMA8084_MPP_L1 1 -#define PMA8084_MPP_S4 2 -#define PMA8084_MPP_L6 3 - -/* - * Analog Input - Set the source for analog input. - * To be used with "qcom,amux-route" property - */ -#define PMIC_MPP_AMUX_ROUTE_CH5 0 -#define PMIC_MPP_AMUX_ROUTE_CH6 1 -#define PMIC_MPP_AMUX_ROUTE_CH7 2 -#define PMIC_MPP_AMUX_ROUTE_CH8 3 -#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 -#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 -#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 -#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 - -/* To be used with "function" */ -#define PMIC_MPP_FUNC_NORMAL "normal" -#define PMIC_MPP_FUNC_PAIRED "paired" -#define PMIC_MPP_FUNC_DTEST1 "dtest1" -#define PMIC_MPP_FUNC_DTEST2 "dtest2" -#define PMIC_MPP_FUNC_DTEST3 "dtest3" -#define PMIC_MPP_FUNC_DTEST4 "dtest4" - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h b/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h deleted file mode 100644 index cf28631..0000000 --- a/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for the Maxim 77802 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H -#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H - -/* Regulator operating modes */ -#define MAX77802_OPMODE_LP 1 -#define MAX77802_OPMODE_NORMAL 3 - -#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h b/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 3f04908..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2014, Steffen Trumtrar - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h deleted file mode 100644 index 527caaf..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-apq8084.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H -#define _DT_BINDINGS_RESET_APQ_GCC_8084_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_BAM_DMA_BCR 44 -#define GCC_TSIF_BCR 45 -#define GCC_TCSR_BCR 46 -#define GCC_BOOT_ROM_BCR 47 -#define GCC_MSG_RAM_BCR 48 -#define GCC_TLMM_BCR 49 -#define GCC_MPM_BCR 50 -#define GCC_MPM_AHB_RESET 51 -#define GCC_MPM_NON_AHB_RESET 52 -#define GCC_SEC_CTRL_BCR 53 -#define GCC_SPMI_BCR 54 -#define GCC_SPDM_BCR 55 -#define GCC_CE1_BCR 56 -#define GCC_CE2_BCR 57 -#define GCC_BIMC_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 -#define GCC_DEHR_BCR 73 -#define GCC_RBCPR_BCR 74 -#define GCC_MSS_RESTART 75 -#define GCC_LPASS_RESTART 76 -#define GCC_WCSS_RESTART 77 -#define GCC_VENUS_RESTART 78 -#define GCC_COPSS_SMMU_BCR 79 -#define GCC_SPSS_BCR 80 -#define GCC_PCIE_0_BCR 81 -#define GCC_PCIE_0_PHY_BCR 82 -#define GCC_PCIE_1_BCR 83 -#define GCC_PCIE_1_PHY_BCR 84 -#define GCC_USB_30_SEC_BCR 85 -#define GCC_USB3_SEC_PHY_BCR 86 -#define GCC_SATA_BCR 87 -#define GCC_CE3_BCR 88 -#define GCC_UFS_BCR 89 -#define GCC_USB30_PHY_COM_BCR 90 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h deleted file mode 100644 index 0ad5ef9..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_806X_H -#define _DT_BINDINGS_RESET_IPQ_806X_H - -#define QDSS_STM_RESET 0 -#define AFAB_SMPSS_S_RESET 1 -#define AFAB_SMPSS_M1_RESET 2 -#define AFAB_SMPSS_M0_RESET 3 -#define AFAB_EBI1_CH0_RESET 4 -#define AFAB_EBI1_CH1_RESET 5 -#define SFAB_ADM0_M0_RESET 6 -#define SFAB_ADM0_M1_RESET 7 -#define SFAB_ADM0_M2_RESET 8 -#define ADM0_C2_RESET 9 -#define ADM0_C1_RESET 10 -#define ADM0_C0_RESET 11 -#define ADM0_PBUS_RESET 12 -#define ADM0_RESET 13 -#define QDSS_CLKS_SW_RESET 14 -#define QDSS_POR_RESET 15 -#define QDSS_TSCTR_RESET 16 -#define QDSS_HRESET_RESET 17 -#define QDSS_AXI_RESET 18 -#define QDSS_DBG_RESET 19 -#define SFAB_PCIE_M_RESET 20 -#define SFAB_PCIE_S_RESET 21 -#define PCIE_EXT_RESET 22 -#define PCIE_PHY_RESET 23 -#define PCIE_PCI_RESET 24 -#define PCIE_POR_RESET 25 -#define PCIE_HCLK_RESET 26 -#define PCIE_ACLK_RESET 27 -#define SFAB_LPASS_RESET 28 -#define SFAB_AFAB_M_RESET 29 -#define AFAB_SFAB_M0_RESET 30 -#define AFAB_SFAB_M1_RESET 31 -#define SFAB_SATA_S_RESET 32 -#define SFAB_DFAB_M_RESET 33 -#define DFAB_SFAB_M_RESET 34 -#define DFAB_SWAY0_RESET 35 -#define DFAB_SWAY1_RESET 36 -#define DFAB_ARB0_RESET 37 -#define DFAB_ARB1_RESET 38 -#define PPSS_PROC_RESET 39 -#define PPSS_RESET 40 -#define DMA_BAM_RESET 41 -#define SPS_TIC_H_RESET 42 -#define SFAB_CFPB_M_RESET 43 -#define SFAB_CFPB_S_RESET 44 -#define TSIF_H_RESET 45 -#define CE1_H_RESET 46 -#define CE1_CORE_RESET 47 -#define CE1_SLEEP_RESET 48 -#define CE2_H_RESET 49 -#define CE2_CORE_RESET 50 -#define SFAB_SFPB_M_RESET 51 -#define SFAB_SFPB_S_RESET 52 -#define RPM_PROC_RESET 53 -#define PMIC_SSBI2_RESET 54 -#define SDC1_RESET 55 -#define SDC2_RESET 56 -#define SDC3_RESET 57 -#define SDC4_RESET 58 -#define USB_HS1_RESET 59 -#define USB_HSIC_RESET 60 -#define USB_FS1_XCVR_RESET 61 -#define USB_FS1_RESET 62 -#define GSBI1_RESET 63 -#define GSBI2_RESET 64 -#define GSBI3_RESET 65 -#define GSBI4_RESET 66 -#define GSBI5_RESET 67 -#define GSBI6_RESET 68 -#define GSBI7_RESET 69 -#define SPDM_RESET 70 -#define SEC_CTRL_RESET 71 -#define TLMM_H_RESET 72 -#define SFAB_SATA_M_RESET 73 -#define SATA_RESET 74 -#define TSSC_RESET 75 -#define PDM_RESET 76 -#define MPM_H_RESET 77 -#define MPM_RESET 78 -#define SFAB_SMPSS_S_RESET 79 -#define PRNG_RESET 80 -#define SFAB_CE3_M_RESET 81 -#define SFAB_CE3_S_RESET 82 -#define CE3_SLEEP_RESET 83 -#define PCIE_1_M_RESET 84 -#define PCIE_1_S_RESET 85 -#define PCIE_1_EXT_RESET 86 -#define PCIE_1_PHY_RESET 87 -#define PCIE_1_PCI_RESET 88 -#define PCIE_1_POR_RESET 89 -#define PCIE_1_HCLK_RESET 90 -#define PCIE_1_ACLK_RESET 91 -#define PCIE_2_M_RESET 92 -#define PCIE_2_S_RESET 93 -#define PCIE_2_EXT_RESET 94 -#define PCIE_2_PHY_RESET 95 -#define PCIE_2_PCI_RESET 96 -#define PCIE_2_POR_RESET 97 -#define PCIE_2_HCLK_RESET 98 -#define PCIE_2_ACLK_RESET 99 -#define SFAB_USB30_S_RESET 100 -#define SFAB_USB30_M_RESET 101 -#define USB30_0_PORT2_HS_PHY_RESET 102 -#define USB30_0_MASTER_RESET 103 -#define USB30_0_SLEEP_RESET 104 -#define USB30_0_UTMI_PHY_RESET 105 -#define USB30_0_POWERON_RESET 106 -#define USB30_0_PHY_RESET 107 -#define USB30_1_MASTER_RESET 108 -#define USB30_1_SLEEP_RESET 109 -#define USB30_1_UTMI_PHY_RESET 110 -#define USB30_1_POWERON_RESET 111 -#define USB30_1_PHY_RESET 112 -#define NSSFB0_RESET 113 -#define NSSFB1_RESET 114 -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h deleted file mode 100644 index a83282f..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8660.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H -#define _DT_BINDINGS_RESET_MSM_GCC_8660_H - -#define AFAB_CORE_RESET 0 -#define SCSS_SYS_RESET 1 -#define SCSS_SYS_POR_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_S_RESET 6 -#define SFAB_CORE_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define SFAB_ADM1_M0_RESET 16 -#define SFAB_ADM1_M1_RESET 17 -#define SFAB_ADM1_M2_RESET 18 -#define MMFAB_ADM1_M3_RESET 19 -#define ADM1_C3_RESET 20 -#define ADM1_C2_RESET 21 -#define ADM1_C1_RESET 22 -#define ADM1_C0_RESET 23 -#define ADM1_PBUS_RESET 24 -#define ADM1_RESET 25 -#define IMEM0_RESET 26 -#define SFAB_LPASS_Q6_RESET 27 -#define SFAB_AFAB_M_RESET 28 -#define AFAB_SFAB_M0_RESET 29 -#define AFAB_SFAB_M1_RESET 30 -#define DFAB_CORE_RESET 31 -#define SFAB_DFAB_M_RESET 32 -#define DFAB_SFAB_M_RESET 33 -#define DFAB_SWAY0_RESET 34 -#define DFAB_SWAY1_RESET 35 -#define DFAB_ARB0_RESET 36 -#define DFAB_ARB1_RESET 37 -#define PPSS_PROC_RESET 38 -#define PPSS_RESET 39 -#define PMEM_RESET 40 -#define DMA_BAM_RESET 41 -#define SIC_RESET 42 -#define SPS_TIC_RESET 43 -#define CFBP0_RESET 44 -#define CFBP1_RESET 45 -#define CFBP2_RESET 46 -#define EBI2_RESET 47 -#define SFAB_CFPB_M_RESET 48 -#define CFPB_MASTER_RESET 49 -#define SFAB_CFPB_S_RESET 50 -#define CFPB_SPLITTER_RESET 51 -#define TSIF_RESET 52 -#define CE1_RESET 53 -#define CE2_RESET 54 -#define SFAB_SFPB_M_RESET 55 -#define SFAB_SFPB_S_RESET 56 -#define RPM_PROC_RESET 57 -#define RPM_BUS_RESET 58 -#define RPM_MSG_RAM_RESET 59 -#define PMIC_ARB0_RESET 60 -#define PMIC_ARB1_RESET 61 -#define PMIC_SSBI2_RESET 62 -#define SDC1_RESET 63 -#define SDC2_RESET 64 -#define SDC3_RESET 65 -#define SDC4_RESET 66 -#define SDC5_RESET 67 -#define USB_HS1_RESET 68 -#define USB_HS2_XCVR_RESET 69 -#define USB_HS2_RESET 70 -#define USB_FS1_XCVR_RESET 71 -#define USB_FS1_RESET 72 -#define USB_FS2_XCVR_RESET 73 -#define USB_FS2_RESET 74 -#define GSBI1_RESET 75 -#define GSBI2_RESET 76 -#define GSBI3_RESET 77 -#define GSBI4_RESET 78 -#define GSBI5_RESET 79 -#define GSBI6_RESET 80 -#define GSBI7_RESET 81 -#define GSBI8_RESET 82 -#define GSBI9_RESET 83 -#define GSBI10_RESET 84 -#define GSBI11_RESET 85 -#define GSBI12_RESET 86 -#define SPDM_RESET 87 -#define SEC_CTRL_RESET 88 -#define TLMM_H_RESET 89 -#define TLMM_RESET 90 -#define MARRM_PWRON_RESET 91 -#define MARM_RESET 92 -#define MAHB1_RESET 93 -#define SFAB_MSS_S_RESET 94 -#define MAHB2_RESET 95 -#define MODEM_SW_AHB_RESET 96 -#define MODEM_RESET 97 -#define SFAB_MSS_MDM1_RESET 98 -#define SFAB_MSS_MDM0_RESET 99 -#define MSS_SLP_RESET 100 -#define MSS_MARM_SAW_RESET 101 -#define MSS_WDOG_RESET 102 -#define TSSC_RESET 103 -#define PDM_RESET 104 -#define SCSS_CORE0_RESET 105 -#define SCSS_CORE0_POR_RESET 106 -#define SCSS_CORE1_RESET 107 -#define SCSS_CORE1_POR_RESET 108 -#define MPM_RESET 109 -#define EBI1_1X_DIV_RESET 110 -#define EBI1_RESET 111 -#define SFAB_SMPSS_S_RESET 112 -#define USB_PHY0_RESET 113 -#define USB_PHY1_RESET 114 -#define PRNG_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h deleted file mode 100644 index 47c8686..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H -#define _DT_BINDINGS_RESET_MSM_GCC_8960_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h deleted file mode 100644 index 9bdf543..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,gcc-msm8974.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H -#define _DT_BINDINGS_RESET_MSM_GCC_8974_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_BAM_DMA_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_CE2_BCR 54 -#define GCC_BIMC_BCR 55 -#define GCC_MPM_NON_AHB_RESET 56 -#define GCC_MPM_AHB_RESET 57 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_DEHR_BCR 72 -#define GCC_RBCPR_BCR 73 -#define GCC_MSS_RESTART 74 -#define GCC_LPASS_RESTART 75 -#define GCC_WCSS_RESTART 76 -#define GCC_VENUS_RESTART 77 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h deleted file mode 100644 index c167139..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H -#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H - -#define MMSS_SPDM_RESET 0 -#define MMSS_SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define VPU_RESET 3 -#define MDSS_RESET 4 -#define AVSYNC_RESET 5 -#define CAMSS_PHY0_RESET 6 -#define CAMSS_PHY1_RESET 7 -#define CAMSS_PHY2_RESET 8 -#define CAMSS_CSI0_RESET 9 -#define CAMSS_CSI0PHY_RESET 10 -#define CAMSS_CSI0RDI_RESET 11 -#define CAMSS_CSI0PIX_RESET 12 -#define CAMSS_CSI1_RESET 13 -#define CAMSS_CSI1PHY_RESET 14 -#define CAMSS_CSI1RDI_RESET 15 -#define CAMSS_CSI1PIX_RESET 16 -#define CAMSS_CSI2_RESET 17 -#define CAMSS_CSI2PHY_RESET 18 -#define CAMSS_CSI2RDI_RESET 19 -#define CAMSS_CSI2PIX_RESET 20 -#define CAMSS_CSI3_RESET 21 -#define CAMSS_CSI3PHY_RESET 22 -#define CAMSS_CSI3RDI_RESET 23 -#define CAMSS_CSI3PIX_RESET 24 -#define CAMSS_ISPIF_RESET 25 -#define CAMSS_CCI_RESET 26 -#define CAMSS_MCLK0_RESET 27 -#define CAMSS_MCLK1_RESET 28 -#define CAMSS_MCLK2_RESET 29 -#define CAMSS_MCLK3_RESET 30 -#define CAMSS_GP0_RESET 31 -#define CAMSS_GP1_RESET 32 -#define CAMSS_TOP_RESET 33 -#define CAMSS_AHB_RESET 34 -#define CAMSS_MICRO_RESET 35 -#define CAMSS_JPEG_RESET 36 -#define CAMSS_VFE_RESET 37 -#define CAMSS_CSI_VFE0_RESET 38 -#define CAMSS_CSI_VFE1_RESET 39 -#define OXILI_RESET 40 -#define OXILICX_RESET 41 -#define OCMEMCX_RESET 42 -#define MMSS_RBCRP_RESET 43 -#define MMSSNOCAHB_RESET 44 -#define MMSSNOCAXI_RESET 45 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h deleted file mode 100644 index 1174111..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H - -#define VPE_AXI_RESET 0 -#define IJPEG_AXI_RESET 1 -#define MPD_AXI_RESET 2 -#define VFE_AXI_RESET 3 -#define SP_AXI_RESET 4 -#define VCODEC_AXI_RESET 5 -#define ROT_AXI_RESET 6 -#define VCODEC_AXI_A_RESET 7 -#define VCODEC_AXI_B_RESET 8 -#define FAB_S3_AXI_RESET 9 -#define FAB_S2_AXI_RESET 10 -#define FAB_S1_AXI_RESET 11 -#define FAB_S0_AXI_RESET 12 -#define SMMU_GFX3D_ABH_RESET 13 -#define SMMU_VPE_AHB_RESET 14 -#define SMMU_VFE_AHB_RESET 15 -#define SMMU_ROT_AHB_RESET 16 -#define SMMU_VCODEC_B_AHB_RESET 17 -#define SMMU_VCODEC_A_AHB_RESET 18 -#define SMMU_MDP1_AHB_RESET 19 -#define SMMU_MDP0_AHB_RESET 20 -#define SMMU_JPEGD_AHB_RESET 21 -#define SMMU_IJPEG_AHB_RESET 22 -#define SMMU_GFX2D0_AHB_RESET 23 -#define SMMU_GFX2D1_AHB_RESET 24 -#define APU_AHB_RESET 25 -#define CSI_AHB_RESET 26 -#define TV_ENC_AHB_RESET 27 -#define VPE_AHB_RESET 28 -#define FABRIC_AHB_RESET 29 -#define GFX2D0_AHB_RESET 30 -#define GFX2D1_AHB_RESET 31 -#define GFX3D_AHB_RESET 32 -#define HDMI_AHB_RESET 33 -#define MSSS_IMEM_AHB_RESET 34 -#define IJPEG_AHB_RESET 35 -#define DSI_M_AHB_RESET 36 -#define DSI_S_AHB_RESET 37 -#define JPEGD_AHB_RESET 38 -#define MDP_AHB_RESET 39 -#define ROT_AHB_RESET 40 -#define VCODEC_AHB_RESET 41 -#define VFE_AHB_RESET 42 -#define DSI2_M_AHB_RESET 43 -#define DSI2_S_AHB_RESET 44 -#define CSIPHY2_RESET 45 -#define CSI_PIX1_RESET 46 -#define CSIPHY0_RESET 47 -#define CSIPHY1_RESET 48 -#define DSI2_RESET 49 -#define VFE_CSI_RESET 50 -#define MDP_RESET 51 -#define AMP_RESET 52 -#define JPEGD_RESET 53 -#define CSI1_RESET 54 -#define VPE_RESET 55 -#define MMSS_FABRIC_RESET 56 -#define VFE_RESET 57 -#define GFX2D0_RESET 58 -#define GFX2D1_RESET 59 -#define GFX3D_RESET 60 -#define HDMI_RESET 61 -#define MMSS_IMEM_RESET 62 -#define IJPEG_RESET 63 -#define CSI0_RESET 64 -#define DSI_RESET 65 -#define VCODEC_RESET 66 -#define MDP_TV_RESET 67 -#define MDP_VSYNC_RESET 68 -#define ROT_RESET 69 -#define TV_HDMI_RESET 70 -#define TV_ENC_RESET 71 -#define CSI2_RESET 72 -#define CSI_RDI1_RESET 73 -#define CSI_RDI2_RESET 74 -#define GFX3D_AXI_RESET 75 -#define VCAP_AXI_RESET 76 -#define SMMU_VCAP_AHB_RESET 77 -#define VCAP_AHB_RESET 78 -#define CSI_RDI_RESET 79 -#define CSI_PIX_RESET 80 -#define VCAP_NPL_RESET 81 -#define VCAP_RESET 82 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h deleted file mode 100644 index da3ec37..0000000 --- a/sys/gnu/dts/include/dt-bindings/reset/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H - -#define SPDM_RESET 0 -#define SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define MDSS_RESET 3 -#define CAMSS_PHY0_RESET 4 -#define CAMSS_PHY1_RESET 5 -#define CAMSS_PHY2_RESET 6 -#define CAMSS_CSI0_RESET 7 -#define CAMSS_CSI0PHY_RESET 8 -#define CAMSS_CSI0RDI_RESET 9 -#define CAMSS_CSI0PIX_RESET 10 -#define CAMSS_CSI1_RESET 11 -#define CAMSS_CSI1PHY_RESET 12 -#define CAMSS_CSI1RDI_RESET 13 -#define CAMSS_CSI1PIX_RESET 14 -#define CAMSS_CSI2_RESET 15 -#define CAMSS_CSI2PHY_RESET 16 -#define CAMSS_CSI2RDI_RESET 17 -#define CAMSS_CSI2PIX_RESET 18 -#define CAMSS_CSI3_RESET 19 -#define CAMSS_CSI3PHY_RESET 20 -#define CAMSS_CSI3RDI_RESET 21 -#define CAMSS_CSI3PIX_RESET 22 -#define CAMSS_ISPIF_RESET 23 -#define CAMSS_CCI_RESET 24 -#define CAMSS_MCLK0_RESET 25 -#define CAMSS_MCLK1_RESET 26 -#define CAMSS_MCLK2_RESET 27 -#define CAMSS_MCLK3_RESET 28 -#define CAMSS_GP0_RESET 29 -#define CAMSS_GP1_RESET 30 -#define CAMSS_TOP_RESET 31 -#define CAMSS_MICRO_RESET 32 -#define CAMSS_JPEG_RESET 33 -#define CAMSS_VFE_RESET 34 -#define CAMSS_CSI_VFE0_RESET 35 -#define CAMSS_CSI_VFE1_RESET 36 -#define OXILI_RESET 37 -#define OXILICX_RESET 38 -#define OCMEMCX_RESET 39 -#define MMSS_RBCRP_RESET 40 -#define MMSSNOCAHB_RESET 41 -#define MMSSNOCAXI_RESET 42 -#define OCMEMNOC_RESET 43 - -#endif diff --git a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h b/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h deleted file mode 100644 index 7ac4292..0000000 --- a/sys/gnu/dts/include/dt-bindings/soc/qcom,gsbi.h +++ /dev/null @@ -1,26 +0,0 @@ -/* Copyright (c) 2013, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_QCOM_GSBI_H -#define __DT_BINDINGS_QCOM_GSBI_H - -#define GSBI_PROT_IDLE 0 -#define GSBI_PROT_I2C_UIM 1 -#define GSBI_PROT_I2C 2 -#define GSBI_PROT_SPI 3 -#define GSBI_PROT_UART_W_FC 4 -#define GSBI_PROT_UIM 5 -#define GSBI_PROT_I2C_UART 6 - -#define GSBI_CRCI_QUP 0 -#define GSBI_CRCI_UART 1 - -#endif -- cgit v1.1