From 592778f249ec299a21574b60dfdf2fb0c67a5df6 Mon Sep 17 00:00:00 2001 From: andreast Date: Sat, 2 Jan 2016 22:04:37 +0000 Subject: Fix booting of 32-bit kernels on 64-bit G5 hardware. For rs6000, most memory insns and addi/addis do not allow GPR0 for RA (they use literal zero there instead). So use a 'b' constraint to make sure to have a base register other than GPR0. GCC-4.7 and up handles this with allocating r9 instead of r0. --- sys/powerpc/aim/mp_cpudep.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sys/powerpc/aim/mp_cpudep.c b/sys/powerpc/aim/mp_cpudep.c index 59a24e2..cedf53b 100644 --- a/sys/powerpc/aim/mp_cpudep.c +++ b/sys/powerpc/aim/mp_cpudep.c @@ -77,10 +77,10 @@ cpudep_ap_early_bootstrap(void) #else __asm __volatile("ld %0, 16(%2); sync; isync; \ mtspr %1, %0; sync; isync;" - : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state)); __asm __volatile("ld %0, 24(%2); sync; isync; \ mtspr %1, %0; sync; isync;" - : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state)); #endif powerpc_sync(); break; @@ -324,10 +324,10 @@ cpudep_ap_setup() mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ sync; isync" - : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state)); __asm __volatile("ld %0, 8(%2); sync; isync; \ mtspr %1, %0; mtspr %1, %0; sync; isync" - : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state)); + : "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state)); #endif powerpc_sync(); -- cgit v1.1