From 5678742cc6736e572768d3cff00c1190bfe666fc Mon Sep 17 00:00:00 2001 From: kato Date: Sat, 19 Apr 1997 05:25:19 +0000 Subject: Don't disable CPU cache in init_486dlc. If BIOS supports Cyrix 486, BIOS enables CPU cache and other registers. If BIOS does not supports it, CPU cache is disabled at reset time. This commit closes PR/3292. PR: 3292 --- sys/amd64/amd64/initcpu.c | 4 +--- sys/i386/i386/initcpu.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 4bd1fe5..e9ee947 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: initcpu.c,v 1.1 1997/03/22 19:00:36 kato Exp $ + * $Id: initcpu.c,v 1.2 1997/03/24 07:23:05 kato Exp $ */ #include "opt_cpu.h" @@ -100,8 +100,6 @@ init_486dlc(void) eflags = read_eflags(); disable_intr(); - - load_cr0(rcr0() | CR0_CD | CR0_NW); invd(); ccr0 = read_cyrix_reg(CCR0); diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index 4bd1fe5..e9ee947 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: initcpu.c,v 1.1 1997/03/22 19:00:36 kato Exp $ + * $Id: initcpu.c,v 1.2 1997/03/24 07:23:05 kato Exp $ */ #include "opt_cpu.h" @@ -100,8 +100,6 @@ init_486dlc(void) eflags = read_eflags(); disable_intr(); - - load_cr0(rcr0() | CR0_CD | CR0_NW); invd(); ccr0 = read_cyrix_reg(CCR0); -- cgit v1.1