From 2d954cfbd6e6e3ebc318ccfdb08e6952ed56f7e1 Mon Sep 17 00:00:00 2001 From: mav Date: Sun, 30 Nov 2008 00:11:48 +0000 Subject: According to "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant TSC. --- sys/i386/i386/identcpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c index 4f90841..67ff943 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/i386/i386/identcpu.c @@ -872,7 +872,11 @@ printcpuinfo(void) tsc_is_invariant = 1; break; case CPU_VENDOR_INTEL: - if (amd_pminfo & AMDPM_TSC_INVARIANT) + if ((amd_pminfo & AMDPM_TSC_INVARIANT) || + (I386_CPU_FAMILY(cpu_id) == 0x6 && + I386_CPU_MODEL(cpu_id) >= 0xe) || + (I386_CPU_FAMILY(cpu_id) == 0xf && + I386_CPU_MODEL(cpu_id) >= 0x3)) tsc_is_invariant = 1; break; } -- cgit v1.1