From 1e8881cf5443d3d5876679aeedef41cc645be7e9 Mon Sep 17 00:00:00 2001 From: jkim Date: Thu, 22 Jan 2009 21:04:46 +0000 Subject: VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine whether TSC is P-state invariant or not. In fact, this MSR is writable but we just leave it at the BIOS default for now. --- sys/amd64/amd64/identcpu.c | 3 ++- sys/i386/i386/identcpu.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c index 793c96f..a1112cc 100644 --- a/sys/amd64/amd64/identcpu.c +++ b/sys/amd64/amd64/identcpu.c @@ -392,7 +392,8 @@ printcpuinfo(void) break; case CPU_VENDOR_CENTAUR: if (AMD64_CPU_FAMILY(cpu_id) == 0x6 && - AMD64_CPU_MODEL(cpu_id) >= 0xf) + AMD64_CPU_MODEL(cpu_id) >= 0xf && + (rdmsr(0x1203) & 0x100000000ULL) == 0) tsc_is_invariant = 1; break; } diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c index aa37776..d2a0292 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/i386/i386/identcpu.c @@ -887,7 +887,8 @@ printcpuinfo(void) break; case CPU_VENDOR_CENTAUR: if (I386_CPU_FAMILY(cpu_id) == 0x6 && - I386_CPU_MODEL(cpu_id) >= 0xf) + I386_CPU_MODEL(cpu_id) >= 0xf && + (rdmsr(0x1203) & 0x100000000ULL) == 0) tsc_is_invariant = 1; break; } -- cgit v1.1