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* MFC 258860,260167,260238,260397:jhb2014-04-171-1/+3
| | | | | | | | | | | | | | | | - Restructure the VMX code to enter and exit the guest. In large part this change hides the setjmp/longjmp semantics of VM enter/exit. vmx_enter_guest() is used to enter guest context and vmx_exit_guest() is used to transition back into host context. Fix a longstanding race where a vcpu interrupt notification might be ignored if it happens after vmx_inject_interrupts() but before host interrupts are disabled in vmx_resume/vmx_launch. We now call vmx_inject_interrupts() with host interrupts disabled to prevent this. - The 'protection' field in the VM exit collateral for the PAGING exit is not used - get rid of it. Reviewed by: grehan
* MFC 259635:jhb2014-04-084-14/+58
| | | | | | | Add an option to ignore accesses by the guest to unimplemented MSRs. Also, ignore a couple of SandyBridge uncore PMC MSRs that Centos 6.4 writes to during boot.
* MFC 258859,259081,259085,259205,259213,259275,259482,259537,259702,259779:jhb2014-02-236-45/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several changes to the local APIC support in bhyve: - Rename 'vm_interrupt_hostcpu()' to 'vcpu_notify_event()'. - If a vcpu disables its local apic and then executes a 'HLT' then spin down the vcpu and destroy its thread context. Also modify the 'HLT' processing to ignore pending interrupts in the IRR if interrupts have been disabled by the guest. The interrupt cannot be injected into the guest in any case so resuming it is futile. - Use callout(9) to drive the vlapic timer instead of clocking it on each VM exit. - When the guest is bringing up the APs in the x2APIC mode a write to the ICR register will now trigger a return to userspace with an exitcode of VM_EXITCODE_SPINUP_AP. - Change the vlapic timer lock to be a spinlock because the vlapic can be accessed from within a critical section (vm run loop) when guest is using x2apic mode. - Fix the vlapic version register. - Add a command to bhyvectl to inject an NMI on a specific vcpu. - Add an API to deliver message signalled interrupts to vcpus. This allows callers to treat the MSI 'addr' and 'data' fields as opaque and also lets bhyve implement multiple destination modes: physical, flat and clustered. - Rename the ambiguously named 'vm_setup_msi()' and 'vm_setup_msix()' to 'vm_setup_pptdev_msi()' and 'vm_setup_pptdev_msix()' respectively. - Consolidate the virtual apic initialization in a single function: vlapic_reset() - Add a generic routine to trigger an LVT interrupt that supports both fixed and NMI delivery modes. - Add an ioctl and bhyvectl command to trigger local interrupts inside a guest. In particular, a global NMI similar to that raised by SERR# or PERR# can be simulated by asserting LINT1 on all vCPUs. - Extend the LVT table in the vCPU local APIC to support CMCI. - Flesh out the local APIC error reporting a bit to cache errors and report them via ESR when ESR is written to. Add support for asserting the error LVT when an error occurs. Raise illegal vector errors when attempting to signal an invalid vector for an interrupt or when sending an IPI. - Export table entries in the MADT and MP Table advertising the stock x86 config of LINT0 set to ExtInt and LINT1 wired to NMI.
* MFC 261607:jhb2014-02-192-0/+6
| | | | | Mark the I/O ports used by the bhyve console and debug devices as system resources.
* MFC 260206:jhb2014-01-2912-115/+417
| | | | | | Rework the DSDT generation code a bit to generate more accurate info about LPC devices. Among other things, the LPC serial ports now appear as ACPI devices.
* MFC 259826,259997,259998:jhb2014-01-2310-39/+371
| | | | | | | | | | | | | | | | | Support soft power-off via the ACPI S5 state for bhyve guests and wire up a virtual power button to SIGTERM: - Implement the PM1_EVT and PM1_CTL registers required by ACPI. - Emulate the Reset Control register at I/O port 0xcf9. - Advertise an _S5 package. - Implement an SMI_CMD register with commands to enable and disable ACPI. Currently the only change when ACPI is enabled is to enable the virtual power button via SIGTERM. - Implement a fixed-feature power button when ACPI is enabled by asserting PWRBTN_STS in PM1_EVT when SIGTERM is received. - Add support for EVFILT_SIGNAL events to mevent. - Implement support for the ACPI system command interrupt (SCI) and assert it when needed based on the values in PM1_EVT. Mark the SCI as active-low and level triggered in the MADT and MP Table.
* MFC 257422,257661,258075,258476,258494,258579,258609,258699:jhb2014-01-2310-438/+108
| | | | | | | | | | Several enhancements to the I/O APIC support in bhyve including: - Move the I/O APIC device model from userspace into vmm.ko and add ioctls to assert and deassert I/O APIC pins. - Add HPET device emulation including a single timer block with 8 timers. - Remove the 'vdev' abstraction. Approved by: neel
* MFC r260446remko2014-01-111-1/+1
| | | | | | | | virtio-block does not exist, the correct name is virtio-blk. PR: 185573 Submitted by: Allan Jude Facilitated by: Snow B.V.
* MFC 259013:jhb2013-12-241-16/+3
| | | | | | Fix the processor table entry structure to use a fixed-width type for 32-bit fields so it is the correct size on amd64. Remove a workaround for the broken structure from bhyve(8).
* MFC r259302,r259413grehan2013-12-182-2/+300
| | | | | | | | r259302 bhyve(8) man page r259413 mdoc: sort SEE ALSO
* MFC r256657,r257018,r257347,r257423,r257729,r257767,grehan2013-12-1312-99/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r257933,r258609,r258614,r258668,r258673,r258855 Pull in some minor bugfixes and functionality enhancements from CURRENT. These are candidates to be moved to 10.0-release. r258855 mdoc: quote string properly. r258673 Don't create an initial value for the host filesystem of "/". r258668 Allow bhyve and bhyveload to attach to tty devices. r258614 The 22-bit Data Byte Count (DBC) field of a Physical Region Descriptor was being read as a 32-bit quantity by the bhyve AHCI driver. r258609 Fix discrepancy between the IOAPIC ID advertised by firmware tables and the actual value read by the guest. r257933 Route the legacy timer interrupt (IRQ0) to pin 2 of the IOAPIC. r257767 Fix an off-by-one error when iterating over the emulated PCI BARs. r257729 Add the VM name to the process name with setproctitle(). r257423 Make the virtual ioapic available unconditionally in a bhyve virtual machine. r257347 Update copyright to include the author of the LPC bridge emulation code. hand-merge r257018 Tidy usage messages for bhyve and bhyveload. r256657 Add an option to bhyveload(8) that allows setting a loader environment variable from the command line. Discussed with: neel
* MFC r257092grehan2013-10-301-31/+85
| | | | | | | | | | Fix bug in the ioapic emulation for level-triggered interrupts, where a pin assertion while a source was masked would result in the interrupt being lost, with the symptom being a console hang. The condition is now recorded, and the interrupt generated when the source is unmasked. Approved by: re (glebius)
* MFC r257293.neel2013-10-3013-596/+1103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PCI-to-ISA LPC bridge emulation. If the LPC bus is attached to a virtual machine then we implicitly create COM1 and COM2 ISA devices. Prior to this change the only way of attaching a COM port to the virtual machine was by presenting it as a PCI device that is mapped at the legacy I/O address 0x3F8 or 0x2F8. There were some issues with the original approach: - It did not work at all with UEFI because UEFI will reprogram the PCI device BARs and remap the COM1/COM2 ports at non-legacy addresses. - OpenBSD GENERIC kernel does not create a /dev/console because it expects the uart device at the legacy 0x3F8/0x2F8 address to be an ISA device. - It was functional with a FreeBSD guest but caused the console to appear on /dev/ttyu2 which was not intuitive. The uart emulation is now independent of the bus on which it resides. Thus it is possible to have uart devices on the PCI bus in addition to the legacy COM1/COM2 devices behind the LPC bus. The command line option to attach ISA COM1/COM2 ports to a virtual machine is "-s <bus>,lpc -l com1,stdio". The command line option to create a PCI-attached uart device is: "-s <bus>,uart[,stdio]" The command line option to create PCI-attached COM1/COM2 device is: "-S <bus>,uart[,stdio]". This style of creating COM ports is deprecated. Approved by: re (glebius)
* MFC r256926, r257005grehan2013-10-252-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | r256926 Fix AHCI ATAPI emulation when backed with /dev/cd0 - remove assumption that the backing file/device had 512-byte sectors - fix incorrect iovec size variable that would result in a buffer overrun when an o/s issued an i/o request with more s/g elements than the blockif api r257005 Export the block size capability to guests. - Use #defines for capability bits - Export the VTBLK_F_BLK_SIZE capability - Fix bug in calculating capacity: it is in 512-byte units, not the underlying sector size This allows virtio-blk to have backing devices with non 512-byte sector sizes e.g. /dev/cd0, and 4K-block harddrives. Approved by: re (glebius)
* MFC r256645.neel2013-10-223-50/+48
| | | | | | | | | | | | | | Add a new capability, VM_CAP_ENABLE_INVPCID, that can be enabled to expose 'invpcid' instruction to the guest. Currently bhyve will try to enable this capability unconditionally if it is available. Consolidate code in bhyve to set the capabilities so it is no longer duplicated in BSP and AP bringup. Add a sysctl 'vm.pmap.invpcid_works' to display whether the 'invpcid' instruction is available. Approved by: re (hrs)
* MFC r256709:grehan2013-10-187-147/+60
| | | | | | | | | | | Eliminate unconditional debug printfs. Linux writes to these nominally read-only registers, so avoid having bhyve write warning messages to stdout when the reg writes can be safely ignored. Change the WPRINTF to DPRINTF which is conditional. Approved by: re (delphij)
* MFC r256709:grehan2013-10-181-1/+1
| | | | | | | | | | | Eliminate unconditional debug printfs. Linux writes to these nominally read-only registers, so avoid having bhyve write warning messages to stdout when the reg writes can be safely ignored. Change the WPRINTF to DPRINTF which is conditional. Approved by: re (gjb)
* MFC r256389grehan2013-10-121-5/+47
| | | | | | | | | | | | Implement the virtio block 'get-ident' operation. This eliminates the annoying verbose boot error of the form g_handleattr: vtbd0 bio_length 24 len 28 -> EFAULT The ident returned by bhyve is a text string 'BHYVE-XXXX-XXXX', where the X's are the first bytes of the md5 hash of the backing filename. Approved by: re (gjb)
* Allow a 4-byte write to PCI config space to overlapgrehan2013-10-091-3/+12
| | | | | | | | | | | | the 2 read-only bytes at the start of a PCI capability. This is the sequence that OpenBSD uses when enabling MSI interrupts, and works fine on real h/w. In bhyve, convert the 4 byte write to a 2-byte write to the r/w area past the first 2 r/o bytes of a capability. Reviewed by: neel Approved by: re@ (blanket)
* Parse the memory size parameter using expand_number() to allow specifyingneel2013-10-092-3/+7
| | | | | | | | the memory size more intuitively (e.g. 512M, 4G etc). Submitted by: rodrigc Reviewed by: grehan Approved by: re (blanket)
* In usr.sbin/bhyve/pci_ahci.c, fix several gcc warnings of the formdim2013-10-081-11/+11
| | | | | | | | | | | "assignment makes pointer from integer without a cast", by changing the cmd_lst and rbis members of struct ahci_port from integers to pointers. Also surround a pow-of-2 test expression with parentheses to clarify it, and avoid another gcc warning. Approved by: re (glebius) Reviewed by: grehan, mav
* After r256062, the static function fbsdrun_get_next_cpu() indim2013-10-081-11/+0
| | | | | | | usr.sbin/bhyve/bhyverun.c is no longer used, so remove it to silence a gcc warning. Approved by: re (glebius)
* Change the behavior of bhyve such that the gdb listening port is opt-inneel2013-10-082-5/+3
| | | | | | | | | | | | | | | rather than opt-out. Prior to this change if the "-g" option was not specified then a listening socket for tunneling gdb packets would be opened at port 6466. If a second virtual machine is fired up, also without the "-g" option, then that would fail because there is already a listener on port 6466. After this change if a gdb tunnel port needs to be created it needs to be explicitly specified with a "-g <portnum>" command line option. Reviewed by: grehan@ Approved by: re@ (blanket)
* Merge projects/bhyve_npt_pmap into head.neel2013-10-053-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the amd64/pmap code aware of nested page table mappings used by bhyve guests. This allows bhyve to associate each guest with its own vmspace and deal with nested page faults in the context of that vmspace. This also enables features like accessed/dirty bit tracking, swapping to disk and transparent superpage promotions of guest memory. Guest vmspace: Each bhyve guest has a unique vmspace to represent the physical memory allocated to the guest. Each memory segment allocated by the guest is mapped into the guest's address space via the 'vmspace->vm_map' and is backed by an object of type OBJT_DEFAULT. pmap types: The amd64/pmap now understands two types of pmaps: PT_X86 and PT_EPT. The PT_X86 pmap type is used by the vmspace associated with the host kernel as well as user processes executing on the host. The PT_EPT pmap is used by the vmspace associated with a bhyve guest. Page Table Entries: The EPT page table entries as mostly similar in functionality to regular page table entries although there are some differences in terms of what bits are used to express that functionality. For e.g. the dirty bit is represented by bit 9 in the nested PTE as opposed to bit 6 in the regular x86 PTE. Therefore the bitmask representing the dirty bit is now computed at runtime based on the type of the pmap. Thus PG_M that was previously a macro now becomes a local variable that is initialized at runtime using 'pmap_modified_bit(pmap)'. An additional wrinkle associated with EPT mappings is that older Intel processors don't have hardware support for tracking accessed/dirty bits in the PTE. This means that the amd64/pmap code needs to emulate these bits to provide proper accounting to the VM subsystem. This is achieved by using the following mapping for EPT entries that need emulation of A/D bits: Bit Position Interpreted By PG_V 52 software (accessed bit emulation handler) PG_RW 53 software (dirty bit emulation handler) PG_A 0 hardware (aka EPT_PG_RD) PG_M 1 hardware (aka EPT_PG_WR) The idea to use the mapping listed above for A/D bit emulation came from Alan Cox (alc@). The final difference with respect to x86 PTEs is that some EPT implementations do not support superpage mappings. This is recorded in the 'pm_flags' field of the pmap. TLB invalidation: The amd64/pmap code has a number of ways to do invalidation of mappings that may be cached in the TLB: single page, multiple pages in a range or the entire TLB. All of these funnel into a single EPT invalidation routine called 'pmap_invalidate_ept()'. This routine bumps up the EPT generation number and sends an IPI to the host cpus that are executing the guest's vcpus. On a subsequent entry into the guest it will detect that the EPT has changed and invalidate the mappings from the TLB. Guest memory access: Since the guest memory is no longer wired we need to hold the host physical page that backs the guest physical page before we can access it. The helper functions 'vm_gpa_hold()/vm_gpa_release()' are available for this purpose. PCI passthru: Guest's with PCI passthru devices will wire the entire guest physical address space. The MMIO BAR associated with the passthru device is backed by a vm_object of type OBJT_SG. An IOMMU domain is created only for guest's that have one or more PCI passthru devices attached to them. Limitations: There isn't a way to map a guest physical page without execute permissions. This is because the amd64/pmap code interprets the guest physical mappings as user mappings since they are numerically below VM_MAXUSER_ADDRESS. Since PG_U shares the same bit position as EPT_PG_EXECUTE all guest mappings become automatically executable. Thanks to Alan Cox and Konstantin Belousov for their rigorous code reviews as well as their support and encouragement. Thanks for John Baldwin for reviewing the use of OBJT_SG as the backing object for pci passthru mmio regions. Special thanks to Peter Holm for testing the patch on short notice. Approved by: re Discussed with: grehan Reviewed by: alc, kib Tested by: pho
* Remove obsolete cmd-line options and code associated withgrehan2013-10-043-154/+28
| | | | | | | | | these. The mux-vcpus option may return at some point, given it's utility in finding bhyve (and FreeBSD) bugs. Approved by: re@ (blanket) Discussed with: neel@
* Hook up the AHCI and blockif code to the build.grehan2013-10-041-2/+2
| | | | Approved by: re@ (blanket)
* Import Zhixiang Yu's GSoC'13 AHCI emulation:grehan2013-10-042-0/+2109
| | | | | | | | | | | | | | | | | https://wiki.freebsd.org/SummerOfCode2013/bhyveAHCI This provides ICH8 SATA disk and ATAPI ports, selectable via the bhyve slot command-line parameter: SATA -s <slot>,ahci-hd,<image-file> ATAPI -s <slot>,ahci-cd,<image-file> Slight modifications by: grehan@ Approved by: re@ (blanket) Obtained from: FreeBSD GSoC'13
* Block-layer backend interface for bhyve block-io device emulations.grehan2013-10-042-0/+490
| | | | Approved by: re@ (blanket)
* Fix incorrect assertion on the minimum side. ZFS wouldgrehan2013-09-261-1/+1
| | | | | | | trigger this. Reported by: Chris Torek, Allan Jude Approved by: re@ (blanket)
* Implement support for the interrupt-on-terminal-count andgrehan2013-09-191-16/+90
| | | | | | | s/w-strobe timer modes. These are commonly used by non-FreeBSD o/s's. Approved by: re@ (blanket)
* Add simplistic periodic timer support to mevent using kqueue'sgrehan2013-09-193-8/+104
| | | | | | | | timer support. This should be enough for the emulation of h/w periodic timers (and no more) e.g. some of the 8254's more esoteric modes that happen to be used by non-FreeBSD o/s's. Approved by: re@ (blanket)
* Allow the alarm hours/mins/seconds registers to be read/written,grehan2013-09-191-0/+30
| | | | | | | | though without any action. This avoids a hypervisor exit when o/s's access these regs (Linux). Reviewed by: neel Approved by: re@ (blanket)
* Use correct offset for the high byte of high memory written togrehan2013-09-191-1/+1
| | | | | | | RTC NVRAM. Submitted by: Bela Lubkin bela dot lubkin at tidalscale dot com Approved by: re@ (blanket)
* Pass the number of supported vectors to pci_emul_add_msicap() andgrehan2013-09-171-1/+2
| | | | | | | not the actual PCI BAR number. Reviewed by: neel Approved by: re@ (blanket)
* Go way past 11 and bump bhyve's max vCPUs to 16.grehan2013-09-101-3/+5
| | | | | | | | | | | | | This should be sufficient for 10.0 and will do until forthcoming work to avoid limitations in this area is complete. Thanks to Bela Lubkin at tidalscale for the headsup on the apic/cpu id/io apic ASL parameters that are actually hex values and broke when written as decimal when 11 vCPUs were configured. Approved by: re@
* Fix spelling.grehan2013-09-061-1/+1
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* Allow level-triggered interrupt sources. While this isn'tgrehan2013-09-061-2/+2
| | | | | precisely emulated, it is good enough for the single consumer i.e. irq4, the serial port on Linux.
* Allow single byte reads of the emulated MSI-X tables. This is not requiredneel2013-08-271-3/+9
| | | | | by the PCI specification but needed to dump MMIO space from "ddb" in the guest.
* Fix off-by-1 error in assert.grehan2013-08-271-1/+1
| | | | Submitted by: Tycho Nightingale (tycho.nightingale@pluribusnetworks.com)
* Fix ordering of legacy IRQ reservations.grehan2013-08-161-10/+10
| | | | Submitted by: Jeremiah Lott jlott at averesystems dot com
* Sanity-check the vm exitcode, and exit the process if it's out-of-boundsgrehan2013-07-181-2/+11
| | | | | | or there is no registered handler. Submitted by: Bela Lubkin bela dot lubkin at tidalscale dot com
* Major rework of the virtio code. Split out common parts, and modifygrehan2013-07-175-961/+1408
| | | | | | | the net/block devices accordingly. Submitted by: Chris Torek torek at torek dot net Reviewed by: grehan
* Implement RTC CMOS nvram. Init some fields that are usedgrehan2013-07-113-22/+105
| | | | | | | by FreeBSD and UEFI. Tested with nvram(4). Reviewed by: neel
* Support an optional "mac=" parameter to virtio-net config, to allowgrehan2013-07-044-29/+85
| | | | | | | | | | | | users to set the MAC address for a device. Clean up some obsolete code in pci_virtio_net.c Allow an error return from a PCI device emulation's init routine to be propagated all the way back to the top-level and result in the process exiting. Submitted by: Dinakar Medavaram dinnu sun at gmail (original version)
* Fix up option parsing to allow a colon in the config section.grehan2013-07-011-13/+8
| | | | | | | Clean up some other unnecessary code. Submitted by: Dinakar Medavaram dinnu sun at gmail Reviewed by: neel
* Allow 8259 registers to be read. This is a transient conditiongrehan2013-06-281-9/+8
| | | | | | | during Linux boot. Submitted by: tycho nightingale at pluribusnetworks com Reviewed by: neel
* Allow the PCI config address register to be read. The Linuxgrehan2013-06-281-11/+21
| | | | | | | kernel does this. Also remove an unused header file. Submitted by: tycho nightingale at pluribusnetworks com Reviewed by: neel
* Implement the NOTIFY_ON_EMPTY capability in the virtio-net device.neel2013-05-032-34/+37
| | | | | | | | If this capability is negotiated by the guest then the device will generate an interrupt when it runs out of available tx/rx descriptors. Reviewed by: grehan Obtained from: NetApp
* Reset some more softc state when the guest resets the virtio network device.neel2013-04-301-0/+7
| | | | Obtained from: NetApp
* Use a separate mutex for the receive path instead of overloading the softcneel2013-04-301-20/+58
| | | | | | mutex for this purpose. Reviewed by: grehan
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