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* dmar_ctx_dtr() does not exist since r284869. Remove the static functionbz2015-09-221-1/+0
| | | | declaration to avoid a cmpile time warning.
* Add domain support to PCI bus allocationzbb2015-09-163-3/+3
| | | | | | | | | | | | When the system has more than a single PCI domain, the bus numbers are not unique, thus they cannot be used for "pci" device numbering. Change bus numbers to -1 (i.e. to-be-determined automatically) wherever the code did not care about domains. Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3406
* Add ASUS Sandybridge laptops to the similar x2apic disable logicadrian2015-09-161-1/+13
| | | | | | | | | | | that was recently added for Lenovo laptops. This is a prime candidate for conversion into a table and also checking other fields like "product". Tested: * ASUS UX31E
* Add stack_save_td_running(), a function to trace the kernel stack of amarkj2015-09-115-13/+82
| | | | | | | | | | | | | | | | | running thread. It is currently implemented only on amd64 and i386; on these architectures, it is implemented by raising an NMI on the CPU on which the target thread is currently running. Unlike stack_save_td(), it may fail, for example if the thread is running in user mode. This change also modifies the kern.proc.kstack sysctl to use this function, so that stacks of running threads are shown in the output of "procstat -kk". This is handy for debugging threads that are stuck in a busy loop. Reviewed by: bdrewery, jhb, kib Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D3256
* Remove the arg0 field from struct amd64_frame. Its existence was a bug,markj2015-09-111-1/+0
| | | | | | | | | | | | since on amd64 the first argument to a function is generally not on the stack. Revert an old DTrace bug fix to some code that assumed that sizeof(struct amd64_frame) == 16. Reviewed by: jhb, kib Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D3255
* Merge stack(9) implementations for i386 and amd64 under x86/.markj2015-09-112-0/+162
| | | | | | Reviewed by: jhb, kib Sponsored by: EMC / Isilon Storage Division Differential Revision: https://reviews.freebsd.org/D3255
* Add missing ofw_machdep.h. Make x86 ofw_machdep.h work pc98 too.imp2015-08-281-1/+1
| | | | | This allows the owc module to compile on pc98 and seems preferable to adding another special case in the build system.
* preload_search_info: make sure mod is setroyger2015-08-212-6/+3
| | | | | | | | | | | Add a check to preload_search_info to make sure mod is set. Most of the callers of preload_search_info don't check that the mod parameter is set, which can cause page faults. While at it, remove some now unnecessary checks before calling preload_search_info. Sponsored by: Citrix Systems R&D Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D3440
* xen: allow disabling PV disks and nicsroyger2015-08-211-4/+24
| | | | | | | | | | | | | | | Introduce two new loader tunnables that can be used to disable PV disks and PV nics at boot time. They default to 0 and should be set to 1 (or any number different than 0) in order to disable the PV devices: hw.xen.disable_pv_disks=1 hw.xen.disable_pv_nics=1 In /boot/loader.conf will disable both PV disks and nics. Sponsored by: Citrix Systems R&D Tested by: Karl Pielorz <kpielorz_lst@tdx.co.uk> MFC after: 1 week
* Automatically disable x2APIC mode on SandyBridge Lenovo machines. Ikib2015-08-211-6/+33
| | | | | | | | | | | | believe that the bug only affects mobile CPUs, at least I did not see other reports, but it is impossible to detect it in madt_setup_local(). While there, reduce duplication in the information strings printed when x2APIC is auto-disabled, and do not print the line when user manually override the setting. Tested and reviewed by: royger (previous version) Sponsored by: The FreeBSD Foundation
* Use pmap_quick_enter_page() to handle bouncing of unmapped buffers in the ↵jah2015-08-141-19/+36
| | | | | | | | | | x86 busdma_bounce implementation. Also treat user buffers as unmapped. This allows two things: 1. Sync'ing bounced maps in non-sleepable contexts. The physcopy* calls previously used could sleep on sf_buf operations in some cases. 2. Sync'ing user buffers outside the context of the owning process Approved by: kib (mentor)
* Reformat x86 bounce buffer synchronization code to reduce indentation. No ↵jah2015-08-141-36/+32
| | | | | | functional change. Approved by: kib (mentor)
* Comment only change, fix grammar and somewhat clarify the action.kib2015-08-141-2/+3
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 3 days
* Better support memory mapped console devices, such as VGA and EFImarcel2015-08-122-21/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | frame buffers and memory mapped UARTs. 1. Delay calling cninit() until after pmap_bootstrap(). This makes sure we have PMAP initialized enough to add translations. Keep kdb_init() after cninit() so that we have console when we need to break into the debugger on boot. 2. Unfortunately, the ATPIC code had be moved as well so as to avoid a spurious trap #30. The reason for which is not known at this time. 3. In pmap_mapdev_attr(), when we need to map a device prior to the VM system being initialized, use virtual_avail as the KVA to map the device at. In particular, avoid using the direct map on amd64 because we can't demote by virtue of not being able to allocate yet. Keep track of the translation. Re-use the translation after the VM has been initialized to not waste KVA and to satisfy the assumption in uart(4) that the handle returned for the low-level console is the same as later returned when the device is probed and attached. 4. In pmap_unmapdev() remove the mapping from the table when called pre-init. Otherwise keep the mapping. During bus probe and attach device resources are mapped and unmapped multiple times, which would have us destroy the mapping used by the low-level console. 5. In pmap_init(), set pmap_initialized to signal that we're not pre-init anymore. On amd64, bring the direct map in sync with the translations created at that time. 6. Implement bus_space_map() and bus_space_unmap() for real: when the tag corresponds to memory space, call the corresponding pmap_mapdev() and pmap_unmapdev() functions to construct and actual handle. 7. In efifb.c and vt_vga.c, remove the crutches and hacks and simply call pmap_mapdev_attr() or bus_space_map() as desired. Notes: 1. uart(4) already used bus_space_map() during low-level console setup but since serial ports have traditionally been I/O port based, the lack of a proper implementation for said function was not a problem. It has always supported memory mapped UARTs for low-level consoles by setting hw.uart.console accordingly. 2. The use of the direct map on amd64 without setting caching attributes has been a bigger problem than previously thought. This change has the fortunate (and unexpected) side-effect of fixing various EFI frame buffer problems (though not all). PR: 191564, 194952 Special thanks to: 1. XipLink, Inc -- generously donated an Intel Bay Trail E3800 based eval board (ADLE3800PC). 2. The FreeBSD Foundation, in particular emaste@ -- for UEFI support in general and testing. 3. Everyone who tested the proposed for PR 191564. 4. jhb@ and kib@ for being a soundboard and applying a clue bat if so needed.
* In x2APIC mode, IPI generation is atomic because it is performed bykib2015-08-121-3/+5
| | | | | | | | | | | | | | | single ICR MSR write. This is in contrast with the xAPIC mode, where we must read current ICR value, do bit fiddling and perform two 32-bit register writes. As a consequence, there is no need to disable interrupts around ICR value calculation and write. Note that typical users of ipi_raw() and ipi_vectored() take spinlock, which already disables interrupts. For them, the change removes unneeded CLI and POPFL/Q instructions. Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Make kstack_pages a tunable on arm, x86, and powepc. On i386, thekib2015-08-101-2/+2
| | | | | | | | | | | | | | | | | | | initial thread stack is not adjusted by the tunable, the stack is allocated too early to get access to the kernel environment. See TD0_KSTACK_PAGES for the thread0 stack sizing on i386. The tunable was tested on x86 only. From the visual inspection, it seems that it might work on arm and powerpc. The arm USPACE_SVC_STACK_TOP and powerpc USPACE macros seems to be already incorrect for the threads with non-default kstack size. I only changed the macros to use variable instead of constant, since I cannot test. On arm64, mips and sparc64, some static data structures are sized by KSTACK_PAGES, so the tunable is disabled. Sponsored by: The FreeBSD Foundation MFC after: 2 week
* Formally pair store_rel(&smp_started) with load_acq(&smp_started).kib2015-08-061-1/+1
| | | | | | | | | | | The expected semantic is to have misc. data, e.g. CPU bitmaps, visible in the BSP after smp_started is written by the last started AP, which formally requires acquire barrier on the load. The change is mostly nop due to the ordered behaviour of the x86 CPUs. Reviewed by: alc Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Remove some more vestiges of the Xen PV domu support. Specifically,jhb2015-08-061-1/+0
| | | | | | | | | use vtophys() directly instead of vtomach() and retire the no-longer-used headers <machine/xenfunc.h> and <machine/xenvar.h>. Reported by: bde (stale bits in <machine/xenfunc.h>) Reviewed by: royger (earlier version) Differential Revision: https://reviews.freebsd.org/D3266
* Fix more style issues.jkim2015-08-051-3/+3
| | | | Submitted by: bde
* Rationalize BSD license on sys/*/include/float.hemaste2015-08-051-1/+1
| | | | | | | Remove the advertising clause from the Regents of the University of California's license, per the letter dated July 22, 1999. Update clause numbering.
* Fix style(9) bugs.jkim2015-08-041-6/+5
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* Always define __va_list for amd64 and restore pre-r232261 behavior for i386.jkim2015-08-041-2/+11
| | | | | | | Note it allows exotic compilers, e.g., TCC, to build with our stdio.h, etc. PR: 201749 MFC after: 1 week
* Clear the IA32_MISC_ENABLE MSR bit, which limits the max CPUIDkib2015-08-031-16/+30
| | | | | | | | | | | | | | reported, on APs. We already did this on BSP. Otherwise, the userspace software which depends on the features reported by the high CPUID levels is misbehaving. In particular, AVX detection is non-functional, depending on which CPU thread happens to execute when doing CPUID. Another victim is the libthr signal handlers interposer, which needs to save full FPU extended state. Reported and tested by: Andre Meiser <ortadur@web.de> Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Add bit names for the IA32_MISC_ENABLE msr.kib2015-07-281-0/+11
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Typo in comment.kib2015-07-201-1/+1
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* Fix warnings about unused functions for UP build.kib2015-07-161-3/+7
| | | | Sponsored by: The FreeBSD Foundation
* Fix KSTACK_PAGES issue when the default value was changed in KERNCONFzbb2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | If KSTACK_PAGES was changed to anything alse than the default, the value from param.h was taken instead in some places and the value from KENRCONF in some others. This resulted in inconsistency which caused corruption in SMP envorinment. Ensure all places where KSTACK_PAGES are used the opt_kstack_pages.h is included. The file opt_kstack_pages.h could not be included in param.h because was breaking the toolchain compilation. Reviewed by: kib Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3094
* Set the initial system time to a sane (as in: not end of 21st century) value ↵brueffer2015-06-291-1/+1
| | | | | | | | | | | | | | when booting on a PC with CMOS clock set to a year before 2000. This uses 1980 (instead of 1970 as in the initial patch) as pivot year as suggested by imp in the PR followup. PR: 195703 Submitted by: cs@soi.spb.ru Reviewed by: imp MFC after: 1 weeks
* Add x86 PT_GETFSBASE, PT_GETGSBASE machine-depended ptrace requests tokib2015-06-291-0/+4
| | | | | | | | | | | | | obtain the thread %fs and %gs bases. Add x86 PT_SETFSBASE and PT_SETGSBASE requests to set the bases from debuggers. The set requests, similarly to the sysarch({I386,AMD64}_SET_FSBASE), override the corresponding segment registers. The main purpose of the operations is to retrieve and modify the tcb address for debuggee. Sponsored by: The FreeBSD Foundation MFC after: 2 weeks
* Split the DMAR unit domains and contexts. Domains carry address spacekib2015-06-268-623/+839
| | | | | | | | | | | | | | | | | | | | and related data structures. Contexts attach requests initiators to domains. There is still 1:1 correspondence between contexts and domains on the running system, since only busdma currently allocates them, using dmar_get_ctx_for_dev(). Large part of the change is formal rename of the ctx to domain, but patch also reworks the context allocation and free to allow for independent domain creation. The helper dmar_move_ctx_to_domain() is introduced for future use, to reassign request initiator from one domain to another. The hard issue which is not yet resolved with the context move is proper handling (or reserving) RMRR entries in the destination domain as required by ACPI DMAR table for moved context. Tested by: pho Sponsored by: The FreeBSD Foundation
* Merge ACPICA 20150619.jkim2015-06-181-2/+2
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* Handle X2APIC entries in the MADT for APICs with an ID < 255. At least onejhb2015-06-091-32/+65
| | | | | | | | | | | | | | BIOS has been seen to include such entries even though the relevant specs require that X2APIC entries only be used for CPUs with an APIC ID >= 255. This was tested on a system with "plain" local APIC entries in the MADT to ensure no regressions, but it has not yet been tested on a system with X2APIC entries in the MADT. Currently such systems do not boot at all, and with this change they might now boot correctly. Differential Revision: https://reviews.freebsd.org/D2521 Reviewed by: kib MFC after: 2 weeks
* Update print_INTEL_TLB() by the tag values from the Intel SDMkib2015-06-061-3/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | rev. 55. The modern CPUs cache and TLB descriptions looked quite questionable without the update, e.g. Haswell i7 4770S reported: Data TLB: 4 KB pages, 4-way set associative, 64 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line After the update, the report is: Data TLB: 1 GByte pages, 4-way set associative, 4 entries Data TLB: 4 KB pages, 4-way set associative, 64 entries Instruction TLB: 2M/4M pages, fully associative, 8 entries Instruction TLB: 4KByte pages, 8-way set associative, 64 entries 64-Byte prefetching Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries L2 cache: 256 kbytes, 8-way associative, 64 bytes/line Some tags were apparently removed from the table 3-21, Vol. 2A. Keep them around, but add a comment stating the removal. Update the format line for cpu_stdext_feature according to the bits from the SDM rev.55. It appears that Haswells do not store %cs and %ds values in the FPU save area. Store content of the %ecx register from the CPUID leaf 0x7 subleaf 0 as cpu_stdext_feature2 and print defined bits from it, again acording to SDM rev. 55. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Remove several write-only variables, all reported by the gcc 4.9kib2015-05-292-9/+3
| | | | | | | | | | | | | | | | buildkernel run. Some of them were write-only under some kernel options, e.g. variables keeping values only used by CTR() macros. It costs nothing to the code readability and correctness to eliminate the warnings in those cases too by removing the local cached values used only for single-access. Review: https://reviews.freebsd.org/D2665 Reviewed by: rodrigc Looked at by: bjk Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Explicitely enable queued invalidation completion interrupt when thekib2015-05-291-0/+2
| | | | | | | | queue is started, not relying on the interrupt remaping method to happen. Also disable interrupts when shooting down the queue. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* xen: make sure xenpv bus is the last to attachroyger2015-05-251-1/+6
| | | | | | | This is needed so other buses have a chance of attaching a real ISA bus, if none is found xenpv will attach it. Sponsored by: Citrix Systems R&D
* CALLOUT_MPSAFE has lost its meaning since r141428, i.e., for more than tenjkim2015-05-221-1/+1
| | | | | | | | | | years for head. However, it is continuously misused as the mpsafe argument for callout_init(9). Deprecate the flag and clean up callout_init() calls to make them more consistent. Differential Revision: https://reviews.freebsd.org/D2613 Reviewed by: jhb MFC after: 2 weeks
* When sleeping in Sx state using MWAIT instruction, accept fast wakeupkib2015-05-191-6/+17
| | | | | | requests from writes to the monitored line. Submitted by: avg
* Update the comments to match what the code ended up becoming.adrian2015-05-151-1/+1
| | | | | | -1 is now "no locality information available". Sponsored by: Norse Corp, Inc.
* Rewrite amd64 PCID implementation to follow an algorithm described inkib2015-05-092-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the Vahalia' "Unix Internals" section 15.12 "Other TLB Consistency Algorithms". The same algorithm is already utilized by the MIPS pmap to handle ASIDs. The PCID for the address space is now allocated per-cpu during context switch to the thread using pmap, when no PCID on the cpu was ever allocated, or the current PCID is invalidated. If the PCID is reused, bit 63 of %cr3 can be set to avoid TLB flush. Each cpu has PCID' algorithm generation count, which is saved in the pmap pcpu block when pcpu PCID is allocated. On invalidation, the pmap generation count is zeroed, which signals the context switch code that already allocated PCID is no longer valid. The implication is the TLB shootdown for the given cpu/address space, due to the allocation of new PCID. The pm_save mask is no longer has to be tracked, which (significantly) reduces the targets of the TLB shootdown IPIs. Previously, pm_save was reset only on pmap_invalidate_all(), which made it accumulate the cpuids of all processors on which the thread was scheduled between full TLB shootdowns. Besides reducing the amount of TLB shootdowns and removing atomics to update pm_saves in the context switch code, the algorithm is much simpler than the maintanence of pm_save and selection of the right address space in the shootdown IPI handler. Reviewed by: alc Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 3 weeks
* If x86 CPU implementation of the MWAIT instruction reasonablykib2015-05-092-2/+34
| | | | | | | | | | | | | | | | | | | | | | | interacts with interrupts, query ACPI and use MWAIT for entrance into Cx sleep states. Support C1 "I/O then halt" mode. See Intel' document 302223-007 "Intelб╝ Processor Vendor-Specific ACPI Interface Specification" for description. Move the acpi_cpu_c1() function into x86/cpu_machdep.c and use it instead of inlining "sti; hlt" sequence in several places. In the acpi(4) man page, besides documenting the dev.cpu.N.cx_methods sysctl, correct the names for dev.cpu.N.{cx_usage,cx_lowest,cx_supported} sysctls. Both jkim and avg have some other patches implementing the mwait functionality; this work is unrelated. Linux does not rely on the ACPI to provide correct tables describing Cx modes. Instead, the driver has pre-defined knowledge of the CPU models, it was supplied by Intel. Tested by: pho (previous versions) Sponsored by: The FreeBSD Foundation
* xen: introduce a newbus function to allocate unused memoryroyger2015-05-081-0/+84
| | | | | | | | | | | | | | | | In order to map memory from other domains when running on Xen FreeBSD uses unused physical memory regions. Until now this memory has been allocated using bus_alloc_resource, but this is not completely safe as we can end up using unreclaimed MMIO or ACPI regions. Fix this by introducing a new newbus method that can be used by Xen drivers to request for unused memory regions. On amd64 we make sure this memory comes from regions above 4GB in order to prevent clashes with MMIO/ACPI regions. On i386 there's nothing we can do, so just fall back to the previous mechanism. Sponsored by: Citrix Systems R&D Tested by: Gustau Pérez <gperez@entel.upc.edu>
* Add initial memory locality cost awareness to the VM, and includeadrian2015-05-081-6/+120
| | | | | | | | | | | | | | | | a basic ACPI SLIT table parser. For now this just exports the map via sysctl; it'll eventually be useful to userland when there's more useful NUMA support in -HEAD. * Add an optional mem_locality map; * add a mapping function taking from/to domain and returning the relative cost, or -1 if it's not available; * Add a very basic SLIT parser to x86 ACPI. Differential Revision: https://reviews.freebsd.org/D2460 Reviewed by: rpaulo, stas, jhb Sponsored by: Norse Corp, Inc (hardware, coding); Dell (hardware)
* Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE.neel2015-05-061-1/+4
| | | | | | AMDID_FFXSR is at bit 25 so correct its value to 0x02000000. MFC after: 1 week
* Remove support for Xen PV domU kernels. Support for HVM domU kernelsjhb2015-04-308-88/+5
| | | | | | | | | | | | | | | | | | | | | remains. Xen is planning to phase out support for PV upstream since it is harder to maintain and has more overhead. Modern x86 CPUs include virtualization extensions that support HVM guests instead of PV guests. In addition, the PV code was i386 only and not as well maintained recently as the HVM code. - Remove the i386-only NATIVE option that was used to disable certain components for PV kernels. These components are now standard as they are on amd64. - Remove !XENHVM bits from PV drivers. - Remove various shims required for XEN (e.g. PT_UPDATES_FLUSH, LOAD_CR3, etc.) - Remove duplicate copy of <xen/features.h>. - Remove unused, i386-only xenstored.h. Differential Revision: https://reviews.freebsd.org/D2362 Reviewed by: royger Tested by: royger (i386/amd64 HVM domU and amd64 PVH dom0) Relnotes: yes
* Microsoft vmbus, storage and other related driver enhancements for HyperV.whu2015-04-291-0/+1
| | | | | | | | | | | | | | | | | | | | - Vmbus multi channel support. - Vector interrupt support. - Signal optimization. - Storvsc driver performance improvement. - Scatter and gather support for storvsc driver. - Minor bug fix for KVP driver. Thanks royger, jhb and delphij from FreeBSD community for the reviews and comments. Also thanks Hovy Xu from NetApp for the contributions to the storvsc driver. PR: 195238 Submitted by: whu Reviewed by: royger, jhb, delphij Approved by: royger MFC after: 2 weeks Relnotes: yes Sponsored by: Microsoft OSTC
* The add_bounce_page() function can be called when loading physicalhselasky2015-04-281-2/+2
| | | | | | | | | | | | pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET flag is set, use the physical address to compute the page offset instead. The physical address should always be valid when adding bounce pages and should contain the same page offset like the virtual address. Submitted by: Svatopluk Kraus <onwahe@gmail.com> MFC after: 1 week Reviewed by: jhb@
* Move common code from sys/i386/i386/mp_machdep.c andkib2015-04-241-0/+1120
| | | | | | | | | sys/amd64/amd64/mp_machdep.c, to the new common x86 source sys/x86/x86/mp_x86.c. Proposed and reviewed by: jhb Review: https://reviews.freebsd.org/D2347 Sponsored by: The FreeBSD Foundation
* Reassign copyright statements on several files from Advancedjhb2015-04-234-4/+4
| | | | | | | Computing Technologies LLC to Hudson River Trading LLC. Approved by: Hudson River Trading LLC (who owns ACT LLC) MFC after: 1 week
* Move some common code from sys/amd64/amd64/machdep.c andkib2015-04-221-0/+533
| | | | | | | | sys/i386/i386/machdep.c to new file sys/x86/x86/cpu_machdep.c. Most of the code is related to the idle handling. Discussed with: pluknet Sponsored by: The FreeBSD Foundation
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