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* When mapping an allocated entry, use the entry size, instead of thekib2015-03-241-1/+1
| | | | | | | | | requested size. If tag restrictions caused split entry, its size is less then requsted. Hardware provided by: Michael Fuckner <michael@fuckner.net> Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Assert that the mapping loop makes progress.kib2015-03-241-0/+1
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Use VT-d interrupt remapping block (IR) to perform FSB messageskib2015-03-1916-40/+921
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | translation. In particular, despite IO-APICs only take 8bit apic id, IR translation structures accept 32bit APIC Id, which allows x2APIC mode to function properly. Extend msi_cpu of struct msi_intrsrc and io_cpu of ioapic_intsrc to full int from one byte. KPI of IR is isolated into the x86/iommu/iommu_intrmap.h, to avoid bringing all dmar headers into interrupt code. The non-PCI(e) devices which generate message interrupts on FSB require special handling. The HPET FSB interrupts are remapped, while DMAR interrupts are not. For each msi and ioapic interrupt source, the iommu cookie is added, which is in fact index of the IRE (interrupt remap entry) in the IR table. Cookie is made at the source allocation time, and then used at the map time to fill both IRE and device registers. The MSI address/data registers and IO-APIC redirection registers are programmed with the special values which are recognized by IR and used to restore the IRE index, to find proper delivery mode and target. Map all MSI interrupts in the block when msi_map() is called. Since an interrupt source setup and dismantle code are done in the non-sleepable context, flushing interrupt entries cache in the IR hardware, which is done async and ideally waits for the interrupt, requires busy-wait for queue to drain. The dmar_qi_wait_for_seq() is modified to take a boolean argument requesting busy-wait for the written sequence number instead of waiting for interrupt. Some interrupts are configured before IR is initialized, e.g. ACPI SCI. Add intr_reprogram() function to reprogram all already configured interrupts, and call it immediately before an IR unit is enabled. There is still a small window after the IO-APIC redirection entry is reprogrammed with cookie but before the unit is enabled, but to fix this properly, IR must be started much earlier. Add workarounds for 5500 and X58 northbridges, some revisions of which have severe flaws in handling IR. Use the same identification methods as employed by Linux. Review: https://reviews.freebsd.org/D1892 Reviewed by: neel Discussed with: jhb Tested by: glebius, pho (previous versions) Sponsored by: The FreeBSD Foundation MFC after: 3 weeks
* Provide definitions for all descriptors types in the DMAR invalidationkib2015-03-191-6/+21
| | | | | | | | | queue. They are for first-level translations and device TLB. Review: https://reviews.freebsd.org/D1892 Reviewed by: neel Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Fix syntax error.kib2015-03-191-1/+1
| | | | | | | Review: https://reviews.freebsd.org/D1892 Found by: neel Sponsored by: The FreeBSD Foundation MFC after: 3 days
* When initial placement of the new entry crosses the boundary,kib2015-03-171-2/+4
| | | | | | | | | | | | | | allocator tries to move the entry up, after the boundary. The new location may still fail to satisfy boundary requirement, for instance, if the boundary is set to page size, and allocation is of multiple pages. Recheck that boundary is not crossed after the move. If it is crossed, give up on allocating the whole entry and split it. Reported by: Michael Fuckner <michael@fuckner.net>, running nvme(4) Sponsored by: The FreeBSD Foundation MFC after: 1 week
* When inserting new entry into the address map, ensure that not onlykib2015-03-171-1/+2
| | | | | | | | next entry does not intersect with the tail of the new entry, but also that previous entry is also before new entry start. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Add x86 specific APIs 'lapic_ipi_alloc()' and 'lapic_ipi_free()' to allow IPIneel2015-03-143-7/+104
| | | | | | | | | | | | vectors to be dynamically allocated. This allows kernel modules like vmm.ko to allocate unique IPI slots when loaded (as opposed to hard allocating one or more vectors). Also, reorganize the fixed IPI vectors to create a contiguous space for dynamic IPI allocation. Reviewed by: kib, jhb Differential Revision: https://reviews.freebsd.org/D2042
* Free up the IPI slot used by IPI_STOP_HARD.neel2015-03-011-1/+6
| | | | | | | | Change the numeric value of IPI_STOP_HARD so it doesn't occupy a valid IPI slot. This can be done because IPI_STOP_HARD is actually delivered via NMI. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D1983
* Since all generations of Intel CPUs have errata which causes hang onkib2015-02-271-5/+10
| | | | | | | | | | | | the cache line flush in the LAPIC page, keep direct map page covering LAPIC mapped uncached. To have the (incomplete) check for the LAPIC range in pmap_invalidate_cache_range() working, lapic_paddr must be initialized in x2APIC mode too. Sponsored by: The FreeBSD Foundation MFC after: 2 months
* xen/intr: fix fallout from r278854royger2015-02-261-14/+23
| | | | | | | | | | | | | | | r278854 introduced a race in the event channel handling code. We must make sure that the pending bit is cleared before executing the filter, or else we might miss other events that would be injected after the filter has ran but before the pending bit is cleared. While there also mask event channels while FreeBSD executes the ithread bound to that event channel. This refrains Xen from injecting more interrupts while the ithread has not finished it's work. Sponsored by: Citrix Systems R&D Reported by: sbruno, robak Tested by: robak
* Implements EOI suppression mode, where LAPIC on EOI command forkib2015-02-263-6/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | level-triggered interrupt does not broadcast the EOI message to all APICs in the system. Instead, interrupt handler must follow LAPIC EOI with IOAPIC EOI. For modern IOAPICs, the later is done by writing to EOIR register. Otherwise, Intel provided Linux with a trick of temporary switching the pin config to edge and then back to level. Detect presence of EOIR register by reading IO-APIC version. The summary table in the comments was taken from the Linux kernel. For Intel, newer IO-APICs are only briefly documented as part of the ICH/PCH datasheet. According to the BKDG and chipset documentation, AMD LAPICs do not provide EOI suppression, althought IO-APICs do declare version 0x21 and implement EOIR. The trick to temporary switch pin to edge mode to clear IRR was tested on modern chipset, by pretending that EOIR is not present, i.e. by forcing io_haseoi to zero. Tunable hw.lapic_eoi_suppression disables the optimization. Reviewed by: neel Tested by: pho Review: https://reviews.freebsd.org/D1943 Sponsored by: The FreeBSD Foundation MFC after: 2 months
* For now, disable x2APIC mode when Xen is detected, even if CPUkib2015-02-251-0/+2
| | | | | | | | | declares support for it. Newer versions of Xen works fine with x2APIC code, but e.g. Xen 4.2 delivers GPF on the LAPIC MSR write, despite x2APIC mode being known to hypervisor. Discussed with: royger Sponsored by: The FreeBSD Foundation
* Revert r276949 and redo the fix for PCIe/PCI bridges, which do notkib2015-02-211-6/+26
| | | | | | | | | | | | | follow specification and do not provide PCIe capability. Verify if the port above such bridge is downstream PCIe (or root port) and treat the bridge as PCIe/PCI then. This allows to avoid maintaining the table of device ids for bridges without capability, while still calculate correct request originator for devices behind the bridge. Submitted by: Jason Harmening <jason.harmening@gmail.com> MFC after: 1 week
* Fix build on i386 without "device apic"tijl2015-02-201-0/+9
| | | | Reviewed by: kib
* Fix UP build.kib2015-02-181-1/+2
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 2 months
* Initialize x2APIC mode on the resume path before accessing LAPIC.kib2015-02-162-1/+1
| | | | | | | | | | Remove unneeded disable of LAPIC in the native_lapic_xapic_mode(). We attempt to send wakeup IPI on the resume path right after BSP wakeup, so disabling is wrong. Reported and tested by: glebius, "Ranjan1018 ." <214748mv@gmail.com> Sponsored by: The FreeBSD Foundation MFC after: 2 months
* xen/intr: improve handling of legacy IRQsroyger2015-02-161-3/+19
| | | | | | | | | | | Devices that use ISA IRQs expect them to be already configured, and don't call bus_config_intr, which prevents those IRQs from working on Xen. In order to solve it pre-register all the legacy IRQs with the default values (edge triggered, low polarity) if no override is found. While there add a panic if the registration of an interrupt override fails. Sponsored by: Citrix Systems R&D
* xen/intr: improve PIRQ handlingroyger2015-02-161-20/+29
| | | | | | | | | | | | | | | Improve and cleanup the Xen PIRQ event channel code: - Remove the xi_shared field as it is unused. - Clean the "pending" bit in the EOI handler, this is more similar to how native interrupts are handled. - Don't mask edge triggered PIRQs, edge trigger interrupts cannot be masked. - Panic if PHYSDEVOP_eoi fails. - Remove the usage of the PHYSDEVOP_alloc_irq_vector hypercall because it's just a no-op in the Xen versions that are supported by FreeBSD Dom0. Sponsored by: Citrix Systems R&D
* Detect whether x2APIC on VMWare is usable without interruptkib2015-02-142-0/+18
| | | | | | | | | | | redirection support. Older versions of the hypervisor mis-interpret the cpuid format in ioapic registers when x2APIC is turned on, but IR is not used by the guest OS. Based on: Linux commit 4cca6ea04d31c22a7d0436949c072b27bde41f86 Tested by: markj Sponsored by: The FreeBSD Foundation MFC after: 2 months
* Registers definitions for the new capabilities from the version 2.4 ofkib2015-02-112-4/+67
| | | | | | | | | | | VT-d specification. Also add definitions for the interrupt remapping table and IEC. Print new capabilities on boot. although there is no hardware which support it. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* vm_page_lookup() accepts read-locked object.kib2015-02-111-4/+2
| | | | | Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Add x2APIC support. Enable it by default if CPU is capable. Thekib2015-02-097-115/+365
| | | | | | | | | | | | | | | | | | | | | | | | | hw.x2apic_enable tunable allows disabling it from the loader prompt. To closely repeat effects of the uncached memory ops when accessing registers in the xAPIC mode, the x2APIC writes to MSRs are preceeded by mfence, except for the EOI notifications. This is probably too strict, only ICR writes to send IPI require serialization to ensure that other CPUs see the previous actions when IPI is delivered. This may be changed later. In vmm justreturn IPI handler, call doreti_iret instead of doing iretd inline, to handle corner conditions. Note that the patch only switches LAPICs into x2APIC mode. It does not enables FreeBSD to support > 255 CPUs, which requires parsing x2APIC MADT entries and doing interrupts remapping, but is the required step on the way. Reviewed by: neel Tested by: pho (real hardware), neel (on bhyve) Discussed with: jhb, grehan Sponsored by: The FreeBSD Foundation MFC after: 2 months
* Revert the IPI startup sequence to match what is described in thejhb2015-02-061-14/+14
| | | | | | | | | | | | | | Intel Multiprocessor Specification v1.4. The Intel SDM claims that the INIT IPIs here are invalid, but other systems follow the MP spec instead. While here, fix the IPI wait routine to accept a timeout in microseconds instead of a raw spin count, and don't spin forever during AP startup. Instead, panic if a STARTUP IPI is not delivered after 20 us. PR: 196542 Differential Revision: https://reviews.freebsd.org/D1719 MFC after: 2 weeks
* Add interface to derive a TSC frequency from the pvclockbryanv2015-02-042-0/+16
| | | | | | | This can later use this to determine the TSC frequency like is done with VMware, instead of using a DELAY loop that is not always accurate in an VM. MFC after: 1 month
* Generalized parts of the XEN timer code into a generic pvclockbryanv2015-02-042-0/+246
| | | | | | | | | KVM clock shares the same data structures between the guest and the host as Xen so it makes sense to just have a single copy of this code. Differential Revision: https://reviews.freebsd.org/D1429 Reviewed by: royger (eariler version) MFC after: 1 month
* Opt for performance over power-saving on Intel CPUs that have ajhb2015-01-291-5/+10
| | | | | | | | | P-state but not C-state invariant TSC by changing the default behavior to leaving the TSC enabled as the timecounter and disabling C2+ instead of disabling the TSC by default. Discussed with: jkim Tested by: Jan Kokemuller <jan.kokemueller@gmail.com>
* loader: fix the size of MODINFOMD_MODULEProyger2015-01-201-1/+1
| | | | | | | | | The data in MODINFOMD_MODULEP is packed by the loader as a 4 byte type, but the amd64 kernel expects a vm_paddr_t, which is of size 8 bytes. Fix this by saving it as 8 bytes in the loader and retrieving it using the proper type in the kernel. Sponsored by: Citrix Systems R&D
* Update the vdso timehands only via tc_windup().neel2015-01-201-6/+7
| | | | | | | | | Prior to this change CLOCK_MONOTONIC could go backwards when the timecounter hardware was changed via 'sysctl kern.timecounter.hardware'. This happened because the vdso timehands update was missing the special treatment in tc_windup() when changing timecounters. Reviewed by: kib
* Include mca_machdep.h.imp2015-01-181-0/+3
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* Need to include opt_mca.h to test for DEV_MCA.imp2015-01-171-0/+1
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* loader: implement multiboot support for Xen Dom0royger2015-01-151-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a subset of the multiboot specification in order to boot Xen and a FreeBSD Dom0 from the FreeBSD bootloader. This multiboot implementation is tailored to boot Xen and FreeBSD Dom0, and it will most surely fail to boot any other multiboot compilant kernel. In order to detect and boot the Xen microkernel, two new file formats are added to the bootloader, multiboot and multiboot_obj. Multiboot support must be tested before regular ELF support, since Xen is a multiboot kernel that also uses ELF. After a multiboot kernel is detected, all the other loaded kernels/modules are parsed by the multiboot_obj format. The layout of the loaded objects in memory is the following; first the Xen kernel is loaded as a 32bit ELF into memory (Xen will switch to long mode by itself), after that the FreeBSD kernel is loaded as a RAW file (Xen will parse and load it using it's internal ELF loader), and finally the metadata and the modules are loaded using the native FreeBSD way. After everything is loaded we jump into Xen's entry point using a small trampoline. The order of the multiboot modules passed to Xen is the following, the first module is the RAW FreeBSD kernel, and the second module is the metadata and the FreeBSD modules. Since Xen will relocate the memory position of the second multiboot module (the one that contains the metadata and native FreeBSD modules), we need to stash the original modulep address inside of the metadata itself in order to recalculate its position once booted. This also means the metadata must come before the loaded modules, so after loading the FreeBSD kernel a portion of memory is reserved in order to place the metadata before booting. In order to tell the loader to boot Xen and then the FreeBSD kernel the following has to be added to the /boot/loader.conf file: xen_cmdline="dom0_mem=1024M dom0_max_vcpus=2 dom0pvh=1 console=com1,vga" xen_kernel="/boot/xen" The first argument contains the command line that will be passed to the Xen kernel, while the second argument is the path to the Xen kernel itself. This can also be done manually from the loader command line, by for example typing the following set of commands: OK unload OK load /boot/xen dom0_mem=1024M dom0_max_vcpus=2 dom0pvh=1 console=com1,vga OK load kernel OK load zfs OK load if_tap OK load ... OK boot Sponsored by: Citrix Systems R&D Reviewed by: jhb Differential Revision: https://reviews.freebsd.org/D517 For the Forth bits: Submitted by: Julien Grall <julien.grall AT citrix.com>
* For x86, read MAXPHYADDR, defined in SDM vol 3 4.1.4 Enumeration of Pagingkib2015-01-121-0/+3
| | | | | | | | | Features by CPUID as CPUID.80000008H:EAX[7:0], into variable cpu_maxphyaddr. Reviewed by: alc Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Right now, for non-coherent DMARs, page table update code flushes thekib2015-01-114-21/+54
| | | | | | | | | | | | | | | | | | | | | | cache for whole page containing modified pte, and more, only last page in the series of the consequtive pages is flushed (i.e. the affected mappings should be larger than 2MB). Avoid excessive flushing and do missed neccessary flushing, by splitting invalidation and unmapping. For now, flush exactly the range of the changed pte. This is still somewhat bigger than neccessary, since pte is 8 bytes, while cache flush line is at least 32 bytes. The originator of the issue reports that after the change, 'dmar_bus_dmamap_unload went from 13,288 cycles down to 3,257. dmar_bus_dmamap_load_buffer went from 9,686 cycles down to 3,517. and I am now able to get line 1GbE speed with Netperf TCP (even with 1K message size).' Diagnosed and tested by: Nadav Amit <nadav.amit@gmail.com> Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Fix calculation of requester for PCI device behind PCIe/PCI bridge.kib2015-01-101-25/+27
| | | | | | | | | | | | | | | | | | | In my case on the test machine, I have hierarchy of pcib2 (PCIe port on host bridge with PCIe capability) -> pci2 -> pcib3 (ITE PCIe/PCI bridge) -> pci3 -> em1 The device to check PCIe capability is pcib2 and not pcib3, as it is currently done in the code. Also, in case of the bridge, we shall step to pcib2 for the loop iteration, since pcib3 does not carry PCIe capability info and would force wrong recalculation of rid. Also change the returned requester to the PCIe bus which provides port for the bridge. This only results in changing hw.busdma.pciX.X.X.X.bounce tunable to force identity-mapped context for the device. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Print rid when announcing DMAR context creation. Print sid when faultkib2015-01-102-4/+5
| | | | | | | | occurs. This allows to connect dots in case the requester is calculated erronously. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Fix DMAR context allocations for the devices behind PCIe->PCI bridgeskib2015-01-091-1/+1
| | | | | | | | | after dmar driver was converted to use rids. The bus component to calculate context page must be taken from the requestor rid, which is a bridge, and not from the device bus number. Sponsored by: The FreeBSD Foundation MFC after: 1 week
* Update Features2 to display SDBG capability of processor. This issbruno2015-01-082-1/+2
| | | | | | | | | | | | | | showing up on Haswell-class CPUs From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register" 11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. Submitted by: jiashiun@gmail.com Reviewed by: jhb neel MFC after: 2 weeks
* Create a cpuset mask for each NUMA domain that is available in thejhb2015-01-081-1/+2
| | | | | | | | | | | kernel via the global cpuset_domain[] array. To export these to userland, add a CPU_WHICH_DOMAIN level that can be used to fetch the mask for a specific domain. Add a -d flag to cpuset(1) that can be used to fetch the mask for a given domain. Differential Revision: https://reviews.freebsd.org/D1232 Submitted by: jeff (kernel bits) Reviewed by: adrian, jeff
* Factor out duplicated code from dumpsys() on each architecture into genericmarkj2015-01-072-333/+96
| | | | | | | | | | | | | | code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly identical and simply redefine a number of constants and helper subroutines; a generic implementation will make it easier to implement features around kernel core dumps. This change does not alter any minidump code and should have no functional impact. PR: 193873 Differential Revision: https://reviews.freebsd.org/D904 Submitted by: Conrad Meyer <conrad.meyer@isilon.com> Reviewed by: jhibbits (earlier version) Sponsored by: EMC / Isilon Storage Division
* On some Intel CPUs with a P-state but not C-state invariant TSC the TSCjhb2015-01-051-6/+6
| | | | | | | | | | | | may also halt in C2 and not just C3 (it seems that in some cases the BIOS advertises its C3 state as a C2 state in _CST). Just play it safe and disable both C2 and C3 states if a user forces the use of the TSC as the timecounter on such CPUs. PR: 192316 Differential Revision: https://reviews.freebsd.org/D1441 No objection from: jkim MFC after: 1 week
* Fix warning about possible use of uninitialized variable.hselasky2015-01-021-1/+1
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* xen/intr: balance dynamic interrupts across available vCPUsroyger2014-12-101-0/+11
| | | | | | | | | | | | By default Xen binds all event channels to vCPU#0, and FreeBSD only shuffles the interrupt sources once, at the end of the boot process. Since new event channels might be created after this point (because new devices or backends are added), try to automatically shuffle them at creation time. This does not affect VIRQ or IPI event channels, that are already bound to a specific vCPU as requested by the caller. Sponsored by: Citrix Systems R&D
* xen: mask event channels while binding them to a vCPUroyger2014-12-101-11/+12
| | | | | | | | Mask the event channel source before trying to bind it to a CPU, this prevents stray interrupts from firing while assigning them and hitting the KASSERT in xen_intr_handle_upcall. Sponsored by: Citrix Systems R&D
* xen: convert the Grant-table code to a NewBus deviceroyger2014-12-101-9/+0
| | | | | | | This allows the Grant-table code to attach directly to the xenpv bus, allowing us to remove the grant-table initialization done in xenpv. Sponsored by: Citrix Systems R&D
* xen: create a new PCI bus overrideroyger2014-12-091-46/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When running as a Xen PVH Dom0 we need to add custom buses that override some of the functionality present in the ACPI PCI Bus and the PCI Bus. We currently override the ACPI PCI Bus, but not the PCI Bus, so add a new override for the PCI Bus and share the generic functions between them. Reported by: David P. Discher <dpd@dpdtech.com> Sponsored by: Citrix Systems R&D conf/files.amd64: - Add the new files. x86/xen/xen_pci_bus.c: - Generic file that contains the PCI overrides so they can be used by the several PCI specific buses. xen/xen_pci.h: - Prototypes for the generic overried functions. dev/xen/pci/xen_pci.c: - Xen specific override for the PCI bus. dev/xen/pci/xen_acpi_pci.c: - Xen specific override for the ACPI PCI bus.
* xen: notify ACPI about SCI overrideroyger2014-12-091-0/+9
| | | | | | | | If the SCI is remapped to a non-ISA global interrupt notify the ACPI subsystem about the override. Reported by: David P. Discher <dpd@dpdtech.com> Sponsored by: Citrix Systems R&D
* Improve support for XSAVE with debuggers.jhb2014-11-212-12/+22
| | | | | | | | | | | | | | | | | | | - Dump an NT_X86_XSTATE note if XSAVE is in use. This note is designed to match what Linux does in that 1) it dumps the entire XSAVE area including the fxsave state, and 2) it stashes a copy of the current xsave mask in the unused padding between the fxsave state and the xstate header at the same location used by Linux. - Teach readelf() to recognize NT_X86_XSTATE notes. - Change PT_GET/SETXSTATE to take the entire XSAVE state instead of only the extra portion. This avoids having to always make two ptrace() calls to get or set the full XSAVE state. - Add a PT_GET_XSTATE_INFO which returns the length of the current XSTATE save area (so the size of the buffer needed for PT_GETXSTATE) and the current XSAVE mask (%xcr0). Differential Revision: https://reviews.freebsd.org/D1193 Reviewed by: kib MFC after: 2 weeks
* MFamd64: Add support for extended FPU states on i386. This includesjhb2014-11-021-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | support for AVX on i386. - Similar to amd64, move the FPU save area out of the PCB and instead store saved FPU state in a variable-sized buffer after the PCB on the stack. - To support the variable PCB location, alter the locore code to only use the bottom-most page of proc0stack for init386(). init386() returns the correct stack pointer to locore which adjusts the stack for thread0 before calling mi_startup(). - Don't bother setting cr3 in thread0's pcb in locore before calling init386(). It wasn't used (init386() overwrote it at the end) and it doesn't work with the variable-sized FPU save area. - Remove the new-bus attachment from npx. This was only ever useful for external co-processors using IRQ13, but those have not been supported for several years. npxinit() is now called much earlier during boot (init386()) similar to amd64. - Implement PT_{GET,SET}XSTATE and I386_GET_XFPUSTATE. - npxsave() is now only called from context switch contexts so it can use XSAVEOPT. Differential Revision: https://reviews.freebsd.org/D1058 Reviewed by: kib Tested on: FreeBSD/i386 VM under bhyve on Intel i5-2520
* Rework virtual machine hypervisor detection.jhb2014-10-283-74/+174
| | | | | | | | | | | | | | | - Move the existing code to x86/x86/identcpu.c since it is x86-specific. - If the CPUID2_HV flag is set, assume a hypervisor is present and query the 0x40000000 leaf to determine the hypervisor vendor ID. Export the vendor ID and the highest supported hypervisor CPUID leaf via hv_vendor[] and hv_high variables, respectively. The hv_vendor[] array is also exported via the hw.hv_vendor sysctl. - Merge the VMWare detection code from tsc.c into the new probe in identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in the TSC code to identify VMWare. Differential Revision: https://reviews.freebsd.org/D1010 Reviewed by: delphij, jkim, neel
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