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* MFC r312001:pfg2017-02-031-4/+4
| | | | | | | | | | | Remove __nonnull() attributes from x86 machine check architecture. In this case the attributes serve little purpose as they just don't enforce run time checks, If anything the attributes would cause NULL pointer checks to be ignored but there are no such checks so the only effect is cosmetic. Reviewed by: jhb, avg
* MFC 308005: Add powerd(8) support for several families of AMD CPUs.jhb2016-12-021-7/+9
| | | | | | | | | | | | | | Use the same logic to calculate the nominal CPU frequency from the P-state MSRs on family 0x12, 0x15, and 0x16 CPUs as is used for family 0x10. Family 0x14 was included in the original patch in the PR but I left that out as the BIOS writer's guide for family 0x14 CPUs show a different layout for the relevant MSR and include a different formulate for calculating the frequency. While here, simplify a few expressions and print out the family of unsupported CPUs in hex rather than decimal. PR: 212020
* MFC 307333: Reprogram I/O APIC interrupt pins when registering an I/O APIC.jhb2016-11-251-2/+9
| | | | | | | | | | | | | | | | All I/O APIC pins are masked when an I/O APIC is first probed. The APIC enumerator (MP Table or MADT) then parses its associated tables to configure individual pins to set custom delivery modes or alternate routing (e.g. routing IRQ 0 to intpin 2). Pins for regular interrupt pins are left masked until the first interrupt is assigned. However, pins with unusual settings (e.g. NMI or SMI) are never assigned an interrupt and thus never re-programmed. The I/O APIC code used to reprogram all interrupt pins during registration but this was lost in r151979. In theory, this is mostly a no-op as the ACPI APIC table does not include a way to enumerate NMI or SMI pins for the I/O APIC, so only systems using an MP Table would be affected.
* MFC 306481sephe2016-10-141-0/+12
| | | | | | | | | | | | x86/ioapic: Fix destination cpu for Hyper-V On Hyper-V: - Stick to the first cpu for all I/O APIC pins. - And don't allow destination cpu changes. Reviewed by: jhb Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D7949
* MFC 305722sephe2016-10-141-19/+22
| | | | | | | | | | | | | | | | | | | x86: Use sx lock for interrupt sources. - Certain pic_assign_cpu, e.g. msi_assign_cpu can have quite a long call chain. For msi_assign_cpu, mutex makes complex PCI bridge drivers more tricky, e.g. sleep can note be called, etc, it will be pretty tricky for upcoming Hyper-V PCI bridge driver for PCI pass-through. - It is not used on any hot code path nor non-sleepable context, so sx should have the same effect as mutex. PIC list is still protected by mutex to keep suspend/resume work. Discussed with: jhb Reviewed by: jhb Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D7784
* MFC r303491:royger2016-10-131-12/+3
| | | | | | Revert r291022: x86/intr: allow mutex recursion in intr_remove_handler Sponsored by: Citrix Systems R&D
* MFC: r284583, r285797, r285799, r287168, r298714, r298720, r298838,jkim2016-09-301-2/+2
| | | | | | | | r300879 Merge ACPICA up to 20160527. Requested by: mav
* MFC 303886: Add additional constants.jhb2016-09-301-0/+4
| | | | | | | | | | - Add constants for the fields in the root-entry table address register, namely the root type type (RTT) and root table address (RTA) mask. - Add macros for the bitmask of the domain ID field in the second word of context table entries as well as a helper macro (DMAR_CTX2_GET_DID) to extract the domain ID from a context table entry. Sponsored by: Chelsio Communications
* MFC r305744:kib2016-09-151-1/+1
| | | | Fix typo in comment.
* MFC 304637: Fix build for !SMP kernels after the Xen MSIX workaround.jhb2016-09-092-0/+8
| | | | | | | Move msix_disable_migration under #ifdef SMP since it doesn't make sense for !SMP kernels. PR: 212014
* MFC r303891, r303892:pfg2016-09-081-3/+3
| | | | | | | | sys: replace comma with semicolon when pertinent. Uses of commas instead of a semicolons can easily go undetected. The comma can serve as a statement separator but this shouldn't be abused when statements are meant to be standalone.
* MFC 302181,302635: Disable MSI-X migration on older Xen hypervisors.jhb2016-08-052-2/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | 302181: Add a tunable to disable migration of MSI-X interrupts. The new 'machdep.disable_msix_migration' tunable can be set to 1 to disable migration of MSI-X interrupts. Xen versions prior to 4.6.0 do not properly handle updates to MSI-X table entries after the initial write. In particular, the operation to unmask a table entry after updating it during migration is not propagated to the "real" table for passthrough devices causing the interrupt to remain masked. At least some systems in EC2 are affected by this bug when using SRIOV. The tunable can be set in loader.conf as a workaround. 302635: xen: automatically disable MSI-X interrupt migration If the hypervisor version is smaller than 4.6.0. Xen commits 74fd00 and 70a3cb are required on the hypervisor side for this to be fixed, and those are only included in 4.6.0, so stay on the safe side and disable MSI-X interrupt migration on anything older than 4.6.0. It should not cause major performance degradation unless a lot of MSI-X interrupts are allocated.
* MFC r301278kib2016-06-101-3/+3
| | | | | | | Reduce number of iterations used for calibrating ICR read loop. MFC r301279: Record correct commit message for r301278.
* MFC r299004: Work around (ignore) broken SRAT tablesvangyzen2016-05-111-2/+6
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* MFC r297857: re-enable AMD Topology extension on certain models ifavg2016-05-042-12/+28
| | | | disabled by BIOS
* MFC 297039,297374,297398,297484:jhb2016-04-271-13/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Poll the IPI status while waiting constantly instead of delaying 5 microseconds between checks. This avoids inserting a minimum latency of 5 microseconds on each IPI. 297039: Check IPI status more frequently when waiting. An IPI cannot be sent via the local APIC if a previous IPI is still being delivered. Attempts to send an IPI will wait for a pending IPI to clear. Prior to r278325 these checks used a spin loop with a hardcoded maximum count which broke AP startup on some systems. However, r278325 also enforced a minimum latency of 5 microseconds if an IPI was still pending which resulted in a measurable performance hit. This change reduces that minimum latency to 1 microsecond. 297374: Calibrate the frequency of the of the native_lapic_ipi_wait() loop, and avoid a delay while waiting for IPI delivery acknowledgement in xAPIC mode. This makes the loop exit immediately after the delivery bit in APIC_ICR register is set, instead of waiting for some microseconds. We only need to ensure that some amount of time is allowed for the LAPIC to react to the command, and we need that the wait time is finite and reasonable. For that reasons, it is irrelevant if the CPU frequency or throttling decrease the speed and make the loop, calibrated for full CPU speed at boot time, execute somewhat slower. 297398: Fix several bugs in r297374: - fix UP build [1] - do not obliterate initial reading of rdtsc by the loop counter [2] - restore the meaning of the argument -1 to native_lapic_ipi_wait() as wait until LAPIC acknowledge without timeout - correct formula for calculating loop iteration count for 1us, it was inverted, and ensure that even on unlikely slow CPUs at least one check for ack is performed. 297484: Style(9), use tabs for the #define LOOPS line. Print unsigned values with %u. Make code slightly more compact by inlining loop limit.
* MFC r298101:kib2016-04-232-2/+26
| | | | Add x86 CPU features definitions published in the Intel SDM rev. 58.
* MFC [Hyper-V]: r293719-r293722, r293869-r293871, r293873-r293875, r293877sephe2016-02-191-0/+2
| | | | | | | | | | | | | | | | | r293719 hyperv/hn: Implement LRO r293720 hyperv/hn: Implement SIOC[SG]IFMEDIA support r293721 hyperv/hn: Avoid mbuf cluster allocation, if the packet is small. r293722 hyperv/hn: Removed unused netvsc_init() r293869 hyperv/hn: Unbreak LINT-NOIP r293870 hyperv: use x86 generic code to do the hypervisor detection r293871 hyperv: remove unused vmbus definitions r293873 hyperv: implement an event timer r293874 hyperv: add interrupt counters r293875 hyperv: set receive buffer size according to NVSP protocol version r293877 Unbreak `make depend` with sys/modules/hyperv/vmbus after r293870 Approved by: re (glebius), adrian (mentor) Sponsored by: Microsoft OSTC
* MFC r289618, r290316:ian2016-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix printf format to allow for bus_size_t not being u_long on all platforms. Fix an alignment check that is wrong in half the busdma implementations. This will enable the elimination of a workaround in the USB driver that artifically allocates buffers twice as big as they need to be (which actually saves memory for very small buffers on the buggy platforms). When deciding how to allocate a dma buffer, armv4, armv6, mips, and x86/iommu all correctly check for the tag alignment <= maxsize as enabling simple uma/malloc based allocation. Powerpc, sparc64, x86/bounce, and arm64/bounce were all checking for alignment < maxsize; on those platforms when alignment was equal to the max size it would fall back to page-based allocators even for very small buffers. This change makes all platforms use the <= check. It should be noted that on all platforms other than arm[v6] and mips, this check is relying on undocumented behavior in malloc(9) that if you allocate a block of a given size it will be aligned to the next larger power-of-2 boundary. There is nothing in the malloc(9) man page that makes that explicit promise (but the busdma code has been relying on this behavior all along so I guess it works). Arm and mips code uses the allocator in kern/subr_busdma_buffalloc.c, which does explicitly implement this promise about size and alignment. Other platforms probably should switch to the aligned allocator.
* MFC r293343: Move amd64 metadata.h to x86 and share with i386emaste2016-01-181-0/+57
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* MFC r292890:kib2016-01-052-0/+3
| | | | Add standard extended feature bit 6 from the Intel SDM rev. 57.
* MFC: r286785, r291088, r291120marius2015-12-271-36/+37
| | | | | | | | | | | | | | | | - Reformat x86 bounce buffer synchronization code to reduce indentation. No functional change. - Avoid a NULL pointer dereference in bounce_bus_dmamap_sync() when the map has been created via bounce_bus_dmamem_alloc(). Even for coherent DMA - which bus_dmamem_alloc(9) typically is used for -, calling of bus_dmamap_sync(9) isn't optional. [1] - Avoid a NULL pointer dereference in bounce_bus_dmamap_unload() when the map has been created via bounce_bus_dmamem_alloc(). In that case bus_dmamap_unload(9) typically isn't called during normal operation but still should be during detach, cleanup from failed attach etc. [2] PR: 188899 (non-original problem) [1] Submitted by: yongari [2]
* MFC r291024:royger2015-12-031-20/+1
| | | | | | xen: fix dropping bitmap IPIs during resume Sponsored by: Citrix Systems R&D
* Revert MFC of r291023:royger2015-12-021-3/+0
| | | | | Due to the delta between HEAD and stable/10 event channel code, this fix is not needed on stable/10 and was also causing build issues. Revert it.
* MFC r291023:royger2015-12-021-0/+3
| | | | | | xen/intr: properly dispose event channels on resume Sponsored by: Citrix Systems R&D
* MFC r291022:royger2015-12-021-3/+12
| | | | | | x86/intr: allow mutex recursion in intr_remove_handler Sponsored by: Citrix Systems R&D
* MFC r291266:kib2015-11-271-1/+1
| | | | | Correct the number of DTLB entries reported for the CPUID Leaf 2 descriptor 0x6c.
* MFC r286999:royger2015-11-241-4/+23
| | | | | | xen: allow disabling PV disks and nics Sponsored by: Citrix Systems R&D
* MFC r289823:kib2015-10-301-0/+12
| | | | | Decode new values for CPUID leaf 2 cache and TLB descriptors, from the Intel SDM revision 56.
* MFC 284175:jhb2015-10-011-32/+65
| | | | | | | | | | | Handle X2APIC entries in the MADT for APICs with an ID < 255. At least one BIOS has been seen to include such entries even though the relevant specs require that X2APIC entries only be used for CPUs with an APIC ID >= 255. This was tested on a system with "plain" local APIC entries in the MADT to ensure no regressions, but it has not yet been tested on a system with X2APIC entries in the MADT. Currently such systems do not boot at all, and with this change they might now boot correctly.
* MFC r276834sbruno2015-09-042-1/+2
| | | | | | | | | | | | | Update Features2 to display SDBG capability of processor. This is showing up on Haswell-class CPUs From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register" 11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. Submitted by: jiashiun@gmail.com
* MFC: r286265, r286293, r286328jkim2015-08-251-2/+10
| | | | Always define __va_list for amd64 and restore pre-r232261 behavior for i386.
* MFC r286667 & r286723marcel2015-08-252-21/+63
| | | | | | | Better support memory mapped console devices, such as VGA and EFI frame buffers and memory mapped UARTs. PR: 191564, 194952, 202276
* MFC r286777:kib2015-08-171-2/+3
| | | | Comment only change, fix grammar and somewhat clarify the action.
* MFC r286228:kib2015-08-171-16/+30
| | | | Clear the IA32_MISC_ENABLE MSR bit on APs.
* Implement x86 ptrace(2) requests PT_{GET,SET}{FS,GS}BASE.kib2015-08-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | MFC r284918: Add helper fill_based_sd(9). MFC r284919: Add x86 PT_GETFSBASE, PT_GETGSBASE machine-depended ptrace requests to obtain the thread %fs and %gs bases. Add x86 PT_SETFSBASE and PT_SETGSBASE requests to set the bases from debuggers. The set requests, similarly to the sysarch({I386,AMD64}_SET_FSBASE), override the corresponding segment registers. MFC r284965: Document x86 machine-specific ptrace(2) requests. MFC r285011: Disallow a debugger on 64bit system to set fs/gs bases of the 32bit process beyond the end of the process address space. MFC r285104: Grammar and language fixes.
* MFC r285932:kib2015-08-041-0/+11
| | | | Add bit names for the IA32_MISC_ENABLE msr.
* MFC: r284931brueffer2015-07-131-1/+1
| | | | | | | | | | | | | Set the initial system time to a sane (as in: not end of 21st century) value when booting on a PC with CMOS clock set to a year before 2000. This uses 1980 (instead of 1970 as in the initial patch) as pivot year as suggested by imp in the PR followup. PR: 195703 Submitted by: cs@soi.spb.ru Reviewed by: imp Approved by: re (gjb)
* MFC: r281751marius2015-07-051-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Refine the workaround for Intel HSD131 [1] added in r269052 (MFCed to stable/10 in r269592): - Use the full mask described by the erratum as with a sufficiently high number of these false-positives, the overflow bit (bit 62) additionally gets set [7]. - HSD131 has been brought into several other Haswell-derived CPUs including to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of these benign errors by default on CPU models affected by HSM142, HSW131 and BDM48 [2 - 5], describing the HSD131 silicon bug for additional models. Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered by this fault [6], with the specification update concerned with HSM142 [2] only referring to 0x3c and 0x46. Submitted by: David Froehlich [7] Approved by: re (kib) http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf [1] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf [2] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf [3] http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf [4] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf [5] https://lists.freebsd.org/pipermail/freebsd-hackers/2015-January/046878.html [6]
* MFC r282209:neel2015-06-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emulate the 'bit test' instruction. MFC r282259: Re-implement RTC current time calculation to eliminate the possibility of losing time. MFC r282281: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs. MFC r282284: When an instruction cannot be decoded just return to userspace so bhyve(8) can dump the instruction bytes. MFC r282287: Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>. MFC r282296: Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are enabled. MFC r282301: Relax limits when transitioning a vector from the IRR to the ISR and also when extinguishing it from the ISR in response to an EOI. MFC r282335: Advertise an additional memory BAR in the "dummy" device emulation. MFC r282336: Emulate machine check related MSRs to allow guest OSes like Windows to boot. MFC r282351: Don't advertise the Intel SMX capability to the guest. MFC r282407: Emulate the 'CMP r/m8, imm8' instruction. MFC r282519: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE. MFC r282520: Emulate guest writes to EFER_MSR properly. MFC r282558: Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup(). MFC r282571: Check 'td_owepreempt' and yield the vcpu thread if it is set. MFC r282595: Allow byte reads of AHCI registers. MFC r282784: Handling indirect descriptors is a capability of the host and not one that needs to be negotiated. Use the host capabilities field and not the negotiated field when verifying that indirect descriptors are supported. MFC r282788: Allow configuration of the sector size advertised to the guest. MFC r282865: Set the subvendor field in config space to the vendor ID. This is required by the Windows virtio drivers to correctly match a device. MFC r282922: Bump the size of the blockif scatter-gather list to 67. MFC r283075: Fix off-by-one in array index bounds check. bhyveload would allow you to create 33 entries on an array that only has 32 slots MFC r283168: Temporarily revert r282922 which bumped the max descriptors. MFC r283255: Emulate the "CMP r/m, reg" instruction (opcode 39H). MFC r283256: Add an option "--get-vmcs-exit-inst-length" to display the instruction length of the instruction that caused the VM-exit. MFC r283264: Change the header type of the emulated host-bridge from type 1 to type 0. MFC r283293: Don't rely on the 'VM-exit instruction length' field in the VMCS to always have an accurate length on an EPT violation. MFC r283299: Remove bogus verification of instruction length after instruction decode. MFC r283308: Exceptions don't deliver an error code in real mode. MFC r283657: Fix non-deterministic delays when accessing a vcpu that was in "running" or "sleeping" state. MFC r283973: Use tunable 'hw.vmm.svm.features' to disable specific SVM features even though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids' to limit the number of ASIDs used by the hypervisor. MFC r284046: Fix regression in 'verify_gla()' with the RIP-relative addressing mode. MFC r284174: Support guest writes to the TSC by enabling the "use TSC offsetting" execution control.
* MFC r284104:kib2015-06-131-3/+180
| | | | Updates from SDM rev. 55.
* MFC r283735:kib2015-06-052-9/+3
| | | | Remove several write-only variables.
* MFC r283692:kib2015-06-051-0/+2
| | | | Explicitely enable queued invalidation completion interrupt.
* MFC 281887:jhb2015-06-024-4/+4
| | | | | Reassign copyright statements on several files from Advanced Computing Technologies LLC to Hudson River Trading LLC.
* MFC 281266:jhb2015-06-021-0/+1
| | | | | | | | | | | | Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h> and export them to userland. - Define __HAVE_REG32 on platforms that define a reg32 structure and check for this in <sys/procfs.h> to control when to export prstatus32, etc. - Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures. libbfd looks for these types, and having them fixes 'gcore' in gdb of a 32-bit process on a 64-bit platform. - Use the structure definitions from <sys/procfs.h> in gcore's elf32 core dump code instead of duplicating the definitions.
* MFC r282120:hselasky2015-05-051-2/+2
| | | | | | | | | | | | The add_bounce_page() function can be called when loading physical pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET flag is set, use the physical address to compute the page offset instead. The physical address should always be valid when adding bounce pages and should contain the same page offset like the virtual address. Submitted by: Svatopluk Kraus <onwahe@gmail.com> Reviewed by: jhb@
* MFC r281495:kib2015-04-271-1/+1
| | | | | | | | | | | | Add config option PAE_TABLES for the i386 kernel. It switches pmap to use PAE format for the page tables, but does not incur other consequences of the full PAE config. In particular, vm_paddr_t and bus_addr_t are left 32bit, and max supported memory is still limited by 4GB. The option allows to have nx permissions for memory mappings on i386 kernel, while keeping the usual i386 KBI and avoiding the kernel data sizing problems typical for the PAE config.
* MFC: r281396, r281475jkim2015-04-181-1/+1
| | | | | | Merge ACPICA 20150410. Relnotes: yes
* MFC 278325,280866:jhb2015-04-151-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert the IPI startup sequence to match what is described in the Intel Multiprocessor Specification v1.4. The Intel SDM claims that 278325: Revert the IPI startup sequence to match what is described in the Intel Multiprocessor Specification v1.4. The Intel SDM claims that the INIT IPIs here are invalid, but other systems follow the MP spec instead. While here, fix the IPI wait routine to accept a timeout in microseconds instead of a raw spin count, and don't spin forever during AP startup. Instead, panic if a STARTUP IPI is not delivered after 20 us. 280866: Wait 100 microseconds for a local APIC to dispatch each startup-related IPI rather than 20. The MP 1.4 specification states in Appendix B.2: "A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal operating conditions". (Note that this appears to be separate from the 10 millisecond (INIT) and 200 microsecond (STARTUP) waits after the IPIs are dispatched.) The Intel SDM is silent on this issue as far as I can tell. At least some hardware requires 60 microseconds as noted in the PR, so bump this to 100 to be on the safe side. PR: 196542, 197756
* MFC r281254:kib2015-04-153-21/+32
| | | | | Account for the offset of the page run when allocating the dmar_map_entry.
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