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* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+1
* Each processor socket in a QPI system has a special PCI bus for thejhb2010-09-071-13/+45
* When DTrace is enabled, make sure we don't overwrite the IDT_DTRACE_RETrpaulo2010-08-301-0/+25
* Correctly ensure that the CPU family is 0x6, not non-zero.jhb2010-08-251-1/+2
* Intel QPI chipsets actually provide two extra "non-core" PCI buses thatjhb2010-08-251-0/+286
* Enable timer interrupt before starting timer. This allows to handle verymav2010-08-241-8/+7
* When performing a sanity check on the SRAT table to ensure that eachjhb2010-07-291-1/+2
* The corrected error count field is dependent on CMCI, not TES.jhb2010-07-281-1/+1
* Add a parser for the ACPI SRAT table for amd64 and i386. It setsjhb2010-07-271-0/+329
* Increment td->td_intr_nesting_level for LAPIC timer interrupts. Among othermav2010-07-241-0/+2
* Fix several un-/signedness bugs of r210290 and r210293. Add one more check.mav2010-07-203-7/+8
* Extend timer driver API to report also minimal and maximal supported periodmav2010-07-203-1/+21
* Move timeevents.c to MI code, as it is not x86-specific. I already havemav2010-07-141-508/+0
* Remove some unneeded includes. Code now can be built on ARM.mav2010-07-141-3/+0
* Rise knowledge about curthread->td_intr_frame by one step. Make timermav2010-07-134-13/+7
* Unify pc98 event timer code with the rest of x86.mav2010-07-131-0/+97
* Instead of deleting existing IRQ resource, which is not really working formav2010-07-122-3/+13
* Make kernel panic with reasonable message if no usable event timer found.mav2010-07-111-0/+2
* Allow attimer to be hinted at ISA if not reported by ISA PNP or ACPI.mav2010-07-012-7/+12
* Rework r209456:mav2010-07-012-2/+4
* Do not trust IRQ reported by ACPI. There are cases when it is wrong.mav2010-06-232-0/+2
* Add "legacy route" support to HPET driver. When enabled, this mode makesmav2010-06-222-28/+32
* Fix i386 LINT build broken by r209371.mav2010-06-211-0/+3
* Implement new event timers infrastructure. It provides unified APIs formav2010-06-204-354/+845
* Core i5, same as previously Core2Duo, found to not set P-state for singlemav2010-06-191-6/+2
* Restore the machine check register banks on resume. For banks beingjhb2010-06-151-19/+66
* Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSImav2010-06-141-1/+2
* Update several places that iterate over CPUs to use CPU_FOREACH().jhb2010-06-111-4/+2
* Do not disable edge-triggered interrupts before migration. DELAY() withmav2010-06-101-1/+1
* Move the MD support for PCI message signalled interrupts to the x86 treejhb2010-06-081-0/+602
* Move the machine check support code to the x86 tree since it is identicaljhb2010-06-081-0/+889
* Move the I/O APIC code to the x86 tree since it is identical on i386 andjhb2010-06-081-0/+922
* Add support for corrected machine check interrupts. CMCI is a new localjhb2010-05-241-1/+39
* - Implement MI helper functions, dividing one or two timer interrupts withmav2010-05-242-83/+16
* Restore different APIC init orders for i386 and amd64 unified in r208452.mav2010-05-241-2/+24
* Unify local_apic.c for x86 archs,mav2010-05-231-0/+1437
* Fix another instance of lapic_cyclic_clock_func.rpaulo2010-04-201-2/+2
* Default the machdep.lapic_allclocks to be enabled in order to cope withattilio2010-04-091-1/+1
* Improving the clocks auto-tunning by firstly checking if the atrtc may beattilio2010-03-031-5/+20
* Introduce the new kernel sub-tree x86 which should contain all the codeattilio2010-02-2517-0/+7491
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