summaryrefslogtreecommitdiffstats
path: root/sys/x86
Commit message (Collapse)AuthorAgeFilesLines
* atrtc: remove (pre-)historic check of RTC NVRAM at address 0x0eavg2010-10-161-4/+1
| | | | | | | | | | | | | | Old scrolls tell that once upon a time IBM AT BIOS was known to put some useful system diagnostic information into RTC NVRAM. It is not really known if and for how long PC BIOSes followed that convention, but I believe that many, if not all, modern BIOSes do not do that any more (not mentioning other types of x86 firmware). Some diagnostic bits don't even make any sense any longer. The check results in confusing messages upon boot on some systems. So I am removing it. Discussed with: bde, jhb, mav MFC after: 3 weeks
* Restore pre-r212778 optimization, skipping timer reprogramming when it ismav2010-09-181-19/+27
| | | | | | | | not neccessary. It allows to avoid time counter jump of up to 1/18s, when base frequency slightly tuned via machdep.i8254_freq sysctl. Fix few style things. Suggested by: bde
* Add one-shot mode support to attimer (i8254) event timer.mav2010-09-171-44/+71
| | | | | | | | Unluckily, using one-shot mode is impossible, when same hardware used for time counting. Introduce new tunable hint.attimer.0.timecounter, setting which to 0 disables i8254 time counter and allows one-shot mode. Note, that on some systems there may be no other reliable enough time counters, so this tunable should be used with understanding.
* Few whitespace cleanups and comments tunings.mav2010-09-161-10/+12
| | | | Submitted by: arundel
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main goal of this is to generate timer interrupts only when there is some work to do. When CPU is busy interrupts are generating at full rate of hz + stathz to fullfill scheduler and timekeeping requirements. But when CPU is idle, only minimum set of interrupts (down to 8 interrupts per second per CPU now), needed to handle scheduled callouts is executed. This allows significantly increase idle CPU sleep time, increasing effect of static power-saving technologies. Also it should reduce host CPU load on virtualized systems, when guest system is idle. There is set of tunables, also available as writable sysctls, allowing to control wanted event timer subsystem behavior: kern.eventtimer.timer - allows to choose event timer hardware to use. On x86 there is up to 4 different kinds of timers. Depending on whether chosen timer is per-CPU, behavior of other options slightly differs. kern.eventtimer.periodic - allows to choose periodic and one-shot operation mode. In periodic mode, current timer hardware taken as the only source of time for time events. This mode is quite alike to previous kernel behavior. One-shot mode instead uses currently selected time counter hardware to schedule all needed events one by one and program timer to generate interrupt exactly in specified time. Default value depends of chosen timer capabilities, but one-shot mode is preferred, until other is forced by user or hardware. kern.eventtimer.singlemul - in periodic mode specifies how much times higher timer frequency should be, to not strictly alias hardclock() and statclock() events. Default values are 2 and 4, but could be reduced to 1 if extra interrupts are unwanted. kern.eventtimer.idletick - makes each CPU to receive every timer interrupt independently of whether they busy or not. By default this options is disabled. If chosen timer is per-CPU and runs in periodic mode, this option has no effect - all interrupts are generating. As soon as this patch modifies cpu_idle() on some platforms, I have also refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions (if supported) under high sleep/wakeup rate, as fast alternative to other methods. It allows SMP scheduler to wake up sleeping CPUs much faster without using IPI, significantly increasing performance on some highly task-switching loads. Tested by: many (on i386, amd64, sparc64 and powerc) H/W donated by: Gheorghe Ardelean Sponsored by: iXsystems, Inc.
* Each processor socket in a QPI system has a special PCI bus for thejhb2010-09-071-13/+45
| | | | | | | | "uncore" devices (such as the memory controller) in that socket. Stop hardcoding support for two busses, but instead start probing buses at domain 0, bus 255 and walk down until a bus probe fails. Also, do not probe a bus if it has already been enumerated elsewhere (e.g. if ACPI ever enumerates these buses in the future).
* When DTrace is enabled, make sure we don't overwrite the IDT_DTRACE_RETrpaulo2010-08-301-0/+25
| | | | | | | entry with an IRQ for some hardware component. Reviewed by: jhb Sponsored by: The FreeBSD Foundation
* Correctly ensure that the CPU family is 0x6, not non-zero.jhb2010-08-251-1/+2
| | | | Submitted by: Dimitry Andric
* Intel QPI chipsets actually provide two extra "non-core" PCI buses thatjhb2010-08-251-0/+286
| | | | | | | | | | provide PCI devices for various hardware such as memory controllers, etc. These PCI buses are not enumerated via ACPI however. Add qpi(4) psuedo bus and Host-PCI bridge drivers to enumerate these buses. Currently the driver uses the CPU ID to determine the bridges' presence. In collaboration with: Joseph Golio @ Isilon Systems MFC after: 2 weeks
* Enable timer interrupt before starting timer. This allows to handle verymav2010-08-241-8/+7
| | | | short periods without interrupt loss.
* When performing a sanity check on the SRAT table to ensure that eachjhb2010-07-291-1/+2
| | | | | | | memory domain has an assigned CPU, ignore disabled CPUs. Previously disabled CPUs were counted as being in domain 0. Reported by: mdf
* The corrected error count field is dependent on CMCI, not TES.jhb2010-07-281-1/+1
| | | | MFC after: 1 week
* Add a parser for the ACPI SRAT table for amd64 and i386. It setsjhb2010-07-271-0/+329
| | | | | | | PCPU(domain) for each CPU and populates a mem_affinity array suitable for the NUMA support in the physical memory allocator. Reviewed by: alc
* Increment td->td_intr_nesting_level for LAPIC timer interrupts. Among othermav2010-07-241-0/+2
| | | | | things it hints SCHED_ULE to run clock swi handlers on their native CPUs, avoiding many unneeded IPI_PREEMPT calls.
* Fix several un-/signedness bugs of r210290 and r210293. Add one more check.mav2010-07-203-7/+8
|
* Extend timer driver API to report also minimal and maximal supported periodmav2010-07-203-1/+21
| | | | | | lengths. Make MI wrapper code to validate periods in request. Make kernel clock management code to honor these hardware limitations while choosing hz, stathz and profhz values.
* Move timeevents.c to MI code, as it is not x86-specific. I already havemav2010-07-141-508/+0
| | | | | it working on Marvell ARM SoCs, and it would be nice to unify timer code between more platforms.
* Remove some unneeded includes. Code now can be built on ARM.mav2010-07-141-3/+0
|
* Rise knowledge about curthread->td_intr_frame by one step. Make timermav2010-07-134-13/+7
| | | | | callback argument really opaque. Not repeat interrupt handler's problem in case somebody will ever need to have both argument and frame.
* Unify pc98 event timer code with the rest of x86.mav2010-07-131-0/+97
| | | | Reviewed by: nyan@
* Instead of deleting existing IRQ resource, which is not really working formav2010-07-122-3/+13
| | | | | ACPI bus, find wanted IRQ rid or spare one. This should fix panic during boot on systems reporting fancy IRQ numbers for attimer and atrtc.
* Make kernel panic with reasonable message if no usable event timer found.mav2010-07-111-0/+2
|
* Allow attimer to be hinted at ISA if not reported by ISA PNP or ACPI.mav2010-07-012-7/+12
| | | | Rephrase respective atrtc code same way to be more readable.
* Rework r209456:mav2010-07-012-2/+4
| | | | | Instead of using fake rid (which ISA doesn't like), delete untrusted IRQ resource and let it be recreated.
* Do not trust IRQ reported by ACPI. There are cases when it is wrong.mav2010-06-232-0/+2
|
* Add "legacy route" support to HPET driver. When enabled, this mode makesmav2010-06-222-28/+32
| | | | | | | | | | | | HPET to steal IRQ0 from i8254 and IRQ8 from RTC timers. It can be suitable for HPETs without FSB interrupts support, as it gives them two unshared IRQs. It allows them to provide one per-CPU event timer on dual-CPU system, that should be suitable for further tickless kernels. To enable it, such lines may be added to /boot/loader.conf: hint.atrtc.0.clock=0 hint.attimer.0.clock=0 hint.hpet.0.legacy_route=1
* Fix i386 LINT build broken by r209371.mav2010-06-211-0/+3
| | | | There appeared such legacy thing as APM, that somehow breaking RTC.
* Implement new event timers infrastructure. It provides unified APIs formav2010-06-204-354/+845
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | writing event timer drivers, for choosing best possible drivers by machine independent code and for operating them to supply kernel with hardclock(), statclock() and profclock() events in unified fashion on various hardware. Infrastructure provides support for both per-CPU (independent for every CPU core) and global timers in periodic and one-shot modes. MI management code at this moment uses only periodic mode, but one-shot mode use planned for later, as part of tickless kernel project. For this moment infrastructure used on i386 and amd64 architectures. Other archs are welcome to follow, while their current operation should not be affected. This patch updates existing drivers (i8254, RTC and LAPIC) for the new order, and adds event timers support into the HPET driver. These drivers have different capabilities: LAPIC - per-CPU timer, supports periodic and one-shot operation, may freeze in C3 state, calibrated on first use, so may be not exactly precise. HPET - depending on hardware can work as per-CPU or global, supports periodic and one-shot operation, usually provides several event timers. i8254 - global, limited to periodic mode, because same hardware used also as time counter. RTC - global, supports only periodic mode, set of frequencies in Hz limited by powers of 2. Depending on hardware capabilities, drivers preferred in following orders, either LAPIC, HPETs, i8254, RTC or HPETs, LAPIC, i8254, RTC. User may explicitly specify wanted timers via loader tunables or sysctls: kern.eventtimer.timer1 and kern.eventtimer.timer2. If requested driver is unavailable or unoperational, system will try to replace it. If no more timers available or "NONE" specified for second, system will operate using only one timer, multiplying it's frequency by few times and uing respective dividers to honor hz, stathz and profhz values, set during initial setup.
* Core i5, same as previously Core2Duo, found to not set P-state for singlemav2010-06-191-6/+2
| | | | | | core lower then set on other cores. Do not try to test P-states on attach on SMP systems. It is hopeless now and will just pollute verbose logs. If needed, check still can be forced via loader tunable.
* Restore the machine check register banks on resume. For banks beingjhb2010-06-151-19/+66
| | | | | | | monitored via CMCI, reset the interrupt threshold to 1 on resume. Reviewed by: jkim MFC after: 2 weeks
* Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSImav2010-06-141-1/+2
| | | | (FSB interrupts) to be used by non-PCI devices, such as HPET.
* Update several places that iterate over CPUs to use CPU_FOREACH().jhb2010-06-111-4/+2
|
* Do not disable edge-triggered interrupts before migration. DELAY() withmav2010-06-101-1/+1
| | | | interrupt disabled highly probable causes interrupt loss.
* Move the MD support for PCI message signalled interrupts to the x86 treejhb2010-06-081-0/+602
| | | | as it is identical for i386 and amd64.
* Move the machine check support code to the x86 tree since it is identicaljhb2010-06-081-0/+889
| | | | | | on i386 and amd64. Requested by: alc
* Move the I/O APIC code to the x86 tree since it is identical on i386 andjhb2010-06-081-0/+922
| | | | amd64.
* Add support for corrected machine check interrupts. CMCI is a new localjhb2010-05-241-1/+39
| | | | | | | | | | | | | | | | APIC interrupt that fires when a threshold of corrected machine check events is reached. CMCI also includes a count of events when reporting corrected errors in the bank's status register. Note that individual banks may or may not support CMCI. If they do, each bank includes its own threshold register that determines when the interrupt fires. Currently the code uses a very simple strategy where it doubles the threshold on each interrupt until it succeeds in throttling the interrupt to occur only once a minute (this interval can be tuned via sysctl). The threshold is also adjusted on each hourly poll which will lower the threshold once events stop occurring. Tested by: Sailaja Bangaru sbappana at yahoo com MFC after: 1 month
* - Implement MI helper functions, dividing one or two timer interrupts withmav2010-05-242-83/+16
| | | | | | | | arbitrary frequencies into hardclock(), statclock() and profclock() calls. Same code with minor variations duplicated several times over the tree for different timer drivers and architectures. - Switch all x86 archs to new functions, simplifying the code and removing extra logic from timer drivers. Other archs are also welcome.
* Restore different APIC init orders for i386 and amd64 unified in r208452.mav2010-05-241-2/+24
| | | | | | Seems noone of them contents both arch for different reasons. Submitted by: kib@
* Unify local_apic.c for x86 archs,mav2010-05-231-0/+1437
|
* Fix another instance of lapic_cyclic_clock_func.rpaulo2010-04-201-2/+2
|
* Default the machdep.lapic_allclocks to be enabled in order to cope withattilio2010-04-091-1/+1
| | | | | | | | | | broken atrtc. Now if you want more correct stats on profhz and stathz it may be disabled by setting to 0. Reported by: A. Akephalos <akephalos dot akephalos at gmail dot com>, Jakub Lach <jakub_lach at mailplus dot pl> MFC: 1 week
* Improving the clocks auto-tunning by firstly checking if the atrtc may beattilio2010-03-031-5/+20
| | | | | | | | | | | | | | | | | | | correctly initialized and just then assign to softclock/profclock. Right now, some atrtc seems reporting strange diagnostic error* making the current pattern bogus. In order to do that cleanly, lapic_setup_clock(), on both ia32 and amd64, now accepts as arguments the desired sources to handle, and returns the actual ones (LAPIC_CLOCK_NONE is forbidden because otherwise there is no meaning in calling such function). This allows to bring out into commont x86 code the handling part for machdep.lapic_allclocks tunable, which is retained. Sponsored by: Sandvine Incorporated Tested by: yongari, Richard Todd <rmtodd at ichotolot dot servalan dot com> MFC: 3 weeks X-MFC: r202387, 204309
* Introduce the new kernel sub-tree x86 which should contain all the codeattilio2010-02-2517-0/+7491
shared and generalized between our current amd64, i386 and pc98. This is just an initial step that should lead to a more complete effort. For the moment, a very simple porting of cpufreq modules, BIOS calls and the whole MD specific ISA bus part is added to the sub-tree but ideally a lot of code might be added and more shared support should grow. Sponsored by: Sandvine Incorporated Reviewed by: emaste, kib, jhb, imp Discussed on: arch MFC: 3 weeks
OpenPOWER on IntegriCloud