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* Fix multiple OpenSSL vulnerabilitites. [SA-16:17]delphij2016-05-041-13/+47
| | | | | | | | | | Fix performance regression in libc hash(3). [EN-16:06] Fix excessive latency in x86 IPI delivery. [EN-16:07] Fix memory leak in ZFS. [EN-16:08] Approved by: so
* MFC [Hyper-V]: r293719-r293722, r293869-r293871, r293873-r293875, r293877sephe2016-02-191-0/+2
| | | | | | | | | | | | | | | | | r293719 hyperv/hn: Implement LRO r293720 hyperv/hn: Implement SIOC[SG]IFMEDIA support r293721 hyperv/hn: Avoid mbuf cluster allocation, if the packet is small. r293722 hyperv/hn: Removed unused netvsc_init() r293869 hyperv/hn: Unbreak LINT-NOIP r293870 hyperv: use x86 generic code to do the hypervisor detection r293871 hyperv: remove unused vmbus definitions r293873 hyperv: implement an event timer r293874 hyperv: add interrupt counters r293875 hyperv: set receive buffer size according to NVSP protocol version r293877 Unbreak `make depend` with sys/modules/hyperv/vmbus after r293870 Approved by: re (glebius), adrian (mentor) Sponsored by: Microsoft OSTC
* MFC r289618, r290316:ian2016-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix printf format to allow for bus_size_t not being u_long on all platforms. Fix an alignment check that is wrong in half the busdma implementations. This will enable the elimination of a workaround in the USB driver that artifically allocates buffers twice as big as they need to be (which actually saves memory for very small buffers on the buggy platforms). When deciding how to allocate a dma buffer, armv4, armv6, mips, and x86/iommu all correctly check for the tag alignment <= maxsize as enabling simple uma/malloc based allocation. Powerpc, sparc64, x86/bounce, and arm64/bounce were all checking for alignment < maxsize; on those platforms when alignment was equal to the max size it would fall back to page-based allocators even for very small buffers. This change makes all platforms use the <= check. It should be noted that on all platforms other than arm[v6] and mips, this check is relying on undocumented behavior in malloc(9) that if you allocate a block of a given size it will be aligned to the next larger power-of-2 boundary. There is nothing in the malloc(9) man page that makes that explicit promise (but the busdma code has been relying on this behavior all along so I guess it works). Arm and mips code uses the allocator in kern/subr_busdma_buffalloc.c, which does explicitly implement this promise about size and alignment. Other platforms probably should switch to the aligned allocator.
* MFC r293343: Move amd64 metadata.h to x86 and share with i386emaste2016-01-181-0/+57
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* MFC r292890:kib2016-01-052-0/+3
| | | | Add standard extended feature bit 6 from the Intel SDM rev. 57.
* MFC: r286785, r291088, r291120marius2015-12-271-36/+37
| | | | | | | | | | | | | | | | - Reformat x86 bounce buffer synchronization code to reduce indentation. No functional change. - Avoid a NULL pointer dereference in bounce_bus_dmamap_sync() when the map has been created via bounce_bus_dmamem_alloc(). Even for coherent DMA - which bus_dmamem_alloc(9) typically is used for -, calling of bus_dmamap_sync(9) isn't optional. [1] - Avoid a NULL pointer dereference in bounce_bus_dmamap_unload() when the map has been created via bounce_bus_dmamem_alloc(). In that case bus_dmamap_unload(9) typically isn't called during normal operation but still should be during detach, cleanup from failed attach etc. [2] PR: 188899 (non-original problem) [1] Submitted by: yongari [2]
* MFC r291024:royger2015-12-031-20/+1
| | | | | | xen: fix dropping bitmap IPIs during resume Sponsored by: Citrix Systems R&D
* Revert MFC of r291023:royger2015-12-021-3/+0
| | | | | Due to the delta between HEAD and stable/10 event channel code, this fix is not needed on stable/10 and was also causing build issues. Revert it.
* MFC r291023:royger2015-12-021-0/+3
| | | | | | xen/intr: properly dispose event channels on resume Sponsored by: Citrix Systems R&D
* MFC r291022:royger2015-12-021-3/+12
| | | | | | x86/intr: allow mutex recursion in intr_remove_handler Sponsored by: Citrix Systems R&D
* MFC r291266:kib2015-11-271-1/+1
| | | | | Correct the number of DTLB entries reported for the CPUID Leaf 2 descriptor 0x6c.
* MFC r286999:royger2015-11-241-4/+23
| | | | | | xen: allow disabling PV disks and nics Sponsored by: Citrix Systems R&D
* MFC r289823:kib2015-10-301-0/+12
| | | | | Decode new values for CPUID leaf 2 cache and TLB descriptors, from the Intel SDM revision 56.
* MFC 284175:jhb2015-10-011-32/+65
| | | | | | | | | | | Handle X2APIC entries in the MADT for APICs with an ID < 255. At least one BIOS has been seen to include such entries even though the relevant specs require that X2APIC entries only be used for CPUs with an APIC ID >= 255. This was tested on a system with "plain" local APIC entries in the MADT to ensure no regressions, but it has not yet been tested on a system with X2APIC entries in the MADT. Currently such systems do not boot at all, and with this change they might now boot correctly.
* MFC r276834sbruno2015-09-042-1/+2
| | | | | | | | | | | | | Update Features2 to display SDBG capability of processor. This is showing up on Haswell-class CPUs From the Intel SDM, "Table 3-20. Feature Information Returned in the ECX Register" 11 | SDBG | A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug. Submitted by: jiashiun@gmail.com
* MFC: r286265, r286293, r286328jkim2015-08-251-2/+10
| | | | Always define __va_list for amd64 and restore pre-r232261 behavior for i386.
* MFC r286667 & r286723marcel2015-08-252-21/+63
| | | | | | | Better support memory mapped console devices, such as VGA and EFI frame buffers and memory mapped UARTs. PR: 191564, 194952, 202276
* MFC r286777:kib2015-08-171-2/+3
| | | | Comment only change, fix grammar and somewhat clarify the action.
* MFC r286228:kib2015-08-171-16/+30
| | | | Clear the IA32_MISC_ENABLE MSR bit on APs.
* Implement x86 ptrace(2) requests PT_{GET,SET}{FS,GS}BASE.kib2015-08-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | MFC r284918: Add helper fill_based_sd(9). MFC r284919: Add x86 PT_GETFSBASE, PT_GETGSBASE machine-depended ptrace requests to obtain the thread %fs and %gs bases. Add x86 PT_SETFSBASE and PT_SETGSBASE requests to set the bases from debuggers. The set requests, similarly to the sysarch({I386,AMD64}_SET_FSBASE), override the corresponding segment registers. MFC r284965: Document x86 machine-specific ptrace(2) requests. MFC r285011: Disallow a debugger on 64bit system to set fs/gs bases of the 32bit process beyond the end of the process address space. MFC r285104: Grammar and language fixes.
* MFC r285932:kib2015-08-041-0/+11
| | | | Add bit names for the IA32_MISC_ENABLE msr.
* MFC: r284931brueffer2015-07-131-1/+1
| | | | | | | | | | | | | Set the initial system time to a sane (as in: not end of 21st century) value when booting on a PC with CMOS clock set to a year before 2000. This uses 1980 (instead of 1970 as in the initial patch) as pivot year as suggested by imp in the PR followup. PR: 195703 Submitted by: cs@soi.spb.ru Reviewed by: imp Approved by: re (gjb)
* MFC: r281751marius2015-07-051-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Refine the workaround for Intel HSD131 [1] added in r269052 (MFCed to stable/10 in r269592): - Use the full mask described by the erratum as with a sufficiently high number of these false-positives, the overflow bit (bit 62) additionally gets set [7]. - HSD131 has been brought into several other Haswell-derived CPUs including to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of these benign errors by default on CPU models affected by HSM142, HSW131 and BDM48 [2 - 5], describing the HSD131 silicon bug for additional models. Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered by this fault [6], with the specification update concerned with HSM142 [2] only referring to 0x3c and 0x46. Submitted by: David Froehlich [7] Approved by: re (kib) http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf [1] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf [2] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf [3] http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf [4] http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf [5] https://lists.freebsd.org/pipermail/freebsd-hackers/2015-January/046878.html [6]
* MFC r282209:neel2015-06-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emulate the 'bit test' instruction. MFC r282259: Re-implement RTC current time calculation to eliminate the possibility of losing time. MFC r282281: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs. MFC r282284: When an instruction cannot be decoded just return to userspace so bhyve(8) can dump the instruction bytes. MFC r282287: Don't require <sys/cpuset.h> to be always included before <machine/vmm.h>. MFC r282296: Emulate MSR_SYSCFG which is accessed by Linux on AMD cpus when MTRRs are enabled. MFC r282301: Relax limits when transitioning a vector from the IRR to the ISR and also when extinguishing it from the ISR in response to an EOI. MFC r282335: Advertise an additional memory BAR in the "dummy" device emulation. MFC r282336: Emulate machine check related MSRs to allow guest OSes like Windows to boot. MFC r282351: Don't advertise the Intel SMX capability to the guest. MFC r282407: Emulate the 'CMP r/m8, imm8' instruction. MFC r282519: Add macros for AMD-specific bits in MSR_EFER: LMSLE, FFXSR and TCE. MFC r282520: Emulate guest writes to EFER_MSR properly. MFC r282558: Deprecate the 3-way return values from vm_gla2gpa() and vm_copy_setup(). MFC r282571: Check 'td_owepreempt' and yield the vcpu thread if it is set. MFC r282595: Allow byte reads of AHCI registers. MFC r282784: Handling indirect descriptors is a capability of the host and not one that needs to be negotiated. Use the host capabilities field and not the negotiated field when verifying that indirect descriptors are supported. MFC r282788: Allow configuration of the sector size advertised to the guest. MFC r282865: Set the subvendor field in config space to the vendor ID. This is required by the Windows virtio drivers to correctly match a device. MFC r282922: Bump the size of the blockif scatter-gather list to 67. MFC r283075: Fix off-by-one in array index bounds check. bhyveload would allow you to create 33 entries on an array that only has 32 slots MFC r283168: Temporarily revert r282922 which bumped the max descriptors. MFC r283255: Emulate the "CMP r/m, reg" instruction (opcode 39H). MFC r283256: Add an option "--get-vmcs-exit-inst-length" to display the instruction length of the instruction that caused the VM-exit. MFC r283264: Change the header type of the emulated host-bridge from type 1 to type 0. MFC r283293: Don't rely on the 'VM-exit instruction length' field in the VMCS to always have an accurate length on an EPT violation. MFC r283299: Remove bogus verification of instruction length after instruction decode. MFC r283308: Exceptions don't deliver an error code in real mode. MFC r283657: Fix non-deterministic delays when accessing a vcpu that was in "running" or "sleeping" state. MFC r283973: Use tunable 'hw.vmm.svm.features' to disable specific SVM features even though they might be available in hardware. Use tunable 'hw.vmm.svm.num_asids' to limit the number of ASIDs used by the hypervisor. MFC r284046: Fix regression in 'verify_gla()' with the RIP-relative addressing mode. MFC r284174: Support guest writes to the TSC by enabling the "use TSC offsetting" execution control.
* MFC r284104:kib2015-06-131-3/+180
| | | | Updates from SDM rev. 55.
* MFC r283735:kib2015-06-052-9/+3
| | | | Remove several write-only variables.
* MFC r283692:kib2015-06-051-0/+2
| | | | Explicitely enable queued invalidation completion interrupt.
* MFC 281887:jhb2015-06-024-4/+4
| | | | | Reassign copyright statements on several files from Advanced Computing Technologies LLC to Hudson River Trading LLC.
* MFC 281266:jhb2015-06-021-0/+1
| | | | | | | | | | | | Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h> and export them to userland. - Define __HAVE_REG32 on platforms that define a reg32 structure and check for this in <sys/procfs.h> to control when to export prstatus32, etc. - Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures. libbfd looks for these types, and having them fixes 'gcore' in gdb of a 32-bit process on a 64-bit platform. - Use the structure definitions from <sys/procfs.h> in gcore's elf32 core dump code instead of duplicating the definitions.
* MFC r282120:hselasky2015-05-051-2/+2
| | | | | | | | | | | | The add_bounce_page() function can be called when loading physical pages which pass a NULL virtual address. If the BUS_DMA_KEEP_PG_OFFSET flag is set, use the physical address to compute the page offset instead. The physical address should always be valid when adding bounce pages and should contain the same page offset like the virtual address. Submitted by: Svatopluk Kraus <onwahe@gmail.com> Reviewed by: jhb@
* MFC r281495:kib2015-04-271-1/+1
| | | | | | | | | | | | Add config option PAE_TABLES for the i386 kernel. It switches pmap to use PAE format for the page tables, but does not incur other consequences of the full PAE config. In particular, vm_paddr_t and bus_addr_t are left 32bit, and max supported memory is still limited by 4GB. The option allows to have nx permissions for memory mappings on i386 kernel, while keeping the usual i386 KBI and avoiding the kernel data sizing problems typical for the PAE config.
* MFC: r281396, r281475jkim2015-04-181-1/+1
| | | | | | Merge ACPICA 20150410. Relnotes: yes
* MFC 278325,280866:jhb2015-04-151-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Revert the IPI startup sequence to match what is described in the Intel Multiprocessor Specification v1.4. The Intel SDM claims that 278325: Revert the IPI startup sequence to match what is described in the Intel Multiprocessor Specification v1.4. The Intel SDM claims that the INIT IPIs here are invalid, but other systems follow the MP spec instead. While here, fix the IPI wait routine to accept a timeout in microseconds instead of a raw spin count, and don't spin forever during AP startup. Instead, panic if a STARTUP IPI is not delivered after 20 us. 280866: Wait 100 microseconds for a local APIC to dispatch each startup-related IPI rather than 20. The MP 1.4 specification states in Appendix B.2: "A period of 20 microseconds should be sufficient for IPI dispatch to complete under normal operating conditions". (Note that this appears to be separate from the 10 millisecond (INIT) and 200 microsecond (STARTUP) waits after the IPIs are dispatched.) The Intel SDM is silent on this issue as far as I can tell. At least some hardware requires 60 microseconds as noted in the PR, so bump this to 100 to be on the safe side. PR: 196542, 197756
* MFC r281254:kib2015-04-153-21/+32
| | | | | Account for the offset of the page run when allocating the dmar_map_entry.
* MFC 276724:jhb2015-04-021-6/+6
| | | | | | | | | | On some Intel CPUs with a P-state but not C-state invariant TSC the TSC may also halt in C2 and not just C3 (it seems that in some cases the BIOS advertises its C3 state as a C2 state in _CST). Just play it safe and disable both C2 and C3 states if a user forces the use of the TSC as the timecounter on such CPUs. PR: 192316
* MFC 261790:jhb2015-04-014-3/+72
| | | | | | | | | | | | | | | | | | | | | | Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. PR: 197076
* MFC 260973:jhb2015-04-014-67/+14
| | | | | | - Reuse legacy_pcib_(read|write)_config() methods in the QPI pcib driver. - Reuse legacy_pcib_alloc_msi{,x}() methods in the QPI and mptable pcib drivers.
* MFC r280435:kib2015-03-311-1/+1
| | | | | | When mapping an allocated entry, use the entry size, instead of the requested size. If tag restrictions caused split entry, its size is less then requsted.
* MFC r280434:kib2015-03-311-0/+1
| | | | Assert that the mapping loop makes progress.
* MFC r280254:kib2015-03-261-6/+21
| | | | | Provide definitions for all descriptors types in the DMAR invalidation queue.
* MFC r280196:kib2015-03-241-2/+4
| | | | | Recheck that boundary is not crossed after the move to satisfy boundary restriction.
* MFC r280195:kib2015-03-241-1/+2
| | | | | | When inserting new entry into the address map, ensure that not only next entry does not intersect with the tail of the new entry, but also that previous entry is also before new entry start.
* MFC r280253:kib2015-03-221-1/+1
| | | | Fix syntax error.
* MFC r271889, 272799, 272800, 274976scottl2015-03-121-8/+28
| | | | | | | | This brings in bus_get_domain() and the related reporting via devinfo, dmesg, and sysctl. Obtained from: adrian, jhb Sponsored by: Netflix, Inc.
* MFC r276949:kib2015-03-011-26/+48
| | | | | | | | (only to ease merging of r279117). MFC r279117: Revert r276949 and redo the fix for PCIe/PCI bridges, which do not follow specification and do not provide PCIe capability.
* MFC r276948:kib2015-03-012-4/+5
| | | | | Print rid when announcing DMAR context creation. Print sid when fault occurs.
* MFC r276867:kib2015-03-011-1/+1
| | | | | | | Fix DMAR context allocations for the devices behind PCIe->PCI bridges after dmar driver was converted to use rids. The bus component to calculate context page must be taken from the requestor rid, which is a bridge, and not from the device bus number.
* MFC r264007,r264008,r264009,r264011,r264012,r264013rstone2015-03-016-47/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MFC support for PCI Alternate RID Interpretation. ARI is an optional PCIe feature that allows PCI devices to present up to 256 functions on a bus. This is effectively a prerequisite for PCI SR-IOV support. r264007: Add a method to get the PCI RID for a device. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc. r264008: Re-implement the DMAR I/O MMU code in terms of PCI RIDs Under the hood the VT-d spec is really implemented in terms of PCI RIDs instead of bus/slot/function, even though the spec makes pains to convert back to bus/slot/function in examples. However working with bus/slot/function is not correct when PCI ARI is in use, so convert to using RIDs in most cases. bus/slot/function will only be used when reporting errors to a user. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc. r264009: Re-write bhyve's I/O MMU handling in terms of PCI RID. Reviewed by: neel MFC after: 2 months Sponsored by: Sandvine Inc. r264011: Add support for PCIe ARI PCIe Alternate RID Interpretation (ARI) is an optional feature that allows devices to have up to 256 different functions. It is implemented by always setting the PCI slot number to 0 and re-purposing the 5 bits used to encode the slot number to instead contain the function number. Combined with the original 3 bits allocated for the function number, this allows for 256 functions. This is enabled by default, but it's expected to be a no-op on currently supported hardware. It's a prerequisite for supporting PCI SR-IOV, and I want the ARI support to go in early to help shake out any bugs in it. ARI can be disabled by setting the tunable hw.pci.enable_ari=0. Reviewed by: kib MFC after: 2 months Sponsored by: Sandvine Inc. r264012: Print status of ARI capability in pciconf -c Teach pciconf how to print out the status (enabled/disabled) of the ARI capability on PCI Root Complexes and Downstream Ports. MFC after: 2 months Sponsored by: Sandvine Inc. r264013: Add missing copyright date. MFC after: 2 months
* MFC 274817,274878,276801,276840,278976:jhb2015-02-232-12/+22
| | | | | | | | | | | | | | | | Improve support for XSAVE with debuggers. - Dump an NT_X86_XSTATE note if XSAVE is in use. This note is designed to match what Linux does in that 1) it dumps the entire XSAVE area including the fxsave state, and 2) it stashes a copy of the current xsave mask in the unused padding between the fxsave state and the xstate header at the same location used by Linux. - Teach readelf() to recognize NT_X86_XSTATE notes. - Change PT_GET/SETXSTATE to take the entire XSAVE state instead of only the extra portion. This avoids having to always make two ptrace() calls to get or set the full XSAVE state. - Add a PT_GET_XSTATE_INFO which returns the length of the current XSTATE save area (so the size of the buffer needed for PT_GETXSTATE) and the current XSAVE mask (%xcr0).
* MFC r278606:kib2015-02-182-4/+67
| | | | Registers definitions for the new capabilities.
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