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* MFC r278606:kib2015-02-182-4/+67
| | | | Registers definitions for the new capabilities.
* MFC r278605:kib2015-02-181-4/+2
| | | | vm_page_lookup() accepts read-locked object.
* MFC 273800:jhb2015-02-103-74/+174
| | | | | | | | | | | | | Rework virtual machine hypervisor detection. - Move the existing code to x86/x86/identcpu.c since it is x86-specific. - If the CPUID2_HV flag is set, assume a hypervisor is present and query the 0x40000000 leaf to determine the hypervisor vendor ID. Export the vendor ID and the highest supported hypervisor CPUID leaf via hv_vendor[] and hv_high variables, respectively. The hv_vendor[] array is also exported via the hw.hv_vendor sysctl. - Merge the VMWare detection code from tsc.c into the new probe in identcpu.c. Add a VM_GUEST_VMWARE to identify vmware and use that in the TSC code to identify VMWare.
* MFC 272666: Fix build for i386 kernels with out 'I686_CPU'.jhb2015-01-211-1/+1
| | | | Reported by: Mike Tancsa <mike@sentex.net>
* MFC r277047:kib2015-01-191-0/+3
| | | | For x86, read MAXPHYADDR into variable cpu_maxphyaddr.
* MFC r277023:kib2015-01-184-21/+54
| | | | | Avoid excessive flushing and do missed neccessary flushing in the IOMMU page table update code.
* MFC r273748neel2014-12-311-0/+65
| | | | | | | | Output a summary of optional SVM features in dmesg similar to CPU features. If bootverbose is enabled, a detailed list is provided; otherwise, a single-line summary is displayed. Requested by: jhb
* MFC 261321neel2014-12-301-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | Rename the AMD MSR_PERFCTR[0-3] so the Pentium Pro MSR_PERFCTR[0-1] aren't redefined. MFC r273214 Fix build to not bogusly always rebuild vmm.ko. MFC r273338 Add support for AMD's nested page tables in pmap.c: - Provide the correct bit mask for various bit fields in a PTE (e.g. valid bit) for a pmap of type PT_RVI. - Add a function 'pmap_type_guest(pmap)' that returns TRUE if the pmap is of type PT_EPT or PT_RVI. Add CPU_SET_ATOMIC_ACQ(num, cpuset): This is used when activating a vcpu in the nested pmap. Using the 'acquire' variant guarantees that the load of the 'pm_eptgen' will happen only after the vcpu is activated in 'pm_active'. Add defines for various AMD-specific MSRs. Discussed with: kib (r261321)
* MFC r270326neel2014-12-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a recursive lock acquisition in vi_reset_dev(). MFC r270434 Return the spurious interrupt vector (IRQ7 or IRQ15) if the atpic cannot find any unmasked pin with an interrupt asserted. MFC r270436 Fix a bug in the emulation of CPUID leaf 0x4. MFC r270437 Add "hw.vmm.topology.threads_per_core" and "hw.vmm.topology.cores_per_package" tunables to modify the default cpu topology advertised by bhyve. MFC r270855 Set the 'inst_length' to '0' early on before any error conditions are detected in the emulation of the task switch. If any exceptions are triggered then the guest %rip should point to instruction that caused the task switch as opposed to the one after it. MFC r270857 The "SUB" instruction used in getcc() actually does 'x -= y' so use the proper constraint for 'x'. The "+r" constraint indicates that 'x' is an input and output register operand. While here generate code for different variants of getcc() using a macro GETCC(sz) where 'sz' indicates the operand size. Update the status bits in %rflags when emulating AND and OR opcodes. MFC r271439 Initialize 'bc_rdonly' to the right value. MFC r271451 Optimize the common case of injecting an interrupt into a vcpu after a HLT by explicitly moving it out of the interrupt shadow. MFC r271888 Restructure the MSR handling so it is entirely handled by processor-specific code. MFC r271890 MSR_KGSBASE is no longer saved and restored from the guest MSR save area. This behavior was changed in r271888 so update the comment block to reflect this. MFC r271891 Add some more KTR events to help debugging. MFC r272197 mmap(2) requires either MAP_PRIVATE or MAP_SHARED for non-anonymous mappings. MFC r272395 Get rid of code that dealt with the hardware not being able to save/restore the PAT MSR on guest exit/entry. This workaround was done for a beta release of VMware Fusion 5 but is no longer needed in later versions. All Intel CPUs since Nehalem have supported saving and restoring MSR_PAT in the VM exit and entry controls. MFC r272670 Inject #UD into the guest when it executes either 'MONITOR' or 'MWAIT'. MFC r272710 Implement the FLUSH operation in the virtio-block emulation. MFC r272838 iasl(8) expects integer fields in data tables to be specified as hexadecimal values. Therefore the bit width of the "PM Timer Block" was actually being interpreted as 50-bits instead of the expected 32-bit. This eliminates an error message emitted by a Linux 3.17 guest during boot: "Invalid length for FADT/PmTimerBlock: 50, using default 32" MFC r272839 Support Intel-specific MSRs that are accessed when booting up a linux in bhyve: - MSR_PLATFORM_INFO - MSR_TURBO_RATIO_LIMITx - MSR_RAPL_POWER_UNIT MFC r273108 Emulate "POP r/m". This is needed to boot OpenBSD/i386 MP kernel in bhyve. MFC r273212 Support stopping and restarting the AHCI command list via toggling PxCMD.ST from '1' to '0' and back. This allows the driver a chance to recover if for instance a timeout occurred due to activity on the host.
* MFC r271208:kib2014-12-231-0/+2
| | | | Add a define for index of IA32_XSS MSR.
* MFC r271206:kib2014-12-231-1/+3
| | | | Adjust the definition of struct xstate_hdr according to SDM rev. 50.
* MFC r271197:kib2014-12-232-0/+16
| | | | | Add more bits for the XSAVE features from CPUID 0xd, sub-function 1 %eax report. Print the XSAVE features 0xd/1 in the boot banner.
* MFC 273988,273989,273995,274057:jhb2014-12-221-4/+2
| | | | | MFamd64: Add support for extended FPU states on i386. This includes support for AVX on i386.
* MFC 271405,271408,271409,272658:jhb2014-12-222-29/+1
| | | | | | MFamd64: Use initializecpu() to set various model-specific registers on AP startup and AP resume (it was already used for BSP startup and BSP resume).
* MFC 260557,271076,271077,271082,271083,271098:jhb2014-12-222-0/+2022
| | | | | | | | | | - Remove spaces from boot messages when we print the CPU ID/Family/Stepping - Move prototypes for various functions into out of C files and into <machine/md_var.h>. - Reduce diffs between i386 and amd64 initcpu.c and identcpu.c files. - Move blacklists of broken TSCs out of the printcpuinfo() function and into the TSC probe routine. - Merge the amd64 and i386 identcpu.c into a single x86 implementation.
* MFC r263710, r273377, r273378, r273423 and r273455:hselasky2014-10-271-8/+1
| | | | | | | - De-vnet hash sizes and hash masks. - Fix multiple issues related to arguments passed to SYSCTL macros. Sponsored by: Mellanox Technologies
* MFC 270850,271053,271192,271717:jhb2014-09-221-15/+28
| | | | | | | | | | | | Save and restore FPU state across suspend and resume on i386. - Create a separate structure for per-CPU state saved across suspend and resume that is a superset of a pcb. - Store the FPU state for suspend and resume in the new structure (for amd64, this moves it out of the PCB) - On both i386 and amd64, all of the FPU suspend/resume handling is now done in C. Approved by: re (hrs)
* MFC r263859:akiyama2014-08-311-10/+8
| | | | | | | | | | Change default logic to CONFORM because this routine is shared with SCI polarity setting. Reviewed by: jhb MFC r269184: Add missing newline to output dmesg properly.
* MFC r267921, r267934, r267949, r267959, r267966, r268202, r268276,grehan2014-08-191-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r268427, r268428, r268521, r268638, r268639, r268701, r268777, r268889, r268922, r269008, r269042, r269043, r269080, r269094, r269108, r269109, r269281, r269317, r269700, r269896, r269962, r269989. Catch bhyve up to CURRENT. Lightly tested with FreeBSD i386/amd64, Linux i386/amd64, and OpenBSD/amd64. Still resolving an issue with OpenBSD/i386. Many thanks to jhb@ for all the hard work on the prior MFCs ! r267921 - support the "mov r/m8, imm8" instruction r267934 - document options r267949 - set DMI vers/date to fixed values r267959 - doc: sort cmd flags r267966 - EPT misconf post-mortem info r268202 - use correct flag for event index r268276 - 64-bit virtio capability api r268427 - invalidate guest TLB when cr3 is updated, needed for TSS r268428 - identify vcpu's operating mode r268521 - use correct offset in guest logical-to-linear translation r268638 - chs value r268639 - chs fake values r268701 - instr emul operand/address size override prefix support r268777 - emulation for legacy x86 task switching r268889 - nested exception support r268922 - fix INVARIANTS build r269008 - emulate instructions found in the OpenBSD/i386 5.5 kernel r269042 - fix fault injection r269043 - Reduce VMEXIT_RESTARTs in task_switch.c r269080 - fix issues in PUSH emulation r269094 - simplify return values from the inout handlers r269108 - don't return -1 from the push emulation handler r269109 - avoid permanent sleep in vm_handle_hlt() r269281 - list VT-x features in base kernel dmesg r269317 - Mark AHCI fatal errors as not completed r269700 - Support PCI extended config space in bhyve r269896 - Minor cleanup r269962 - use max guest memory when creating IOMMU domain r269989 - fix interrupt mode names
* MFC: r260457marius2014-08-051-7/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The changes in r233781 attempted to make logging during a machine check exception more readable. In practice they prevented all logging during a machine check exception on at least some systems. Specifically, when an uncorrected ECC error is detected in a DIMM on a Nehalem/Westmere class machine, all CPUs receive a machine check exception, but only CPUs on the same package as the memory controller for the erroring DIMM log an error. The CPUs on the other package would complete the scan of their machine check banks and panic before the first set of CPUs could log an error. The end result was a clearer display during the panic (no interleaved messages), but a crashdump without any useful info about the error that occurred. To handle this case, make all CPUs spin in the machine check handler once they have completed their scan of their machine check banks until at least one machine check error is logged. I tried using a DELAY() instead so that the CPUs would not potentially hang forever, but that was not reliable in testing. While here, don't clear MCIP from MSR_MCG_STATUS before invoking panic. Only clear it if the machine check handler does not panic and returns to the interrupted thread. MFC: r263113 Correct type for malloc(). Submitted by: "Conrad Meyer" <conrad.meyer@isilon.com> MFC: r269052, r269239, r269242 Intel desktop Haswell CPUs may report benign corrected parity errors (see HSD131 erratum in [1]) at a considerable rate. So filter these (default), unless logging is enabled. Unfortunately, there really is no better way to reasonably implement suppressing these errors than to just skipping them in mca_log(). Given that they are reported for bank 0, they'd need to be masked in MSR_MC0_CTL. However, P6 family processors require that register to be set to either all 0s or all 1s, disabling way more than the one error in question when using all 0s there. Alternatively, it could be masked for the corresponding CMCI, but that still wouldn't keep the periodic scanner from detecting these spurious errors. Apart from that, register contents of MSR_MC0_CTL{,2} don't seem to be publicly documented, neither in the Intel Architectures Developer's Manual nor in the Haswell datasheets. Note that while HSD131 actually is only about C0-stepping as of revision 014 of the Intel desktop 4th generation processor family specification update, these corrected errors also have been observed with D0-stepping aka "Haswell Refresh". 1: http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf Reviewed by: jhb Sponsored by: Bally Wulff Games & Entertainment GmbH
* Merge r266746, 266775:scottl2014-07-011-30/+35
| | | | | | | | | | | | | Now that there are separate back-end implementations of busdma, the bounce implementation shouldn't steal flags from the common front-end. Move those flags to the back-end. Eliminate the fake contig_dmamap and replace it with a new flag, BUS_DMA_KMEM_ALLOC. They serve the same purpose, but using the flag means that the map can be NULL again, which in turn enables significant optimizations for the common case of no bouncing. Obtained from: Netflix, Inc.
* MFC r263795:rodrigc2014-06-231-4/+8
| | | | | | | | | | | | | Strict value checking will cause problem. Bay trail DN2820FYKH is supported on Linux but does not work on FreeBSD. This behaviour is bug-compatible with Linux-3.13.5. References: http://d.hatena.ne.jp/syuu1228/20140326 http://lxr.linux.no/linux+v3.13.5/arch/x86/kernel/acpi/boot.c#L1094 Submitted by: syuu PR: 187966
* Undo bad merge.rodrigc2014-06-231-8/+4
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* MFC r263795:rodrigc2014-06-231-4/+8
| | | | | | | | | | | | | Strict value checking will cause problem. Bay trail DN2820FYKH is supported on Linux but does not work on FreeBSD. This behaviour is bug-compatible with Linux-3.13.5. References: http://d.hatena.ne.jp/syuu1228/20140326 http://lxr.linux.no/linux+v3.13.5/arch/x86/kernel/acpi/boot.c#L1094 Submitted by: syuu PR: 187966
* MFC 266263,266551,266552:jhb2014-06-121-6/+25
| | | | | | - Add definitions for more structured extended features as well as XSAVE Extended Features for AVX512 and MPX (Memory Protection Extensions). - Don't permit users to request a subset of the AVX512 or MPX xsave masks.
* MFC 263772: Fix build without SMP.jhb2014-06-041-1/+5
| | | | PR: 187854
* MFC r257738, r259202, r258410, r260288, r260292, r260294, r260320, r260323,ian2014-05-142-18/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r260326, r260327, r260331, r260333, r260340, r260371, r260372, r260373, r260374, r260375 Add common bus_space tag definition shared for most supported ARMv6/v7 SoCs. Correct license statements to reflect the fact that these files were all derived from sys/arm/mv/bus_space.c. In pmap_unmapdev(), remember the size, and use that as an argument to kva_free(), or we'd end up always passing it a size of 0 In pmap_mapdev(), first check whether a static mapping exists, Convert TI static device mapping to use the new arm_devmap_add_entry(), Use the common armv6 fdt_bus_tag defintion for tegra instead of a local copy. Eliminate use of fdt_immr_addr(), it's not needed for tegra Convert lpc from using fdt_immr style to arm_devmap_add_entry() to make static device mappings. Retire machine/fdt.h as a header used by MI code, as its function is now obsolete. This involves the following pieces: - Remove it entirely on PowerPC, where it is not used by MD code either - Remove all references to machine/fdt.h in non-architecture-specific code (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat non-arch-specific). - Fix code relying on header pollution from machine/fdt.h includes - Legacy fdtbus.c (still used on x86 FDT systems) now passes resource requests to its parent (nexus). This allows x86 FDT devices to allocate both memory and IO requests and removes the last notionally MI use of fdtbus_bs_tag. - On those architectures that retain a machine/fdt.h, unused bits like FDT_MAP_IRQ and FDT_INTR_MAX have been removed. Add #include <machine/fdt.h> to a few files that used to get it via pollution Enable the mv cesa security/crypto device by providing the required property in the dts source, and adding the right devices to the kernel config. Remove dev/fdt/fdt_pci.c, which was code specific to Marvell ARM SoCs, related to setting up static device mappings. Since it was only used by arm/mv/mv_pci.c, it's now just static functions within that file, plus one public function that gets called only from arm/mv/mv_machdep.c. Switch RPi to using arm_devmap_add_entry() to set up static device mapping. Allow 'no static device mappings' to potentially work. Don't try to find a static mapping before calling pmap_mapdev(), that logic is now part of pmap_mapdev() and doesn't need to be duplicated here. Switch a10 to using arm_devmap_add_entry() to set up static device mapping.
* MFC r263998:tijl2014-04-151-1/+1
| | | | | Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4 -fms-extensions.
* MFC r263001royger2014-04-041-183/+10
| | | | | | | | Move asm IPIs handlers to C code, so both Xen and native IPI handlers share the same code. Approved by: gibbs Sponsored by: Citrix Systems R&D
* MFC r263306:kib2014-03-253-17/+122
| | | | Add some support for the PCI(e)-PCI bridges to the Intel VT-d driver.
* MFC r263305:kib2014-03-251-0/+9
| | | | | Provide a workaround by identity mapping the 32 pages after the bogus entry start, which seems to be enough for the reported BIOS.
* MFC r263289: Update NetBSD Foundation copyrights to 2-clause BSDemaste2014-03-241-7/+0
| | | | | | | | | | | The NetBSD Foundation states "Third parties are encouraged to change the license on any files which have a 4-clause license contributed to the NetBSD Foundation to a 2-clause license." This change removes clauses 3 and 4 from copyright / license blocks that list The NetBSD Foundation as the only copyright holder. Sponsored by: The FreeBSD Foundation
* MFC r263304:kib2014-03-211-2/+2
| | | | Trim at EOL.
* MFC: r262746, r262748, r262750, r262752jkim2014-03-101-1/+1
| | | | Move fpusave() wrapper for suspend hander to sys/amd64/amd64/fpu.c.
* MFC 261517,261520:jhb2014-02-186-18/+0
| | | | | Convert the license on files where I am the sole copyright holder to 2 clause BSD licenses.
* MFC 259140:jhb2014-02-184-31/+42
| | | | | Move constants for indices in the local APIC's local vector table from apicvar.h to apicreg.h.
* MFC r257417: Remove references to an unused fasttrap probe hookavg2014-02-171-1/+0
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* MFC r258779,r258780,r258787,r258822:eadler2014-02-041-8/+8
| | | | | | | | | | | | | Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this shifts into the sign bit. Instead use (1U << 31) which gets the expected result. Similar to the (1 << 31) case it is not defined to do (2 << 30). This fix is not ideal as it assumes a 32 bit int, but does fix the issue for most cases. A similar change was made in OpenBSD.
* MFC 259823:jhb2014-01-311-0/+1
| | | | Fix i386 build.
* MFC 259782:jhb2014-01-291-0/+5
| | | | | | Add a resume hook for bhyve that runs a function on all CPUs during resume. For Intel CPUs, invoke vmxon for CPUs that were in VMX mode at the time of suspend.
* MFC r259197:mav2014-01-091-3/+2
| | | | | | | | | Do not DELAY() for P-state transition unless we want to see the result. Intel manual says: "If a transition is already in progress, transition to a new value will subsequently take effect. Reads of IA32_PERF_CTL determine the last targeted operating point." So seems it should be fine to just trigger wanted transition and go. Linux does the same.
* MFC 259013:jhb2013-12-241-4/+4
| | | | | | Fix the processor table entry structure to use a fixed-width type for 32-bit fields so it is the correct size on amd64. Remove a workaround for the broken structure from bhyve(8).
* MFC DMAR busdma implementation.kib2013-12-1713-1/+6389
| | | | | | | | | | | | | | | | | | | | | | MFC r257251: Import the driver for VT-d DMAR hardware. Implement the busdma(9) using DMARs. MFC r257512: Add support for queued invalidation. MFC miscellaneous follow-ups to r257251. MFC r257266: Remove redundand assignment to error variable and check for its value. MFC r257308: Remove redundand declaration. MFC r257511: Return BUS_PROBE_NOWILDCARD from the DMAR probe method. MFC r257860,r257896,r257900,r257902,r257903 (by dim): Fixes for gcc compilation.
* MFC r257230:kib2013-12-173-998/+1330
| | | | | Add a virtual table for the busdma methods on x86, to allow different busdma implementations to coexist.
* MFC r257228:kib2013-12-171-0/+10
| | | | | Add bus_dmamap_load_ma() function to load map with the array of vm_pages.
* MFC r257769 to stable/10sbruno2013-12-051-2/+7
| | | | | | | | | | | Fix powerd/states on AMD cpus. Resolves issues with system reporting: hwpstate0: set freq failed, err 6 Tested on FX-8150 and others. PR: kern/167018 Submitted by: avg@ Approved by: re (gjb)
* MFC r258135: x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)emaste2013-11-251-1/+9
| | | | | | | | | | | | | | | Debuggers may need to change PSL_RF. Note that tf_eflags is already stored in the signal context during signal handling and PSL_RF previously could be modified via sigreturn, so this change should not provide any new ability to userspace. For background see the thread at: http://lists.freebsd.org/pipermail/freebsd-i386/2007-September/005910.html Reviewed by: jhb, kib Sponsored by: DARPA, AFRL Approved by: re (gjb)
* MFC r257856:kib2013-11-151-0/+6
| | | | | | | Add bits for the AMD features from CPUID function 0x80000001 ECX, described in the rev. 3.0 of the Kabini BKDG, document 48751.pdf. Approved by: re (gjb)
* MFC r257069:kib2013-11-011-0/+96
| | | | | | Add ddb 'show ioapic' and 'show all ioapics' commands. Approved by: re (glebius)
* Add a va_copy() to our fall-back stdarg implementation for use with lint(1)phk2013-10-071-0/+2
| | | | Approved by: re@ (glebius@)
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