| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Use a dedicated taskqueue with a thread that runs at a software-interrupt | jhb | 2011-02-03 | 1 | -3/+7 |
| * | Introduce signed and unsigned version of CTLTYPE_QUAD, renaming | mdf | 2011-01-19 | 1 | -2/+2 |
| * | If an interrupt on an I/O APIC is moved to a different CPU after it has | jhb | 2011-01-13 | 1 | -2/+0 |
| * | Revert to using bus_size_t for the bounce_zone's alignment member. | mdf | 2011-01-13 | 1 | -3/+10 |
| * | Fix a brain fart. Since this file is shared between i386 and amd64, a | mdf | 2011-01-12 | 1 | -3/+3 |
| * | sysctl(9) cleanup checkpoint: amd64 GENERIC builds cleanly. | mdf | 2011-01-12 | 1 | -2/+2 |
| * | Remove unneeded includes of <sys/linker_set.h>. Other headers that use | jhb | 2011-01-11 | 1 | -1/+0 |
| * | Copy powerpc/include/_inttypes.h to x86 and replace i386/amd64/pc98 | tijl | 2011-01-08 | 1 | -0/+221 |
| * | Drop the icu_lock spinlock while pausing briefly after masking the | jhb | 2010-12-23 | 1 | -0/+2 |
| * | Merge amd64 and i386 bus.h and move the resulting header to x86. Replace | tijl | 2010-12-20 | 2 | -12/+1102 |
| * | Small style fixes: | jhb | 2010-12-16 | 1 | -10/+10 |
| * | Remove AMD Family 0Fh, Model 6Bh, Stepping 2 from the list of P-state | jkim | 2010-12-09 | 1 | -1/+1 |
| * | Replace i386/i386/busdma_machdep.c and amd64/amd64/busdma_machdep.c | cperciva | 2010-12-09 | 1 | -0/+1222 |
| * | Merge sys/amd64/amd64/tsc.c and sys/i386/i386/tsc.c and move to sys/x86/x86. | jkim | 2010-12-08 | 1 | -0/+281 |
| * | Merge amd64/i386 _align.h by aligning on the size of register_t (copied | tijl | 2010-11-26 | 1 | -0/+52 |
| * | x86/local_apic: use newly added ARAT bit definition | avg | 2010-11-23 | 1 | -1/+1 |
| * | hwpstate: use CPU_FOREACH when binding to all available processors | avg | 2010-11-16 | 1 | -12/+8 |
| * | Move identical copies of apm_bios.h to sys/x86/include, replace them with | jkim | 2010-11-11 | 1 | -0/+264 |
| * | make it possible to actually enable hwpstate_verbose | avg | 2010-11-11 | 1 | -1/+2 |
| * | Make APM emulation look more closer to its origin. Use device_get_softc(9) | jkim | 2010-11-10 | 1 | -7/+6 |
| * | Refactor acpi_machdep.c for amd64 and i386, move APM emulation into a new | jkim | 2010-11-10 | 1 | -0/+490 |
| * | Move the mptable.h under x86/include/. | attilio | 2010-11-09 | 3 | -2/+148 |
| * | Now OsdEnvironment.c is identical on amd64 and i386. Move it to a new home. | jkim | 2010-11-09 | 1 | -0/+91 |
| * | Move the MADT parser for amd64 and i386 to sys/x86/acpica now that it is | jhb | 2010-11-08 | 1 | -0/+572 |
| * | Sync the APIC startup sequence with amd64: | jhb | 2010-11-08 | 2 | -12/+6 |
| * | Only dump the values of the PMC and CMCI local vector table entries on a | jhb | 2010-11-08 | 1 | -4/+9 |
| * | Cosmetic change to revert one of my earlier ones. | jhb | 2010-11-02 | 1 | -1/+1 |
| * | Further tweaks to the ram_attach() routine: | jhb | 2010-11-02 | 1 | -9/+8 |
| * | Skip SMAP regions above 4GB on i386 since they will not fit into a long. | jhb | 2010-11-02 | 1 | -12/+19 |
| * | Move <machine/apicreg.h> to <x86/apicreg.h>. | jhb | 2010-11-01 | 5 | -4/+449 |
| * | Move the <machine/mca.h> header to <x86/mca.h>. | jhb | 2010-11-01 | 3 | -2/+58 |
| * | - Merge ram_attach() implementation for i386 and amd64 | attilio | 2010-10-29 | 1 | -42/+39 |
| * | Merge nexus.c from amd64 and i386 to x86 subtree. | attilio | 2010-10-28 | 1 | -0/+814 |
| * | Merge the mptable support from MD bits to x86 subtree. | attilio | 2010-10-28 | 2 | -0/+1232 |
| * | Style fix. | attilio | 2010-10-26 | 1 | -2/+2 |
| * | Remove usage of PRI* macro for style compliancy. | attilio | 2010-10-26 | 1 | -4/+3 |
| * | Merge dump_machdep.c i386/amd64 under the x86 subtree. | attilio | 2010-10-26 | 1 | -0/+374 |
| * | Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returned | jhb | 2010-10-25 | 1 | -6/+6 |
| * | atrtc: remove (pre-)historic check of RTC NVRAM at address 0x0e | avg | 2010-10-16 | 1 | -4/+1 |
| * | Restore pre-r212778 optimization, skipping timer reprogramming when it is | mav | 2010-09-18 | 1 | -19/+27 |
| * | Add one-shot mode support to attimer (i8254) event timer. | mav | 2010-09-17 | 1 | -44/+71 |
| * | Few whitespace cleanups and comments tunings. | mav | 2010-09-16 | 1 | -10/+12 |
| * | Refactor timer management code with priority to one-shot operation mode. | mav | 2010-09-13 | 1 | -1/+1 |
| * | Each processor socket in a QPI system has a special PCI bus for the | jhb | 2010-09-07 | 1 | -13/+45 |
| * | When DTrace is enabled, make sure we don't overwrite the IDT_DTRACE_RET | rpaulo | 2010-08-30 | 1 | -0/+25 |
| * | Correctly ensure that the CPU family is 0x6, not non-zero. | jhb | 2010-08-25 | 1 | -1/+2 |
| * | Intel QPI chipsets actually provide two extra "non-core" PCI buses that | jhb | 2010-08-25 | 1 | -0/+286 |
| * | Enable timer interrupt before starting timer. This allows to handle very | mav | 2010-08-24 | 1 | -8/+7 |
| * | When performing a sanity check on the SRAT table to ensure that each | jhb | 2010-07-29 | 1 | -1/+2 |
| * | The corrected error count field is dependent on CMCI, not TES. | jhb | 2010-07-28 | 1 | -1/+1 |
