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* Reimplement how PCI-PCI bridges manage their I/O windows. Previously thejhb2011-05-031-0/+1
* Each processor socket in a QPI system has a special PCI bus for thejhb2010-09-071-13/+45
* Correctly ensure that the CPU family is 0x6, not non-zero.jhb2010-08-251-1/+2
* Intel QPI chipsets actually provide two extra "non-core" PCI buses thatjhb2010-08-251-0/+286
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