| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
| |
Print rid when announcing DMAR context creation. Print sid when fault
occurs.
|
|
|
|
|
|
|
| |
Fix DMAR context allocations for the devices behind PCIe->PCI bridges
after dmar driver was converted to use rids. The bus component to
calculate context page must be taken from the requestor rid, which is
a bridge, and not from the device bus number.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
MFC support for PCI Alternate RID Interpretation. ARI is an optional PCIe
feature that allows PCI devices to present up to 256 functions on a bus.
This is effectively a prerequisite for PCI SR-IOV support.
r264007:
Add a method to get the PCI RID for a device.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264008:
Re-implement the DMAR I/O MMU code in terms of PCI RIDs
Under the hood the VT-d spec is really implemented in terms of
PCI RIDs instead of bus/slot/function, even though the spec makes
pains to convert back to bus/slot/function in examples. However
working with bus/slot/function is not correct when PCI ARI is
in use, so convert to using RIDs in most cases. bus/slot/function
will only be used when reporting errors to a user.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264009:
Re-write bhyve's I/O MMU handling in terms of PCI RID.
Reviewed by: neel
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264011:
Add support for PCIe ARI
PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions. It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number. Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.
This is enabled by default, but it's expected to be a no-op on currently
supported hardware. It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264012:
Print status of ARI capability in pciconf -c
Teach pciconf how to print out the status (enabled/disabled) of the ARI
capability on PCI Root Complexes and Downstream Ports.
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264013:
Add missing copyright date.
MFC after: 2 months
|
|
|
|
|
| |
Avoid excessive flushing and do missed neccessary flushing in the IOMMU
page table update code.
|
|
|
|
| |
Add some support for the PCI(e)-PCI bridges to the Intel VT-d driver.
|
|
|
|
|
| |
Provide a workaround by identity mapping the 32 pages after the bogus
entry start, which seems to be enough for the reported BIOS.
|
|
MFC r257251:
Import the driver for VT-d DMAR hardware. Implement the busdma(9) using DMARs.
MFC r257512:
Add support for queued invalidation.
MFC miscellaneous follow-ups to r257251.
MFC r257266:
Remove redundand assignment to error variable and check for its value.
MFC r257308:
Remove redundand declaration.
MFC r257511:
Return BUS_PROBE_NOWILDCARD from the DMAR probe method.
MFC r257860,r257896,r257900,r257902,r257903 (by dim):
Fixes for gcc compilation.
|