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* - Apparently, it's no longer a problem to call shutdown_nice(9) from withinmarius2013-03-021-12/+14
| | | | | | | | | | an interrupt filter (some other drivers in the tree do the same). So change the overtemperature and power fail interrupts from handlers in order to code and get rid of a !INTR_MPSAFE handlers. - Mark unused parameters as such. - Use NULL instead of 0 for pointers. MFC after: 1 week
* - While Netra X1 generally show no ill effects when registering a powermarius2013-03-021-27/+44
| | | | | | | | | | | | | | | | | fail interrupt handler, there seems to be either a broken batch of them or a tendency to develop a defect which causes this interrupt to fire inadvertedly. Given that apart from this problem these machines work just fine, add a tunable allowing the setup of the power fail interrupt to be disabled. While at it, remove the DEBUGGER_ON_POWERFAIL compile time option and make that behavior also selectable via the newly added tunable. - Apparently, it's no longer a problem to call shutdown_nice(9) from within an interrupt filter (some other drivers in the tree do the same). So change the power fail interrupt from an handler in order to simplify the code and get rid of a !INTR_MPSAFE handler. - Use NULL instead of 0 for pointers. MFC after: 1 week
* - In sbbc_pci_attach() just pass the already obtained bus tag and handlemarius2013-03-011-4/+3
| | | | | | | instead of acquiring these anew. - Use NULL instead of 0 for pointers. MFC after: 1 week
* - Remove an unused header.marius2013-03-011-6/+41
| | | | | | | | | | | - Use NULL instead of 0 for pointers. - Let ofw_pcib_probe() return BUS_PROBE_DEFAULT instead of 0 so specialized PCI-PCI-bridge drivers may attach instead. - Add WARs for PLX Technology PEX 8114 bridges and PEX 8532 switches. Ideally, these should live in MI code but at least for the latter we're missing the necessary infrastructure there. MFC after: 1 week
* MFcalloutng:mav2013-02-281-18/+11
| | | | | | | Switch eventtimers(9) from using struct bintime to sbintime_t. Even before this not a single driver really supported full dynamic range of struct bintime even in theory, not speaking about practical inexpediency. This change legitimates the status quo and cleans up the code.
* Merge from vmobj-rwlock:attilio2013-02-271-3/+2
| | | | | | | | | | | VM_OBJECT_LOCKED() macro is only used to implement a custom version of lock assertions right now (which likely spread out thanks to copy and paste). Remove it and implement actual assertions. Sponsored by: EMC / Isilon storage division Reviewed by: alc Tested by: pho
* Merge from vmobj-rwlock branch:attilio2013-02-261-1/+0
| | | | | | | | Remove unused inclusion of vm/vm_pager.h and vm/vnode_pager.h. Sponsored by: EMC / Isilon storage division Tested by: pho Reviewed by: alc
* Reform the busdma API so that new types may be added without modifyingkib2013-02-123-412/+277
| | | | | | | | | | | | | | | | | | | | | every architecture's busdma_machdep.c. It is done by unifying the bus_dmamap_load_buffer() routines so that they may be called from MI code. The MD busdma is then given a chance to do any final processing in the complete() callback. The cam changes unify the bus_dmamap_load* handling in cam drivers. The arm and mips implementations are updated to track virtual addresses for sync(). Previously this was done in a type specific way. Now it is done in a generic way by recording the list of virtuals in the map. Submitted by: jeff (sponsored by EMC/Isilon) Reviewed by: kan (previous version), scottl, mjacob (isp(4), no objections for target mode changes) Discussed with: ian (arm changes) Tested by: marius (sparc64), mips (jmallet), isci(4) on x86 (jharris), amd64 (Fabian Keil <freebsd-listen@fabiankeil.de>)
* The 'end' word was missed in the comment.kib2013-02-081-2/+2
| | | | MFC after: 3 days
* Remove support for plip from the GENERIC kernel as no systems in theeadler2013-02-011-1/+0
| | | | | | | | | | | last 10 years require this support. Discussed with: db Discussed with: kib Reviewed by: imp Reviewed by: jhb Reviewed by: -hackers Approved by: cperciva (mentor)
* Revert the part of r239864 which removed obtaining the SMP mutex aroundmarius2013-01-232-20/+4
| | | | | | | | | | | | | reading registers from other CPUs. As it turns out, the hardware doesn't really like concurrent IPI'ing causing adverse effects. Also the thought deadlock when using this spin lock here and the targeted CPU(s) are also holding or in case of nested locks can't actually happen. This is due to the fact that on sparc64, spinlock_enter() only raises the PIL but doesn't disable interrupts completely. Thus direct cross calls as used for the register reading (and all other MD IPI needs) still will be executed by the targeted CPU(s) in that case. MFC after: 3 days
* Revert bogus part of r241740.marius2013-01-031-4/+5
| | | | | | Reported by: Michael Moll MFC after: 3 days
* Enable the UFS quotas for big-iron GENERIC kernels.kib2013-01-031-0/+1
| | | | | Discussed with: mckusick MFC after: 2 weeks
* As discussed on -current last October, remove the firewire drivers fromdes2013-01-031-9/+0
| | | | GENERIC.
* Revert r237842 and switch back to SCHED_ULE. All problems I encounteredmarius2012-12-161-1/+1
| | | | | | with the latter have been fixed with r241780. MFC after: 3 days
* Move the declaration of vm_phys_paddr_to_vm_page() from vm/vm_page.hkib2012-11-161-0/+1
| | | | | | | to vm/vm_phys.h, where it belongs. Requested and reviewed by: alc MFC after: 2 weeks
* - Implement run-time expansion of the KTR buffer via sysctl.jeff2012-11-151-0/+1
| | | | | | | | | | - Implement a function to ensure that all preempted threads have switched back out at least once. Use this to make sure there are no stale references to the old ktr_buf or the lock profiling buffers before updating them. Reviewed by: marius (sparc64 parts), attilio (earlier patch) Sponsored by: EMC / Isilon Storage Division
* Flip the semantic of M_NOWAIT to only require the allocation to notkib2012-11-141-8/+1
| | | | | | | | | | | | | | | | | | | | sleep, and perform the page allocations with VM_ALLOC_SYSTEM class. Previously, the allocation was also allowed to completely drain the reserve of the free pages, being translated to VM_ALLOC_INTERRUPT request class for vm_page_alloc() and similar functions. Allow the caller of malloc* to request the 'deep drain' semantic by providing M_USE_RESERVE flag, now translated to VM_ALLOC_INTERRUPT class. Previously, it resulted in less aggressive VM_ALLOC_SYSTEM allocation class. Centralize the translation of the M_* malloc(9) flags in the single inline function malloc2vm_flags(). Discussion started by: "Sears, Steven" <Steven.Sears@netapp.com> Reviewed by: alc, mdf (previous version) Tested by: pho (previous version) MFC after: 2 weeks
* Remove duplicate const specifiers in many drivers (I hope I got all ofdim2012-11-053-4/+4
| | | | | | | | | | | | | | | | | | | | them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
* Rework the known rwlock to benefit about staying on their ownattilio2012-11-032-13/+2
| | | | | | | cache line in order to avoid manual frobbing but using struct rwlock_padalign. Reviewed by: alc, jimharris
* - Give PIL_PREEMPT the lowest priority just above low/stray interrupts.marius2012-10-202-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The reason for this is that the SPARC v9 architecture allows nested interrupts of higher priority/level than that of the current interrupt to occur (and we can't just entirely bypass this model, also, at least for tick interrupts, this also wouldn't be wise). However, when a preemption interrupt interrupts another interrupt of lower priority, f.e. PIL_ITHREAD, and that one in turn is nested by a third interrupt, f.e. PIL_TICK, with SCHED_ULE the execution of interrupts higher than PIL_PREEMPT may be migrated to another CPU. In particular, tl1_ret(), which is responsible for restoring the state of the CPU prior to entry to the interrupt based on the (also migrated) trap frame, then is run on a CPU which actually didn't receive the interrupt in question, causing an inappropriate processor interrupt level to be "restored". In turn, this causes interrupts of the first level, i.e. PIL_ITHREAD in the above scenario, to be blocked on the target of the migration until the correct PIL happens to be restored again on that CPU again. Making PIL_PREEMPT the lowest real priority, this effectively prevents this scenario from happening, as preemption interrupts no longer can interrupt any other interrupt besides stray ones (which is no issue). Thanks to attilio@ and especially mav@ for helping me to understand this problem at the 201208DevSummit. - Give PIL_STOP (which is also used for IPI_STOP_HARD, given that there's no real equivalent to NMIs on SPARC v9) the highest possible priority just below the hardwired PIL_TICK, so it has a chance to interrupt more things. MFC after: 1 week
* - Remove an unused header.marius2012-10-191-6/+4
| | | | | | - Don't waste a delay slot. MFC after: 3 days
* Let SCHED_ULE give affinity to the CPU the tick interrupt triggered onmarius2012-10-191-1/+3
| | | | | | | | when running tick_process(), similarly to what the x86 equivalents of this function do, however employing the less racy sequence also used in intr_event_handle(). MFC after: 3 days
* Add an unified macro to deny ability from the compiler to reorderattilio2012-10-091-3/+3
| | | | | | | | | | instruction loads/stores at its will. The macro __compiler_membar() is currently supported for both gcc and clang, but kernel compilation will fail otherwise. Reviewed by: bde, kib Discussed with: dim, theraven MFC after: 2 weeks
* Reverts r234074,234105,234564,234723,234989,235231-235232 and part ofattilio2012-10-093-15/+3
| | | | | | | | r234247. Use, instead, the static intializer introduced in r239923 for x86 and sparc64 intr_cpus, unwinding the code to the initial version. Reviewed by: marius
* Eliminate a stale comment. It describes another use case for the pmap inalc2012-09-281-5/+0
| | | | Mach that doesn't exist in FreeBSD.
* Correct double "the the"eadler2012-09-141-1/+1
| | | | | Approved by: cperciva MFC after: 3 days
* userret() already checks for td_locks when INVARIANTS is enabled, soattilio2012-09-081-1/+0
| | | | | | | there is no need to check if Giant is acquired after it. Reviewed by: kib MFC after: 1 week
* Prevent indent(1) from reformatting this comment, as it containsgavin2012-09-071-1/+1
| | | | a formatting-sensitive table.
* Add a global MD macro for the VIS block size instead of duplicatingmarius2012-08-314-51/+48
| | | | | | it and using magic values all over the place. MFC after: 1 week
* - Unlike cache invalidation and TLB demapping IPIs, reading registers frommarius2012-08-293-17/+29
| | | | | | | | | | | | | other CPUs doesn't require locking so get rid of it. As the latter is used for the timecounter on certain machine models, using a spin lock in this case can lead to a deadlock with the upcoming callout(9) rework. - Merge r134227/r167250 from x86: Avoid cross-IPI SMP deadlock by using the smp_ipi_mtx spin lock not only for smp_rendezvous_cpus() but also for the MD cache invalidation and TLB demapping IPIs. - Mark some unused function arguments as such. MFC after: 1 week
* Grammar fix: s/NIC's/NICs/gjb2012-08-261-1/+1
| | | | MFC after: 3 days
* Merge r236494 from x86:marius2012-08-052-4/+12
| | | | | | | Isolate the global TTE list lock from data and other locks to prevent false sharing within the cache. MFC after: 3 days
* Switch back to the 4BSD scheduler for now. There is some more or lessmarius2012-06-301-1/+1
| | | | | | | | recent regression with ULE, causing processes to get stuck in getblk as well as interrupt handler execution delays to rise above the command timeout of mpt(4). MFC after: 3 days
* Now that the mps(4) driver is endian-safe, add it to the powerpc andken2012-06-281-0/+1
| | | | | | sparc64 GENERIC config files. MFC after: 3 days
* Add new pmap layer locks to the predefined lock order. Change the namesalc2012-06-271-2/+3
| | | | of a few existing VM locks to follow a consistent naming scheme.
* Make the wchar_t type machine dependent.andrew2012-06-242-6/+4
| | | | | | | | | | | | | | This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an unsigned short with the former preferred. Because of this requirement we need to move the definition of __wchar_t to a machine dependent header. It also cleans up the macros defining the limits of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine dependent header then using them to define WCHAR_MIN and WCHAR_MAX respectively. Discussed with: bde
* Implement mechanism to export some kernel timekeeping data tokib2012-06-221-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usermode, using shared page. The structures and functions have vdso prefix, to indicate the intended location of the code in some future. The versioned per-algorithm data is exported in the format of struct vdso_timehands, which mostly repeats the content of in-kernel struct timehands. Usermode reading of the structure can be lockless. Compatibility export for 32bit processes on 64bit host is also provided. Kernel also provides usermode with indication about currently used timecounter, so that libc can fall back to syscall if configured timecounter is unknown to usermode code. The shared data updates are initiated both from the tc_windup(), where a fast task is queued to do the update, and from sysctl handlers which change timecounter. A manual override switch kern.timecounter.fast_gettime allows to turn off the mechanism. Only x86 architectures export the real algorithm data, and there, only for tsc timecounter. HPET counters page could be exported as well, but I prefer to not further glue the kernel and libc ABI there until proper vdso-based solution is developed. Minimal stubs neccessary for non-x86 architectures to still compile are provided. Discussed with: bde Reviewed by: jhb Tested by: flo MFC after: 1 month
* Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer tokib2012-06-221-0/+1
| | | | | | timekeeping information. MFC after: 1 week
* The page flag PGA_WRITEABLE is set and cleared exclusively by the pmapalc2012-06-161-0/+1
| | | | | | | | | | | | | | | | layer, but it is read directly by the MI VM layer. This change introduces pmap_page_is_write_mapped() in order to completely encapsulate all direct access to PGA_WRITEABLE in the pmap layer. Aesthetics aside, I am making this change because amd64 will likely begin using an alternative method to track write mappings, and having pmap_page_is_write_mapped() in place allows me to make such a change without further modification to the MI VM layer. As an added bonus, tidy up some nearby comments concerning page flags. Reviewed by: kib MFC after: 6 weeks
* Replace all uses of the vm page queues lock by a r/w lock that is privatealc2012-05-293-47/+55
| | | | | | | | | | | | | to this pmap.c. This new r/w lock is used primarily to synchronize access to the TTE lists. However, it will be used in a somewhat unconventional way. As finer-grained TTE list locking is added to each of the pmap functions that acquire this r/w lock, its acquisition will be changed from write to read, enabling concurrent execution of the pmap functions with finer-grained locking. Reviewed by: attilio Tested by: flo MFC after: 10 days
* Merge from x86: r232521marius2012-05-251-28/+0
| | | | Exclude USB drivers (except umass and ukbd) from main kernel image.
* MFp4 bz_ipv6_fast:bz2012-05-241-0/+4
| | | | | | | | | | | | | | | | | | | | in_cksum.h required ip.h to be included for struct ip. To be able to use some general checksum functions like in_addword() in a non-IPv4 context, limit the (also exported to user space) IPv4 specific functions to the times, when the ip.h header is present and IPVERSION is defined (to 4). We should consider more general checksum (updating) functions to also allow easier incremental checksum updates in the L3/4 stack and firewalls, as well as ponder further requirements by certain NIC drivers needing slightly different pseudo values in offloading cases. Thinking in terms of a better "library". Sponsored by: The FreeBSD Foundation Sponsored by: iXsystems Reviewed by: gnn (as part of the whole) MFC After: 3 days
* MFprojects/zfsd:mav2012-05-241-1/+1
| | | | Generalize and unify ses device description.
* Fix mismerge in r235231.marius2012-05-101-1/+1
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* Merge r234989 from x86:marius2012-05-102-9/+2
| | | | Revert part of r234723 by re-enabling the SMP protection for intr_bind().
* Add a convenience macro for the returns_twice attribute, and apply it todim2012-04-291-1/+1
| | | | | | | the prototypes of the appropriate functions (getcontext, savectx, setjmp, sigsetjmp and vfork). MFC after: 2 weeks
* Clean up the intr* MD KPI from the SMP dependency, removing a cause ofattilio2012-04-263-4/+16
| | | | | | | | | | | discrepancy between modules and kernel, but deal with SMP differences within the functions themselves. As an added bonus this also helps in terms of code readability. Requested by: gibbs Reviewed by: jhb, marius MFC after: 1 week
* Turn on PREEMPTION by default. After fixing several bugs over time, themarius2012-04-161-1/+1
| | | | | | | | | | | last show-stopper keeping PREEMPTION from being usable on sparc64 should have been dealt with in r230662. At least on 2-way systems, PREEMPTION causes a little bit of a degradation in worldstone performance. However, FreeBSD seems to have started building up regressions in !PREEMPTION cases so sparc64 better should not be an oddball in this regard. MFC after: 1 week
* Merge from x86:marius2012-04-132-3/+7
| | | | | | | | | | | | | | | | | | | | | | | r233961: Fix interrupt load balancing regression, introduced in revision 222813, that left all un-pinned interrupts assigned to CPU 0. In intr_shuffle_irqs(), remove CPU_SETOF() call that initialized the "intr_cpus" cpuset to only contain CPU0. This initialization is too late and nullifies the results of calls to the intr_add_cpu() that occur much earlier in the boot process. r234074 (partial): The BSP is not added to the mask of valid target CPUs for interrupts. Fix this by adding the BSP as an interrupt target directly in r234105: Fix !SMP build after r234074. MFC after: 3 days
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