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* Fix typos, mostly s/ an / a / where appropriate and a few s/an/and/schweikh2002-12-302-2/+2
| | | | Add FreeBSD Id tag where missing.
* Use memset instead of __builtin_memset. Apparently there's an inlinejake2002-12-291-1/+1
| | | | memset in libkern which causes problems; why that's there is beyond me.
* Use the meaningful mnemonics for ancillary state registers now that gasjake2002-12-293-8/+7
| | | | | | | | is invoked properly to understand them. %asr19 -> %gsr %asr20 -> %set_softint %asr21 -> %clear_softint
* Forgot this file in previous commit.jake2002-12-281-0/+1
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* - Moved storing %g1-%g5 in the trapframe until after interrupts are enabled.jake2002-12-281-27/+41
| | | | | | - Restore %g6 and %g7 for kernel traps if we are returning to prom code. This allows complex traps (ones that call into C code) to be handled from the prom.
* Pass 0 in %o1 to tl0_trap for all non-interrupt traps. This will be usedjake2002-12-281-0/+7
| | | | to pass the pil when tl0_trap also handles interrupts.
* Hold the page queues lock around calls to vm_page_flag_clear() andalc2002-12-281-0/+4
| | | | vm_page_wakeup().
* Use VM_ALLOC_WIRED in pmap_pinit().alc2002-12-281-4/+1
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* Define UMA_MD_SMALL_ALLOC so that uma_small_alloc and uma_small_free willjake2002-12-271-0/+2
| | | | | | | be used for zones that allocate objects of less 1 page. The biggest advantage of this is that all of a sudden the majority of kernel malloc-ed data doesn't need kva allocated for it. Besides microbenchmarks I haven't seen a measurable performance improvement from doing this.
* Teach /dev/kmem about direct mapped addresses.jake2002-12-271-5/+6
| | | | | Note that a better solution for how to make kernacc work for direct mapped addresses is needed for all platforms that use them.
* Implement uma_small_alloc and uma_small_free. Not yet used.jake2002-12-271-0/+52
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* - Use direct mapped addresses for the message buffer, for the crash dumpjake2002-12-273-62/+12
| | | | | mappings, and for pmap_map which is used to map the vm_page structures. - Don't allocate kva space for any of the above.
* - Change the way the direct mapped region is implemented to be generallyjake2002-12-235-108/+220
| | | | | | | | | | | | | | | | | | | | | useful for accessing more than 1 page of contiguous physical memory, and to use 4mb tlb entries instead of 8k. This requires that the system only use the direct mapped addresses when they have the same virtual colour as all other mappings of the same page, instead of being able to choose the colour and cachability of the mapping. - Adapt the physical page copying and zeroing functions to account for not being able to choose the colour or cachability of the direct mapped address. This adds a lot more cases to handle. Basically when a page has a different colour than its direct mapped address we have a choice between bypassing the data cache and using physical addresses directly, which requires a cache flush, or mapping it at the right colour, which requires a tlb flush. For now we choose to map the page and do the tlb flush. This will allows the direct mapped addresses to be used for more things that don't require normal pmap handling, including mapping the vm_page structures, the message buffer, temporary mappings for crash dumps, and will provide greater benefit for implementing uma_small_alloc, due to the much greater tlb coverage.
* - Fix a bug where the faulting address for an mmu miss could sometimes bejake2002-12-231-5/+5
| | | | | | clobbered due to some debug code. This was harmless and just superfluous soft faults. - Update some comments.
* - Rearrange pmap_bootstrap slightly to be more in dependency order.jake2002-12-221-50/+49
| | | | | | | - Put the kernel tsb before before the kernel load address, below VM_MIN_KERNEL_ADDRESS, instead of after the kernel where it consumes usable kva. This is magic mapped so the virtual address is irrelevant, it just needs to be out of the way.
* - Add a spin lock to single thread cache invalidation and tlb flush ipis,jake2002-12-224-19/+19
| | | | | which allows ipis to be sent outside of Giant. - Remove the ap boot mutex, which is unused.
* MB_LEN_MAX is not MD, move it to the MI limits.h.tjr2002-12-222-2/+0
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* - Add a pmap pointer to struct md_page, and use this to find the pmap thatjake2002-12-214-69/+70
| | | | | | | | | | | | | | | | | | | | | | | | a mapping belongs to by setting it in the vm_page_t structure that backs the tsb page that the tte for a mapping is in. This allows the pmap that a mapping belongs to to be found without keeping a pointer to it in the tte itself. - Remove the pmap pointer from struct tte and use the space to make the tte pv lists doubly linked (TAILQs), like on other architectures. This makes entering or removing a mapping O(1) instead of O(n) where n is the number of pmaps a page is mapped by (including kernel_pmap). - Use atomic ops for setting and clearing bits in the ttes, now that they return the old value and can be easily used for this purpose. - Use __builtin_memset for zeroing ttes instead of bzero, so that gcc will inline it (4 inline stores using %g0 instead of a function call). - Initially set the virtual colour for all the vm_page_ts to be equal to their physical colour. This will be more useful once uma_small_alloc is implemented, but basically pages with virtual colour equal to phsyical colour are easier to handle at the pmap level because they can be safely accessed through cachable direct virtual to physical mappings with that colour, without fear of causing illegal dcache aliases. In total these changes give a minor performance improvement, about 1% reduction in system time during buildworld.
* Make pmap_qenter and pmap_qremove look more like the other pmaps.jake2002-12-211-7/+10
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* Removed unused pmap_qenter_flags.jake2002-12-212-17/+0
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* Make the atomic arithmetic functions return the old value, since they'rejake2002-12-211-40/+38
| | | | all implemented with cas anyway.
* Add page queue locking around functions that call vm_page_flag_set. Thisjake2002-12-202-0/+4
| | | | | | fixes a failed assertion early in boot on sparc64. Reported by: Roderick van Domburg <r.s.a.vandomburg@student.utwente.nl>
* Unbreak the KSE code. Keep track of zobie threads using the Per-CPU storagejulian2002-12-101-1/+1
| | | | | | | | during the context switch. Rearrange thread cleanups to avoid problems with Giant. Clean threads when freed or when recycled. Approved by: re (jhb)
* Exclude yet more interrupt mapping registers from the OBIO INO search,tmm2002-12-061-2/+2
| | | | | | | | | | namely the ones for the timers, error handling and power management. The registers for the timers, power management and PCI bus b errors are reserved on Sabres (US-IIi) and can lead to false matches there. Since all of them are never used for devices on the bus, they can be omitted safely. Approved by: re
* Remove a workaround for a binutils bug that was fixed in the recenttmm2002-12-021-19/+4
| | | | | | | | | | import, as it breaks the relocation kernel modules built with the new binutils. Note that this, together with the binutils import, marks a kernel module flag day on sparc64: modules built with the old binutils will not work with new kernels and vice versa. Mismatches will result in panics. Approved by: re
* Always initialize the UPA target module id in the interrupt mappingtmm2002-12-013-33/+34
| | | | | | | | | | | | register to the one of the processor doing the interrupt setup. This is required since this field is preinitialized to 0, but there exist machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2 processors). Add some more macros for handle the interrupt mapping registers, and rename some existing ones for consistency. Approved by: re
* 1.) Do not look for PCI INOs in the FFB interrupt mapping registers; theytmm2002-12-011-2/+6
| | | | | | | | | | | are nevers used for PCI interrupts, but can cause false matches since they are fully programmable. 2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges, since they are not present there. Again, this could cause false matches, which would result in the interrupt being delivered at most once. Submitted by: jake (2) Approved by: re
* Remove some long-dead cruft in the interrupt handling code which wastmm2002-12-011-44/+31
| | | | | | never used in FreeBSD. Approved by: re
* Reverse the quirk table entry for swizzling on a missing interrupt map;tmm2002-12-011-7/+10
| | | | | | | | | | | | | this is now done on all machines except for some known problematic ones. Add an additional guard to make sure that the interrupt numbers are in the correct range before swizzling. This should catch any remaining models for which the swizzle is inappropriate. Correct the swizzle calculation to account for the fact that the parent interrupt numbers to be swizzled are 1-based. Approved by: re
* Fix some comments describing psycho registers.tmm2002-12-011-2/+2
| | | | Approved by: re
* Do not panic when a dmamap is unloaded more then once, but just silentlytmm2002-12-011-4/+2
| | | | | | | ignore it. This is non-fatal on the other architectures, and some drivers seem to do this. Approved by: re
* Add page queues locking to vunmapbuf().alc2002-11-241-0/+2
| | | | Approved by: re (blanket)
* Under certain circumstances, we were calling kmem_free() frommux2002-11-221-0/+5
| | | | | | | | | | i386 cpu_thread_exit(). This resulted in a panic with WITNESS since we need to hold Giant to call kmem_free(), and we weren't helding it anymore in cpu_thread_exit(). We now do this from a new MD function, cpu_thread_dtor(), called by thread_dtor(). Approved by: re@ Suggested by: jhb
* Fix compile in the case of SMP defined but DDB not defined.jhb2002-11-201-1/+7
| | | | Approved by: re (implicit, DP2 doesn't build w/o this)
* Run configure at SI_SUB_THIRD instead of SI_SUB_ANY like otherjake2002-11-181-1/+1
| | | | architectures.
* MFi386 r1.369. Clear the PG_WRITEABLE flag in pmap_clear_write; returnjake2002-11-171-1/+3
| | | | | | immediately if its already clear. Suggested by: alc
* Add getcontext, setcontext, and swapcontext as system calls.deischen2002-11-161-0/+14
| | | | | | | | | | | Previously these were libc functions but were requested to be made into system calls for atomicity and to coalesce what might be two entrances into the kernel (signal mask setting and floating point trap) into one. A few style nits and comments from bde are also included. Tested on alpha by: gallatin
* Don't register the powerfail interrupt as fast in thetmm2002-11-141-2/+8
| | | | | | | non-DEBUGGER_ON_POWERFAIL case so that shutdown_nice() can be called without problems. Reported & tested by: Gavin Atkinson <gavin@ury.york.ac.uk>
* Move pmap_collect() out of the machine-dependent code, rename italc2002-11-132-11/+0
| | | | | | | | to reflect its new location, and add page queue and flag locking. Notes: (1) alpha, i386, and ia64 had identical implementations of pmap_collect() in terms of machine-independent interfaces; (2) sparc64 doesn't require it; (3) powerpc had it as a TODO.
* - Clear the page's PG_WRITEABLE flag in the i386's pmap_changebit()alc2002-11-111-2/+0
| | | | | | if we're removing write access from the page's PTEs. - Export pmap_remove_all() on alpha, i386, and ia64. (It's already exported on sparc64.)
* Remove physmem from here, too, as it is defined in vm_init.c sincetmm2002-11-081-1/+0
| | | | | | r1.35 (forgotten in my last commit due to a botched patch). Pointy hat to: tmm
* Add two new workaround for firmware anomalies:tmm2002-11-079-18/+102
| | | | | | | | | | | | | | | | | 1. At least some Netra t1 models have PCI buses with no associated interrupt map, but obviously expect the PCI swizzle to be done with the interrupt number from the higher level as intpin. In this case, the mapping also needs to continue at parent bus nodes. To handle that, add a quirk table based on the "name" property of the root node to avoid breaking other boxen. This property is now retrieved and printed at boot. 2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped at all, and full interrupt numbers (not just INOs) are given in the interrupt properties. This is more or less cosmetical; the PCI interrupt numbers would be wrong, but the psycho resource allocation method would pass the right numbers on anyway. Tested by: mux (1), Maxim Mazurok <maxim@km.ua> (2)
* s/HZ/Hz/mux2002-11-061-1/+1
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* Remove what was a temporary bogus assignment of bits of siginfo_t, as it doesjmallett2002-11-061-2/+0
| | | | | | not look like the prerequisites to fill it in properly will be in the tree for the upcoming release, but it's mostly done, so there is no need for these to stay around to remind us.
* Don peril sensitive sun glasses and change the default system call vectorjake2002-10-272-4/+37
| | | | | | | | | | | | | | | | | for sparc64 from trap #9 to trap #65. This is one of the ABI "blessed" system call vectors and is different from any other system that we might want to emulate, making the emulation easier by reducing the number of code paths that need to be shared. Compatibility with old applications is provided with COMPAT_FREEBSD4. Add defines for a few special traps that we may need to implement for compatibility with 32bit applications, and add comments on which vectors are used for what in other systems, and which are available. Pass magic flags to trap() for deprecated or unimplemented system call vectors so they will deliver SIGSYS instead of SIGILL. This piggy backs nicely with the recent sigaction(2) system call number change, and provided the rules are followed for upgrading past it, this change should not be noticed.
* Allow deprecated or unimplemented system call vectors to deliver SIGSYS,jake2002-10-261-1/+1
| | | | as suggested by the sparc v9 ABI.
* Remove an unused macro.jake2002-10-261-6/+0
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* Add COMPAT_FREEBSD4 for the transition. COMPAT_43 was already present.peter2002-10-261-0/+1
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* Split 4.x and 5.x signal handling so that we can keep 4.x signalpeter2002-10-252-22/+10
| | | | | | | | | | | | | | | | handling clean and functional as 5.x evolves. This allows some of the nasty bandaids in the 5.x codepaths to be unwound. Encapsulate 4.x signal handling under COMPAT_FREEBSD4 (there is an anti-foot-shooting measure in place, 5.x folks need this for a while) and finish encapsulating the older stuff under COMPAT_43. Since the ancient stuff is required on alpha (longjmp(3) passes a 'struct osigcontext *' to the current sigreturn(2), instead of the 'ucontext_t *' that sigreturn is supposed to take), add a compile time check to prevent foot shooting there too. Add uniform COMPAT_43 stubs for ia64/sparc64/powerpc. Tested on: i386, alpha, ia64. Compiled on sparc64 (a few days ago). Approved by: re
* Initialize tick_MHz and related variables much earlier. After the lasttmm2002-10-253-13/+17
| | | | | | | revision of tick.c, this was done at SI_SUB_CLOCKS, which is too late because tick_MHz is required for DELAY() to work. Reviewed by: jake
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