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* 1. Implement an optimization for pmap_remove() and pmap_protect(): if atmm2002-01-024-48/+143
* Correct the defintion of struct ofw_upa_regs, and use it instead oftmm2002-01-026-61/+82
* Close a window of time during early boot in which an interrupt wouldtmm2002-01-021-18/+18
* Correctly identify the cpu in certain ultra 1s.jake2002-01-011-0/+1
* Define __ASM__ so that libc will know not to define C things.jake2002-01-011-0/+2
* Add a define for the fp restore soft trap type.jake2002-01-011-1/+2
* Add constants needed by user trap code.jake2002-01-011-0/+6
* Enable virtual caching for kernel pages. When we enabled virtual cachingjake2002-01-011-3/+3
* Add some more info to traces.jake2002-01-012-38/+26
* Ensure that the syscall trap vector is properly aligned.jake2002-01-012-0/+2
* Implement sysarch(SPARC_UTRAP_INSTALL).jake2002-01-011-0/+69
* Implement user trap delivery as specified by the sparc abi. This providesjake2002-01-016-4/+189
* Add a panic stack, which is used as a known good stack when there isjake2002-01-016-9/+244
* Add a soft trap for restoring the fpu registers from the pcb.jake2002-01-012-0/+24
* Fix long lines in the trap table due to the abi specificied trap typesjake2002-01-012-258/+260
* Do not include pcib.h, which only existed in my development tree, and dotmm2001-12-301-2/+1
* Add bus_common.h, which contains some definiton that apply to both PCItmm2001-12-301-0/+69
* Make these compile.jake2001-12-293-24/+18
* Remove local change that crept in.jake2001-12-291-1/+0
* Add a header for user trap types required by the sparc abi.jake2001-12-291-0/+84
* Adapt for used by upcoming fp emulation code.jake2001-12-291-62/+41
* Print the correct v9 opcodes.jake2001-12-291-18/+18
* Update to new constants.jake2001-12-291-34/+34
* Make cont in ddb work.jake2001-12-291-0/+1
* Prototype dcache_inval_phys.jake2001-12-291-0/+1
* Add comments as to why VM_MAXUSER_ADDRESS is magic (abitrary).jake2001-12-291-6/+21
* Make tte bit constants explicitly unsigned and long.jake2001-12-291-46/+33
* Add definitions for dcache color bits, which may move to cache.h.jake2001-12-291-6/+36
* Implement pv entries as separate structures from the ttes, like otherjake2001-12-291-162/+29
* Remove support for multi level tsbs, making this code much simpler andjake2001-12-292-356/+103
* Implement pv entries as separate structures from the ttes, as otherjake2001-12-291-172/+177
* Great pmap rewrite to use a much simpler one level tsb of ttes, insteadjake2001-12-291-430/+867
* Use fprs to track floating register usage. Clear it once we've savedjake2001-12-292-344/+270
* Add .register directives for gcc3.jake2001-12-292-1372/+1634
* Add needed include of fsr.h.jake2001-12-291-5/+5
* 1. Adapt to new trap types.jake2001-12-291-137/+149
* Add .register directives for gcc3.jake2001-12-292-34/+74
* Assert at compile time that structures which need to be a power ofjake2001-12-291-6/+10
* Remove a debug printf.jake2001-12-291-70/+59
* intr_handlers is an array of function pointers, not small structures.jake2001-12-291-2/+5
* Add .register directive for gcc3.jake2001-12-292-4/+16
* 1. Make this more name space friendly (* -> emul_*).jake2001-12-291-20/+16
* Be paranoid about the sizeof passed to db_get_value, not all trapframejake2001-12-291-136/+91
* Implement dcache_inval_phys, which shoots the cache lines that correspondjake2001-12-291-4/+29
* Rename definitions to better match the hardware wstate fields.jake2001-12-291-2/+2
* Add definitions for TSTATE_MM_* and TSTATE_{I,X}CC_*.jake2001-12-291-0/+10
* Rename and renumber trap types to comply with the user trap types asjake2001-12-291-40/+54
* 1. Certain tlb operations need to be atomic, so disable interrupts forjake2001-12-291-0/+54
* jmpbuf is no longer a ucontext_t since it does not need to be passedjake2001-12-291-1/+7
* Add fprs to struct fpreg.jake2001-12-291-0/+1
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