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* - Remove the eintrcnt/eintrnames usage and introduce the concept ofattilio2011-07-182-5/+8
| | | | | | | | | | | | | | | | sintrcnt/sintrnames which are symbols containing the size of the 2 tables. - For amd64/i386 remove the storage of intr* stuff from assembly files. This area can be widely improved by applying the same to other architectures and likely finding an unified approach among them and move the whole code to be MI. More work in this area is expected to happen fairly soon. No MFC is previewed for this patch. Tested by: pluknet Reviewed by: jhb Approved by: re (kib)
* Remove NULL assignments which are redundant for static timecounters.marius2011-07-121-4/+0
| | | | Submitted by: jkim
* - Remove redundant timecounter masking from counter_get_timecount().marius2011-07-121-4/+2
| | | | | | | - Zero the timecounter when allocation so we don't need to initialize unused members and remove a now redundant NULL assignment. Submitted by: jkim
* - Current testing shows that (ab)using the JBC performance counter in busmarius2011-07-121-13/+10
| | | | | | | | cycle mode as timecounter just works fine. My best guess is that a firmware update has fixed this, check at run-time whether it advances and use a positive quality if it does. The latter will cause this timecounter to be used instead of the tick counter based one, which just sucks for SMP. - Remove a redundant NULL assignment from the timecounter initialization.
* - Add a missing shift in schizo_get_timecount(). This happened to be non-fatalmarius2011-07-121-3/+3
| | | | | | | as STX_CTRL_PERF_CNT_CNT0_SHIFT actually is zero, if we were using the second counter in the upper 32 bits this would be required though as the MI timecounter code doesn't support 64-bit counters/counter registers. - Remove a redundant NULL assignment from the timecounter initialization.
* Remove the IDR_CHEETAH_MAX_BN_PAIRS limit from cheetah_ipi_selected().marius2011-07-051-2/+2
| | | | | | This is just a simple approach. For reasons unknown OpenSolaris uses a more sophisticated one involving IPIing the remaining CPUs in reverse order after the first batch of 32.
* It can be useful to know which page still has mappings.marius2011-07-051-1/+1
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* - pmap_cache_remove() and pmap_protect_tte() are only used within pmap.cmarius2011-07-052-6/+6
| | | | | so static'ize them. - Correct a typo.
* In pmap_remove_all() assert that the page is neither fictitious normarius2011-07-051-0/+2
| | | | | | unmanaged as also done on other architectures. Reviewed by: alc
* Call pmap_qremove() before freeing or unwiring the pages, otherwisemarius2011-07-051-1/+1
| | | | | | | | there's a window during which a page can be re-used before its previous mapping is removed. Reviewed by: alc MFC after: 1 week
* With retirement of cpumask_t and usage of cpuset_t for representing aattilio2011-07-041-8/+0
| | | | | | | | | | | | | | | mask of CPUs, pc_other_cpus and pc_cpumask become highly inefficient. Remove them and replace their usage with custom pc_cpuid magic (as, atm, pc_cpumask can be easilly represented by (1 << pc_cpuid) and pc_other_cpus by (all_cpus & ~(1 << pc_cpuid))). This change is not targeted for MFC because of struct pcpu members removal and dependency by cpumask_t retirement. MD review by: marcel, marius, alc Tested by: pluknet MD testing by: marcel, marius, gonzo, andreast
* UltraSPARC-IV CPUs seem to be affected by a not publicly documentedmarius2011-07-022-1/+26
| | | | | | | | | erratum causing them to trigger stray vector interrupts accompanied by a state in which they even fault on locked TLB entries. Just retrying the instruction in that case gets the CPU back on track though. OpenSolaris also just ignores a certain number of stray vector interrupts. While at it, implement the stray vector interrupt handling for SPARC64-VI which use these for indicating uncorrectable errors in interrupt packets.
* Don't waste a delay slot.marius2011-07-021-2/+2
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* - For Cheetah- and Zeus-class CPUs don't flush all unlocked entries frommarius2011-07-0210-68/+249
| | | | | | | | | | | | | | | | | | | the TLBs in order to get rid of the user mappings but instead traverse them an flush only the latter like we also do for the Spitfire-class. Also flushing the unlocked kernel entries can cause instant faults which when called from within cpu_switch() are handled with the scheduler lock held which in turn can cause timeouts on the acquisition of the lock by other CPUs. This was easily seen with a 16-core V890 but occasionally also happened with 2-way machines. While at it, move the SPARC64-V support code entirely to zeus.c. This causes a little bit of duplication but is less confusing than partially using Cheetah-class bits for these. - For SPARC64-V ensure that 4-Mbyte page entries are stored in the 1024- entry, 2-way set associative TLB. - In {d,i}tlb_get_data_sun4u() turn off the interrupts in order to ensure that ASI_{D,I}TLB_DATA_ACCESS_REG actually are read twice back-to-back. Tested by: Peter Jeremy (16-core US-IV), Michael Moll (2-way SPARC64-V)
* Using .comm to declare intrnames and eintrnames causes binutils 2.17.50 tomarius2011-07-021-5/+12
| | | | merge the two.
* Add some checks to ensure that Capsicum is behaving correctly, and add somejonathan2011-06-301-0/+21
| | | | | | | more explicit comments about what's going on and what future maintainers need to do when e.g. adding a new operation to a sys_machdep.c. Approved by: mentor(rwatson), re(bz)
* Fix whitespacemarius2011-06-211-5/+5
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* On machines where we don't need to lock the kernel TSB into the dTLB andmarius2011-06-212-2/+2
| | | | | thus may basically use the entire 64-bit kernel address space reduce VM_KMEM_SIZE_SCALE to 1 allowing kernel to use more memory.
* On machines where we don't need to lock the kernel TSB into the dTLB andmarius2011-06-211-3/+6
| | | | | thus may basically use the entire 64-bit kernel address space increase the kernel virtual memory to not be limited by VM_KMEM_SIZE_MAX.
* As astopgap minimize the sched_lock coverage in pmap_activate() in ordermarius2011-06-201-4/+4
| | | | to reduce lock contention.
* - Remove MD usage of pc_cpumask and pc_other_cpus. [1]marius2011-06-203-16/+15
| | | | | | - Remove CTASSERTs which no longer need to hold since r222813. Submitted by: attilio [1]
* - As with stray vector interrupts limit the reporting of stray levelmarius2011-06-181-9/+20
| | | | | | | | | | interrupts. Bringup on additional machine models repeatedly reveals firmware that enables interrupts behind our back, causing the console to be flooded otherwise. - As with the regular interrupt counters using uint16_t instead of u_long for counting the stray vector interrupts should be more than sufficient. - Cache the interrupt vector in intr_stray_vector().
* Don't include curcpu in the mask which is used as the IPI cookie as wemarius2011-06-151-12/+16
| | | | | | | have to ignore it when sending the IPI anyway. Actually I can't think of a good reason why this ever was done that way in the first place as it's not even usefull for debugging. While at it replace the use of pc_other_cpus as it's slated for deorbit.
* - Merge r222980 from x86: add sound(4) and common device drivers.marius2011-06-131-2/+9
| | | | - Fix whitespace.
* - For the case when tl1_align(_trap) is used to call rsf_fatal viamarius2011-06-071-2/+3
| | | | | | | | RSF_FATAL we need to switch to alternate globals for KSTACK_CHECK just like tl1_data_excptn(_trap) does. This is more or less cosmetic because in case RSF_FATAL is called we're already heading south. - Correct an END(). - Read the window state from the correct register for a CATR().
* Adapt CATR() to r222813. This is somewhat tricky as we can't afford usingmarius2011-06-074-61/+88
| | | | | | | | | more than three temporary register in several places CATR() is used so this code trades instructions in for registers. Actually, this still isn't sufficient and CATR() has the side-effect of clobbering %y. Luckily, with the current uses of CATR() this either doesn't matter or we are able to (save and) restore it. Now that there's only one use of AND() and TEST() left inline these.
* Fix a problem with r222813; given that we may only operate on interruptmarius2011-06-071-9/+11
| | | | globals here but clobber %y save and restore the latter.
* MFCattilio2011-05-312-2/+2
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* Fix KTR_CPUMASK in order to accept a string representing a cpuset_t.attilio2011-05-311-0/+2
| | | | | | | | | | | | This introduce all the underlying support for making this possible (via the function cpusetobj_strscan() and keeps ktr_cpumask exported. sparc64 implements its own assembly primitives for tracing events and needs to properly check it. Anyway the sparc64 logic is not implemented yet due to lack of knowledge (by me) and time (by marius), but it is just a matter of using ktr_cpumask when possible. Tested and fixed by: pluknet Reviewed by: marius
* Revert a change that crept in during MFC.attilio2011-05-311-2/+0
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* MFCattilio2011-05-311-0/+2
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* | Revert a patch that unvolountary sneaked in while I was MFCing.attilio2011-05-231-2/+0
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* | MFCattilio2011-05-231-0/+2
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* | MFCattilio2011-05-151-1/+4
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| * Recognize the eeprom device found in Fujitsu PRIMEPOWER650 and 900.marius2011-05-151-1/+4
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| * Disconnect sun4v architecture from the three.attilio2011-05-143-65/+0
| | | | | | | | | | | | | | | | | | Some files keep the SUN4V tags as a code reference, for the future, if any rewamped sun4v support wants to be added again. Reviewed by: marius Tested by: sbruno Approved by: re
| * Move the ZERO_REGION_SIZE to a machine-dependent file, as on manymdf2011-05-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | architectures (i386, for example) the virtual memory space may be constrained enough that 2MB is a large chunk. Use 64K for arches other than amd64 and ia64, with special handling for sparc64 due to differing hardware. Also commit the comment changes to kmem_init_zero_region() that I missed due to not saving the file. (Darn the unfamiliar development environment). Arch maintainers, please feel free to adjust ZERO_REGION_SIZE as you see fit. Requested by: alc MFC after: 1 week MFC with: r221853
* | Fix yet another inversion in the logic by applying the x86 version of this,marius2011-05-141-2/+2
| | | | | | | | | | which avoids CPU_EMPTY() in the first place. Do I get a beer or something for every inversion I find?
* | MFCattilio2011-05-143-65/+0
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* | MFCattilio2011-05-131-0/+7
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* | When setting up pc_other_cpus for APs based on pc_allcpu clear pc_cpuidmarius2011-05-131-1/+1
| | | | | | | | | | in the former rather than the latter. This gets this branch working on at least Jalapeno-class CPUs.
* | MFCattilio2011-05-121-0/+11
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| * Add an ATOMIC_CLEAR_LONG.marius2011-05-101-0/+11
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| * Retire isa_setup_intr() and isa_teardown_intr() and use the generic busjhb2011-05-061-23/+0
| | | | | | | | | | | | versions instead. They were never needed as bus_generic_intr() and bus_teardown_intr() had been changed to pass the original child device up in 42734, but the ISA bus was not converted to new-bus until 45720.
| * Reimplement how PCI-PCI bridges manage their I/O windows. Previously thejhb2011-05-032-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | driver would verify that requests for child devices were confined to any existing I/O windows, but the driver relied on the firmware to initialize the windows and would never grow the windows for new requests. Now the driver actively manages the I/O windows. This is implemented by allocating a bus resource for each I/O window from the parent PCI bus and suballocating that resource to child devices. The suballocations are managed by creating an rman for each I/O window. The suballocated resources are mapped by passing the bus_activate_resource() call up to the parent PCI bus. Windows are grown when needed by using bus_adjust_resource() to adjust the resource allocated from the parent PCI bus. If the adjust request succeeds, the window is adjusted and the suballocation request for the child device is retried. When growing a window, the rman_first_free_region() and rman_last_free_region() routines are used to determine if the front or end of the existing I/O window is free. From using that, the smallest ranges that need to be added to either the front or back of the window are computed. The driver will first try to grow the window in whichever direction requires the smallest growth first followed by the other direction if that fails. Subtractive bridges will first attempt to satisfy requests for child resources from I/O windows (including attempts to grow the windows). If that fails, the request is passed up to the parent PCI bus directly however. The PCI-PCI bridge driver will try to use firmware-assigned ranges for child BARs first and only allocate a "fresh" range if that specific range cannot be accommodated in the I/O window. This allows systems where the firmware assigns resources during boot but later wipes the I/O windows (some ACPI BIOSen are known to do this) to "rediscover" the original I/O window ranges. The ACPI Host-PCI bridge driver has been adjusted to correctly honor hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge makes a wildcard request for an I/O window range. The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option is enabled. This is a transition aide to allow platforms that do not yet support bus_activate_resource() and bus_adjust_resource() in their Host-PCI bridge drivers (and possibly other drivers as needed) to use the old driver for now. Once all platforms support the new driver, the kernel option and old driver will be removed. PR: kern/143874 kern/149306 Tested by: mav
* | Update for the fact that the first members of the IPI args structures andmarius2011-05-122-12/+21
| | | | | | | | | | | | | | | | | | | | pc_cpumask were changed to cpuset_t. This now calculates the cpumask based on pc_cpuid itself as pc_cpumask is slated for being deorbited. Note that this needs r221750 to be MFC'ed in order to compile. This seems to work fine but after a few dozens of successful IPIs something suddenly adds pc_cpuid to pc_other_cpus, causing the respective assertions in mp_machdep.c to be triggered when the latter is used as the base for the targets.
* | The ita_mask should include curcpu but the cpuset passed to cpu_ipi_selected()marius2011-05-111-3/+3
| | | | | | | | | | | | must not, otherwise we tell the CPU to IPI itself, which the sun4u CPUs don't support. For reasons unknown so far MD and MI IPI use actually still triggers that assertion though.
* | Update for the fact that pm_active and pc_cpumask were changed to cpuset_t.marius2011-05-112-11/+32
| | | | | | | | | | | | | | This now calculates pc_cpumask based on pc_cpuid itself as the former is slated for being deorbited. This branch now at least boots UP again. MP needs more things converted and the existing conversion from cpumask_t to cpuset_t still has bugs.
* | Fix an inversion in logic.attilio2011-05-101-1/+1
| | | | | | | | Submitted by: marius
* | - Fix a typoattilio2011-05-082-2/+2
| | | | | | | | - Fix an inversion in the logic
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