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path: root/sys/sparc64/sparc64/mp_exception.S
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* Don't waste a delay slot.marius2011-07-021-2/+2
* Fix a problem with r222813; given that we may only operate on interruptmarius2011-06-071-9/+11
* Update for the fact that the first members of the IPI args structures andmarius2011-05-121-11/+21
* - As it is not possible for sched_bind(9) to context switch withmarius2010-08-081-4/+28
* USIII and beyond CPUs have stricter requirements when it comesmarius2008-09-081-5/+7
* - USIII-based machines can consist of CPUs having different cachemarius2008-09-021-8/+5
* Convert the remainder of the low hanging fruits regarding includingmarius2007-01-191-1/+2
* - Rename the IPI_WAIT macro to IPI_DONE.jake2003-06-191-11/+8
* - Fix placement of cvs ids in previous commit to match .S files in libc.jake2003-04-291-3/+3
* I was wrong, the ENTRY bits in asm.h did have a purpose -- for userland.obrien2003-04-261-2/+3
* - Remove unused cache flushing routines. These will not necessary workjake2003-03-191-6/+39
* Use the meaningful mnemonics for ancillary state registers now that gasjake2002-12-291-1/+1
* Remove the tlb argument to tlb_page_demap (itlb or dtlb), in order to betterjake2002-07-261-10/+1
* Remove test code.jake2002-06-081-15/+0
* Add SMP aware cache flushing functions, which operate on a single physicaljake2002-05-201-0/+80
* Fix braino.jake2002-03-131-3/+0
* Make IPI_WAIT use a bit mask of the cpus that a pmap is active on and onlyjake2002-03-131-10/+18
* Implement delivery of tlb shootdown ipis. This is currently more fine grainedjake2002-03-071-53/+68
* Add initial smp support. This gets as far as allowing the secondaryjake2002-01-081-0/+169
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