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* - Current testing shows that (ab)using the JBC performance counter in busmarius2011-07-121-13/+10
| | | | | | | | cycle mode as timecounter just works fine. My best guess is that a firmware update has fixed this, check at run-time whether it advances and use a positive quality if it does. The latter will cause this timecounter to be used instead of the tick counter based one, which just sucks for SMP. - Remove a redundant NULL assignment from the timecounter initialization.
* - Add a missing shift in schizo_get_timecount(). This happened to be non-fatalmarius2011-07-121-3/+3
| | | | | | | as STX_CTRL_PERF_CNT_CNT0_SHIFT actually is zero, if we were using the second counter in the upper 32 bits this would be required though as the MI timecounter code doesn't support 64-bit counters/counter registers. - Remove a redundant NULL assignment from the timecounter initialization.
* Reimplement how PCI-PCI bridges manage their I/O windows. Previously thejhb2011-05-032-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | driver would verify that requests for child devices were confined to any existing I/O windows, but the driver relied on the firmware to initialize the windows and would never grow the windows for new requests. Now the driver actively manages the I/O windows. This is implemented by allocating a bus resource for each I/O window from the parent PCI bus and suballocating that resource to child devices. The suballocations are managed by creating an rman for each I/O window. The suballocated resources are mapped by passing the bus_activate_resource() call up to the parent PCI bus. Windows are grown when needed by using bus_adjust_resource() to adjust the resource allocated from the parent PCI bus. If the adjust request succeeds, the window is adjusted and the suballocation request for the child device is retried. When growing a window, the rman_first_free_region() and rman_last_free_region() routines are used to determine if the front or end of the existing I/O window is free. From using that, the smallest ranges that need to be added to either the front or back of the window are computed. The driver will first try to grow the window in whichever direction requires the smallest growth first followed by the other direction if that fails. Subtractive bridges will first attempt to satisfy requests for child resources from I/O windows (including attempts to grow the windows). If that fails, the request is passed up to the parent PCI bus directly however. The PCI-PCI bridge driver will try to use firmware-assigned ranges for child BARs first and only allocate a "fresh" range if that specific range cannot be accommodated in the I/O window. This allows systems where the firmware assigns resources during boot but later wipes the I/O windows (some ACPI BIOSen are known to do this) to "rediscover" the original I/O window ranges. The ACPI Host-PCI bridge driver has been adjusted to correctly honor hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge makes a wildcard request for an I/O window range. The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option is enabled. This is a transition aide to allow platforms that do not yet support bus_activate_resource() and bus_adjust_resource() in their Host-PCI bridge drivers (and possibly other drivers as needed) to use the old driver for now. Once all platforms support the new driver, the kernel option and old driver will be removed. PR: kern/143874 kern/149306 Tested by: mav
* Allocate memory for a DMA method table only in case we need to overridemarius2011-03-292-9/+18
| | | | | | | the iommu(4) provided one, i.e. in case of Hummingbird and Sabre bridges, otherwise just use the iommu(4) one. This also fixes a bug introduced in r220039 which caused an empty DMA method table to be used for the second of a pair of Psycho bridges.
* - A closer inspection of the OpenSolaris code indicates that the DMAmarius2011-03-262-158/+52
| | | | | | | | | | | syncing for Hummingbird and Sabre bridges should be applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around interrupt handlers for devices behind PCI-PCI bridges only as suggested by the documentation (code for the latter actually exists in OpenSolaris but is disabled by default), which also makes more sense. - Take advantage of the ofw_pci_setup_device method introduced in r220038 for disabling bus parking for certain EBus bridges in order to - Mark some unused parameters as such.
* - Merge the *_SET macros from fire(4) which generally print out themarius2011-03-266-257/+308
| | | | | | | | | | | | | | | | | | | | | | | | | register changes when compiled with SCHIZO_DEBUG and take advantage of them. - Add support for the XMITS Fireplane/Safari to PCI-X bridges. I tought I'd need this for a Sun Fire 3800, which then turned out to not being equipped with such a bridge though. The support for these should be complete but given that it hasn't actually been tested probing is disabled for now. This required a way to alter the XMITS configuration in case a PCI-X device is found further down the device tree so the sparc64 specific ofw_pci kobj was revived with a ofw_pci_setup_device method, which is called by the ofw_pcibus code for every device added. - A closer inspection of the OpenSolaris code indicates that consistent DMA flushing/syncing as well as the block store workaround should be applied with every BUS_DMASYNC_POSTREAD instead of in a wrapper around interrupt handlers for devices behind PCI-PCI bridges only as suggested by the documentation (code for the latter actually exists in OpenSolaris but is disabled by default), which also makes more sense. - Add a workaround for Casinni/Skyhawk combinations. Chances are that this solves the crashes seen when using the the on-board Casinni NICs of Sun Fire V480 equipped with centerplanes other than 501-6780 or 501-6790. This also takes advantage of the ofw_pci_setup_device method. - Mark some unused parameters as such.
* - Make a panic message better reflect the actual problem.marius2011-03-191-13/+15
| | | | | | - A closer inspection of the OpenSolaris code indicates the block store workaround is only necessary in case of BUS_DMASYNC_POSTREAD. - Mark some unused parameters as such.
* In case reading PCIR_MINGNT fails don't use it for calculating themarius2011-03-191-1/+1
| | | | | latency. This is more or less a theoretical problem though as it typically indicates way bigger problems.
* Sync licenses and the corresponding RCS IDs with NetBSD, mainly switchingmarius2011-03-123-6/+59
| | | | | | the licenses of Matthew R. Green and the TNF to 2-clause. Obtained from: NetBSD
* Resurrect ofw_pci_if.m from r178578.marius2011-02-211-0/+53
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* Fix typos - remove duplicate "the".brucec2011-02-211-1/+1
| | | | | | PR: bin/154928 Submitted by: Eitan Adler <lists at eitanadler.com> MFC after: 3 days
* Inherit the APB and the generic OFW PCI-PCI bridge driver from the genericmarius2011-01-042-38/+5
| | | | PCI-PCI bridge driver in order to safe some code.
* Reserve INTR_MD[1-4] similarly to what BUS_DMA_BUS[1-4] are intended formarius2011-01-043-3/+3
| | | | | | | | | and switch sparc64 to use the first one for bus error filter handlers of bridge drivers instead of (ab)using INTR_FAST for that so we eventually can get rid of the latter. Reviewed by: jhb MFC after: 1 month
* Convert drivers somehow missed in r200874 to multipass probing.marius2010-11-152-2/+4
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* Catch up to rename of the constant for the Master Data Parity Error bit injhb2010-09-091-1/+1
| | | | | | | the PCI status register. Pointed out by: mdf Pointy hat to: jhb
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-184-4/+4
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* - Enable DMA write parity error interrupts on Schizo with a workingmarius2010-05-143-41/+91
| | | | | | | | | | | | implementation. - Revert the Sun Fire V890 WAR of r205254. Instead let schizo_pci_bus() only panic in case of fatal errors as the interrupt triggered by the error the firmware of these and also Sun Fire 280R with version 7 Schizo caused may happen as late as using the HBA and not only prior to touching the PCI bus (in the former case the actual error still is fatal but we clear it before touching the PCI bus). While at it count and export non-fatal error interrupts via sysctl(9). - Remove unnecessary locking from schizo_ue().
* Add missing copyright shebang.marius2010-04-101-1/+1
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* Add sbbc(4), a driver for the BootBus controller found in Serengeti andmarius2010-04-101-0/+1074
| | | | | | | | | | StarCat systems which provides time-of-day services for both as well as console service for Serengeti, i.e. Sun Fire V1280. While the latter is described with a device type of serial in the OFW device tree, it isn't actually an UART. Nevertheless the console service is handled by uart(4) as this allowed to re-use quite a bit of MD and MI code. Actually, this idea is stolen from Linux which interfaces the sun4v hypervisor console with the Linux counterpart of uart(4).
* Use device_get_nameunit(9) rather than device_get_name(9) so one canmarius2010-03-312-5/+5
| | | | identify the reporting bridge in machines with multiple PCI domains.
* Don't re-implement device_get_nameunit(9).marius2010-03-311-14/+10
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* - Take advantage of the INTCLR_* macros.marius2010-03-312-18/+18
| | | | - Right-justify the backslashes as per style(9).
* - Add quirk handling for Sun Fire V1280. The firmware of these machinesmarius2010-03-172-5/+29
| | | | | | | | | | | | | | | | provides no ino-bitmap properties so forge them using the default set of controller interrupts and let schizo_setup_intr() take care of the children, hoping for non-fancy routing. - Add quirk handling for Sun Fire V890. When booting these machines from disk a Schizo comes up with PCI error residing which triggers as soon as we register schizo_pci_bus() even when clearing it from all involved registers (it's no longer indicated once we're in schizo_pci_bus() though). Thus make PCI bus errors non-fatal until we actually touch the bus. With this change schizo_pci_bus() typically triggers once during attach in this case. Obviously this approach isn't exactly race free but it's about the best we can do about this problem as we're not guaranteed that the interrupt will actually trigger on V890 either, as it certainly doesn't when for example netbooting them.
* - Zero the MSI/MSI-X queue argument, otherwise mtx_init(9) can panicmarius2010-01-271-3/+3
| | | | | | | | | | indicating an already initialized lock. - Check for an empty MSI/MSI-X queue entry before asserting that we have received a MSI/MSI-X message in order to not panic in case of stray MSI/ MSI-X queue interrupts which may happen in case of using an interrupt handler rather than a filter. MFC after: 3 days
* When setting up MSIs with a filter ensure that the event queue interruptmarius2010-01-101-2/+10
| | | | | is cleared as it might have triggered before and given we supply NULL as ic_clear, inthand_add() won't do this for us in this case.
* - According to OpenSolaris it's sufficient to align the MSIs of amarius2010-01-101-52/+95
| | | | | | | | | | | | | | | | | device in the table based on the count rather than the maxcount. Also the previous code didn't work properly as it would have been necessary to reserve the entire maxcount range in order keep later requests from filling the spare MSIs between count and maxcount, which would be complicated to unreserve in fire_release_msi(). - For MSIs with filters rather than handlers only don't clear the event queue interrupt via fire_intr_clear() since given that these are executed directly would clear it while we're still processing the event queue, which in turn would lead to lost MSIs. - Save one level of indentation in fire_setup_intr(). - Correct a bug in fire_teardown_intr() which prevented it from correctly restoring the MSI in the resource, causing allocation of a resource representing an MSI to fail after the first pass when repeatedly loading and unloading a driver module.
* - Preserve the PROM IOMMU in order to allow OFW drivers to continue tomarius2010-01-024-4/+25
| | | | | | | | work. - Sanity check the parameters passed to the implementations of the pcib_{read,write}_config() methods. Using illegal values can cause no real harm but it doesn't hurt to avoid unnecessary data error traps requiring to flush and re-enable the level 1 caches.
* - Remove a redundant variable and an unnecessary cast.marius2009-12-291-6/+5
| | | | - Fix whitespace.
* - Prefer i and j over i and n for temporary integer variables.marius2009-12-292-111/+120
| | | | | - Wrap/shorten too long lines. - Remove a redundant variable and an unnecessary cast in schizo(4).
* Account for firmware versions which include the CDMA interrupts inmarius2009-12-281-19/+32
| | | | | | the OFW device tree. MFC after: 3 days
* Add a driver for the `Fire' JBus to PCIe bridges found in at leastmarius2009-12-273-0/+3224
| | | | | | | | | | | | | | | | | | | | | | | | | the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also already includes all the code to support the `Oberon' Uranus to PCIe bridges found in the Fujitsu-Siemens based Mx000 machines but due to lack of access to such a system for testing, probing of these bridges is currently disabled. Unfortunately, the event queue mechanism of these bridges for MSIs/ MSI-Xs matches our current MD and MI interrupt frameworks like square pegs fit into round holes so for now we are generous and use one event queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge (we use one event queue for the PCIe error messages). This seems tolerable as long as most devices just use one MSI/MSI-X anyway. Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should allow us to decouple the 1:1 mapping at the cost of no longer being able to bind MSIs/MSI-Xs to specific CPUs as we currently have no reliable way to quiesce a device during the transition of its MSIs/ MSI-Xs to another event queue. This would still require the problem of interrupt storms generated by devices which have no one-shot behavior or can't/don't mask interrupts while the filter/handler is executed (like the older PCIe NICs supported by bge(4)) to be solved though. Committed from: 26C3
* - Hook up the default implementations of the MSI/MSI-X pcib_if methodsmarius2009-12-251-2/+39
| | | | | | | | | | | | | | | | | so requests may bubble up to a host-PCI bridge driver. - Distinguish between PCI and PCIe bridges in the device description so it's a bit easier to follow what hangs off of what in the dmesg. Unfortunately we can't also tell PCI and PCI-X apart based on the information provided in the OFW device tree. - Add quirk handling for the ALi M5249 found in Fire-based machines which are used as a PCIe-PCIe bridge there. These are obviously subtractive decoding as as they have a PCI-ISA bridge on their secondary side (and likewise don't include the ISA I/O range in their bridge decode) but don't indicate this via the class code. Given that this quirk isn't likely to apply to all ALi M5249 and I have no datasheet for these chips so I could implement a check using the chip specific bits enabling subtractive decoding this quirk handling is added to the MD code rather than the MI one.
* Merge from amd64/i386:marius2009-12-242-0/+28
| | | | Implement support for interrupt descriptions.
* - Add quirk handling for ALi M5229, mainly setting the magic "forcemarius2009-12-231-3/+24
| | | | | | | | enable IDE I/O" bit which prevents data access traps with revision 0xc8 in Fire-based machines when pci(4) enables PCIM_CMD_PORTEN. - Like for sun4v also don't add the PCI side of host-PCIe bridges to the bus on sun4u as they don't have configuration space implement there either.
* - Sort the prototypes.marius2009-12-231-24/+23
| | | | | - Add macros to ease the access of device configuration space in ofw_pcibus_setup_device().
* Add structures for OFW MSI/MSI-X support. These are identical formarius2009-12-231-0/+25
| | | | both sun4u and sun4v.
* Enroll these drivers in multipass probing. The motivation behind thismarius2009-12-223-3/+5
| | | | | | | | | is that the JBus to EBus bridges share the interrupt controller of a sibling JBus to PCIe bridge (at least as far as the OFW device tree is concerned, in reality they are part of the same chip) so we have to probe and attach the latter first. That happens to be also the case due to the fact that the JBus to PCIe bridges appear first in the OFW device tree but it doesn't hurt to ensure the right order.
* Provide and consume missing module dependency information.marius2009-12-212-0/+2
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* Factor out the duplicated macro for the device type used in themarius2009-09-133-6/+6
| | | | | | OFW device tree for PCI bridges and add a new one for PCI Express. While at it, take advantage of the former for the rman(9) work- around in jbusppm(4).
* Bring the implementation of the pnpinfo string function more inmarius2009-03-191-8/+6
| | | | line with the rest of this file.
* - Ensure we find no unexpected partner.marius2009-03-192-53/+60
| | | | | | | | | | | | | | | | | | | | | | | - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
* - Take advantage of KOBJMETHOD_END.marius2009-03-191-9/+13
| | | | | | | | | - Hook up the streaming buffer (not used by iommu(4) by default, yet) if available and usable. [1] - Move the message regarding belated registration as interrupt control under bootverbose as this isn't something the user should worry about. Tested by: Michael Moll [1]
* Take advantage of KOBJMETHOD_END.marius2009-03-191-1/+1
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* - Sort device methods.marius2009-03-192-4/+4
| | | | - Take advantage of KOBJMETHOD_END.
* - Failing to register as interrupt controller during attach shouldn'tmarius2008-12-181-10/+35
| | | | | | | | | | | | | | | | be fatal so just inform about this instead of panicing. - Ensure we use the right softc in case the interrupt of a child is is routed to the companion PBM instead. This hasn't been seen in the wild so far but given that it's the case for the Schizo interrupts, handling this situation also for child interrupts as a precaution seemed a good idea. - Deal with broken firmware versions which miss child entries in the ino-bitmap as seen on V880 by belatedly registering as interrupt controller in schizo_setup_intr(). [1] - Add missing '\n' when printing the warning regarding Schizo Errata I-13. Reported and tested by: Beat Gaetzi [1]
* Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,nwhitehorn2008-12-157-7/+19
| | | | | | | | | | | | | | | the code for parsing interrupt maps) to PowerPC and reflect their new MI status by moving them to the shared dev/ofw directory. This commit also modifies the OFW PCI enumeration procedure on PowerPC to allow the bus to find non-firmware-enumerated devices that Apple likes to add, and adds some useful Open Firmware properties (compat and name) to the pnpinfo string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the change to PCI enumeration on PowerPC, X has started working again on PPC machines with Grackle hostbridges. Reviewed by: marius Obtained from: sparc64
* - According to OpenSolaris, CDMA flushing/syncing for Tomatillosmarius2008-11-203-70/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and XMITS has to be basically done in the same manner as for the Sabres, i.e. only for devices behind PCI-PCI-bridges and after a PIO read on the far side of the farest PCI-PCI-bridge. Given that the Tomatillo documentation mentions no difference to the Schizo bridges in this regard and this is also still part of the procedure described Schizo documentation this seems about right so adjust accordingly (the unconditional CDMA flushing/syncing previously done was based on how Linux behaves). - Implement CDMA flushing/syncing for Schizo version >= 5, which requires the workaround described in Schizo Errata I-23. According to Schizo Errata I-13 it's just unusable with version < 5 though. [1] - Don't register the Schizo streaming buffer for now until it's usage is sorted out according to the erratas. - Register our interrupt filters with the revived INTR_FAST so they these interrupts can even interrupt filters of device drivers as necessary. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. Reported by: Michael Moll [1]
* - Turn off interrupts instead of only entering a critical sectionmarius2008-10-281-14/+10
| | | | | | | | | | | | | | | | | | | | | | while doing the block store workaround so we restore the correct floating-point registers state in case of nested floating-point operations resulting from nested interrupts. This allows the VIS-based block copy/zero functions to be used on machines requiring this workaround. Alternatively, we could take care of saving the floating-point registers here, which would be more inefficiently though and also involves turning off interrupts. - It turns out that the SCZ_PCI_DMA_SYNC register doesn't work like the TOMXMS_PCI_DMA_SYNC_PEND one (but more like the corresponding register in of Hummingbird and Sabre bridges) and writing the INO of the respective device to it causes a Safari bus error. However, due to the Schizo errata I-23, SCZ_PCI_DMA_SYNC can't be used as intended either, so remove consistent DMA syncing for Schzio bridges for now, which means that add-on cards with non-"sun4u compliant" (whatever that means exactly) PCI-PCI-bridges should be avoided until the proper workaround is implemented. [1] Reported by: Michael Moll [1]
* Add a driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo'marius2008-09-283-0/+1649
| | | | | | JBus to PCI 2.2 bridges. In theory, this driver should also handle `XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access to such hardware, support for these hasn't be fleshed out, yet.
* Clear any possibly pending PCI error bits left by the firmware. Thesemarius2008-09-182-64/+56
| | | | | | | could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
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