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* - Ensure we find no unexpected partner.marius2009-03-192-53/+60
| | | | | | | | | | | | | | | | | | | | | | | - Failing to register as interrupt controller during attach shouldn't be fatal so just inform about this instead of panicing. - Disable rerun of the streaming cache as workaround for a silicon bug of certain Psycho versions. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. - Don't panic if the power failure, power management or over-temperature interrupts doesn't exist as these aren't mandatory and not available with all controllers (not even Psychos). [1] - Take advantage of KOBJMETHOD_END. - Remove some redundant variables. - Add missing const. PR: 131371 [1]
* - Take advantage of KOBJMETHOD_END.marius2009-03-191-9/+13
| | | | | | | | | - Hook up the streaming buffer (not used by iommu(4) by default, yet) if available and usable. [1] - Move the message regarding belated registration as interrupt control under bootverbose as this isn't something the user should worry about. Tested by: Michael Moll [1]
* Take advantage of KOBJMETHOD_END.marius2009-03-191-1/+1
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* - Sort device methods.marius2009-03-192-4/+4
| | | | - Take advantage of KOBJMETHOD_END.
* - Failing to register as interrupt controller during attach shouldn'tmarius2008-12-181-10/+35
| | | | | | | | | | | | | | | | be fatal so just inform about this instead of panicing. - Ensure we use the right softc in case the interrupt of a child is is routed to the companion PBM instead. This hasn't been seen in the wild so far but given that it's the case for the Schizo interrupts, handling this situation also for child interrupts as a precaution seemed a good idea. - Deal with broken firmware versions which miss child entries in the ino-bitmap as seen on V880 by belatedly registering as interrupt controller in schizo_setup_intr(). [1] - Add missing '\n' when printing the warning regarding Schizo Errata I-13. Reported and tested by: Beat Gaetzi [1]
* Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,nwhitehorn2008-12-157-7/+19
| | | | | | | | | | | | | | | the code for parsing interrupt maps) to PowerPC and reflect their new MI status by moving them to the shared dev/ofw directory. This commit also modifies the OFW PCI enumeration procedure on PowerPC to allow the bus to find non-firmware-enumerated devices that Apple likes to add, and adds some useful Open Firmware properties (compat and name) to the pnpinfo string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the change to PCI enumeration on PowerPC, X has started working again on PPC machines with Grackle hostbridges. Reviewed by: marius Obtained from: sparc64
* - According to OpenSolaris, CDMA flushing/syncing for Tomatillosmarius2008-11-203-70/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and XMITS has to be basically done in the same manner as for the Sabres, i.e. only for devices behind PCI-PCI-bridges and after a PIO read on the far side of the farest PCI-PCI-bridge. Given that the Tomatillo documentation mentions no difference to the Schizo bridges in this regard and this is also still part of the procedure described Schizo documentation this seems about right so adjust accordingly (the unconditional CDMA flushing/syncing previously done was based on how Linux behaves). - Implement CDMA flushing/syncing for Schizo version >= 5, which requires the workaround described in Schizo Errata I-23. According to Schizo Errata I-13 it's just unusable with version < 5 though. [1] - Don't register the Schizo streaming buffer for now until it's usage is sorted out according to the erratas. - Register our interrupt filters with the revived INTR_FAST so they these interrupts can even interrupt filters of device drivers as necessary. - Remove the comment regarding lack of newbus'ified bus_dma(9) as being able to associate a DMA tag with a device would allow to implement CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally kill performance. Given that for devices not behind a PCI-PCI bridge the host-to-PCI bridges also only do CDMA flushing/syncing based on interrupts there's no additional disadvantage for polling(4) callbacks in the case schizo(4) has to do the CDMA flushing/syncing but rather a general problem. Reported by: Michael Moll [1]
* - Turn off interrupts instead of only entering a critical sectionmarius2008-10-281-14/+10
| | | | | | | | | | | | | | | | | | | | | | while doing the block store workaround so we restore the correct floating-point registers state in case of nested floating-point operations resulting from nested interrupts. This allows the VIS-based block copy/zero functions to be used on machines requiring this workaround. Alternatively, we could take care of saving the floating-point registers here, which would be more inefficiently though and also involves turning off interrupts. - It turns out that the SCZ_PCI_DMA_SYNC register doesn't work like the TOMXMS_PCI_DMA_SYNC_PEND one (but more like the corresponding register in of Hummingbird and Sabre bridges) and writing the INO of the respective device to it causes a Safari bus error. However, due to the Schizo errata I-23, SCZ_PCI_DMA_SYNC can't be used as intended either, so remove consistent DMA syncing for Schzio bridges for now, which means that add-on cards with non-"sun4u compliant" (whatever that means exactly) PCI-PCI-bridges should be avoided until the proper workaround is implemented. [1] Reported by: Michael Moll [1]
* Add a driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo'marius2008-09-283-0/+1649
| | | | | | JBus to PCI 2.2 bridges. In theory, this driver should also handle `XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access to such hardware, support for these hasn't be fleshed out, yet.
* Clear any possibly pending PCI error bits left by the firmware. Thesemarius2008-09-182-64/+56
| | | | | | | could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
* Announce the speed of the PCI bus for informational purpose.marius2008-08-241-3/+6
| | | | MFC after: 3 days
* The PCI specifications don't explain the details on how to calculatemarius2008-08-241-20/+58
| | | | | | | | | | | | | | the latency based on the Min_Gnt register so use the algorithm found in OpenSolaris as they probably know how to interpret the value Sun puts into these registers (previously, the latency calculated for 66MHz was most likely wrong) and for bridges additionally set up the secondary latency register. Also set up the bridge control register the way it's done in OpenSolaris. As the latency register don't apply to PCI-Express and the bridge control setup wasn't tested on sun4v (besides most likely not being needed), expand the #ifndef SUN4V accordingly. MFC after: 3 days
* cosmetic changes and style fixesmarius2008-08-223-24/+31
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* - Use the name returned by device_get_nameunit(9) for the name of themarius2008-05-071-25/+19
| | | | | | | | | | | | counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
* Remove an header which is unused for sun4v.marius2008-05-021-1/+3
| | | | MFC after: 3 days
* Remove the MD isa_irq_pending() and the underlying PCI-specificmarius2008-04-263-74/+0
| | | | | | | | | infrastructure. Its only consumer ever was sio(4) and thus was unused on sparc64 since removing the last traces of sio(4) in sparc64 configuration files in favor for uart(4) over three years ago. If similar functionality is required again it should be brought back as an MD intr_pending() which works for all busses by using for example interrupt controller hooks.
* o Rename ic_eoi to ic_clear to emphasize the functions it pointsmarius2008-04-231-3/+15
| | | | | | | | | | | | | | | | | | | don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
* On sparc64 machines with multiple host-PCI-bridges these bridgesmarius2008-04-178-149/+21
| | | | | | | | | | | | | | | | | have separate configuration spaces so by definition they implement different PCI domains. Thus change psycho(4) to use PCI domains instead of reenumerating all PCI busses so they have globally unique bus numbers and drop support for reenumerating busses in the OFW PCI code. According to CVS history reenumeration was also required in order to get some E450 to boot but given that no other open source kernel changes the PCI bus numbers assigned by the firmware I believe the real problem was that the old code used the bus number as the device number for the PCI busses and unlike most of the other machines the firmwares of the problematic ones don't use disjoint PCI bus numbers across the host-PCI-bridges. MFC after: 1 month
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-251-1/+1
| | | | | | | | | for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run. Assign approximate why values to all current consumers of the kdb_enter() interface.
* Fix a non-fatal off-by-one error in the previous revision.marius2007-12-011-1/+1
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* - Add the PCI side of the HOST-PCI bridge itself to the bus. Thismarius2007-11-303-14/+76
| | | | | | | | | | | is required by the X.Org PCI domains code and additionally needs a workaround for Hummingbird and Sabre bridges as these don't allow their config headers to be read at any width, which is an unusual behavior. - In psycho(4) take advantage of DEFINE_CLASS_0 and use more appropriate types for some softc members. MFC after: 3 days
* Make the PCI code aware of PCI domains (aka PCI segments) so we canmarius2007-09-303-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | support machines having multiple independently numbered PCI domains and don't support reenumeration without ambiguity amongst the devices as seen by the OS and represented by PCI location strings. This includes introducing a function pci_find_dbsf(9) which works like pci_find_bsf(9) but additionally takes a domain number argument and limiting pci_find_bsf(9) to only search devices in domain 0 (the only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order to no longer report false positives when searching for siblings and dupe devices in the same domain respectively. Along with this change the sole host-PCI bridge driver converted to actually make use of PCI domain support is uninorth(4), the others continue to use domain 0 only for now and need to be converted as appropriate later on. Note that this means that the format of the location strings as used by pciconf(8) has been changed and that consumers of <sys/pciio.h> potentially need to be recompiled. Suggested by: jhb Reviewed by: grehan, jhb, marcel Approved by: re (kensmith), jhb (PCI maintainer hat)
* - Use the actual clock frequency of the PCI bus instead of assumingmarius2007-09-261-17/+16
| | | | | | | | | | | | | | | | | | 33MHz for calculating the latency timer values for its children. Inspired by NetBSD doing the same and Linux as well as OpenSolaris using a similar approach. While at it rename a variable and change its type to be more appropriate fuer values of PCI properties so the variable can be more easily reused. - Initialize the cache line size register of PCI devices to a legal value; the cache line size is limited to 64 bytes by the Fireplane/Safari, JBus and UPA interconnection busses. Setting it to an unsupported value caused bad performance at least with GEM as it causes them to not do cache line bursts and to not issue cache line commands on the PCI bus. Approved by: re (kensmith) MFC after: 1 week
* o Revamp the sparc64 interrupt code in order to be able to interfacemarius2007-09-062-172/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
* - Divorce the IOTSBs, which so far where handled via a global listmarius2007-08-052-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead of per IOMMU, so we no longer need to program all of them identically in systems having multiple IOMMUs. This continues the rototilling of the nexus(4) done about 5 months ago, which amongst others changed nexus(4) and the drivers for host-to-foo bridges to provide bus_get_dma_tag methods, allowing to handle DMA tags in a hierarchical way and to link them with devices. This still doesn't move the silicon bug workarounds for Sabre (and in the uncommitted schizo(4) for Tomatillo) bridges into special bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy() this still requires too much hackery, i.e. per-child parent DMA tags in the parent driver. - Let the host-to-foo drivers supply the maximum physical address of the IOMMU accompanying the bridges. Previously iommu(4) hard- coded an upper limit of 16GB, which actually only applies to the IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants as well as the U2S in fact can can translate to up to 2TB, i.e. translate to 41-bit physical addresses. According to the recently available Tomatillo documentation these bridges even translate to 43-bit physical addresses and hints at the Schizo bridges doing 43 bits as well. This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on sparc64" was refering to and pretty much obsoletes the lack of support for bounce buffers on sparc64. Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual. Approved by: re (kensmith)
* - Move ofw_pci_alloc_busno() to the ofw_pci KOBJ interface,marius2007-06-185-97/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | allowing the driver for the host-PCI-bridge to indicate that reenumeration of the PCI busses isn't supported by returning -1 instead of a valid PCI bus number. This is needed in order support both Tomatillo, which don't support reenumeration and thus are apparently intended to be used for independently numbered PCI domains only, and Psycho bridges, whose busses need to be reenumerated on at least some E450, without the #ifndef currently used for sun4v in order to support multiple independently PCI domains. The actual allocation/incrementation of the PCI bus numbers is now done in psycho(4), though it no longer establish a mapping between bus numbers and device nodes like ofw_pci_alloc_busno() did as that functionality wasn't used (but can easily brought back if really needed). The now no longer used sys/sparc64/pci/ofw_pci.c is also removed from sys/conf/files.sun4v as ofw_pci_alloc_busno() wasn't used there in the first place. - In ofw_pci_default_{adjust_busrange,intr_pending}() sanity check that the device has a parent before passing it on. - Make psycho_softcs static to sys/sparc64/pci/psycho.c as it's not used outside of that module. - In sys/sparc64/pci/ofw_pcib_subr.c remove the superfluous inclusion of opt_global.h and correct the debug output for adjusting the subordinate bus number.
* For sun4u also add PCI busses with a device unit number of -1marius2007-06-181-8/+1
| | | | | | | | | | | instead of using the PCI bus number, like it's already done for sun4v in order to deal properly with independently numbered PCI domains which can't be reenumerated (in the case of sun4u f.e. Tomatillo bridges). For machines where we need to reenumerate all PCI busses this change obviously introduces the theoretical cosmetic problem that the device number of the PCI bus no longer equals to its PCI bus number. In practice this doesn't happen as both are assigned linearly and in parallel.
* Remove unused softc.marius2007-06-171-6/+2
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* - Use the newly introduced pcib_mtx spin lock to lock psycho_ce(),marius2007-06-162-60/+54
| | | | | | | | | | | | | | | | | allowing it to be a filter/"fast" handler. Locking the interrupt handlers with a spin lock is mainly a requirement in schizo(4) but as we ought to register the spin lock anyway it should not hurt to take advantage of it in psycho(4). - Pass both a driver_filter_t and a driver_intr_t argument to psycho_set_intr(), allowing to get rid of the FAST interrupt flag hack. - Don't register the over-temperature interrupt handler as filter/ "fast" handler so shutdown_nice() can acquire the process lock. - Use bus_{read,write}_8() instead of bus_space_{read,write}_8() in order to get rid of sc_bushandle and sc_bustag in the softc. - Correct the debug output for adjusting the subordinate bus number. - Remove the banal and outdated above psycho_filter_stub(). - Fix some white space nits.
* Teach the bridge wrapper how to handle the filter+ithread case.piso2007-06-061-11/+24
| | | | Reviewed by: marius
* Delete the unused/not really used sparc64 (as in sun4u) cache.h,marius2007-05-201-2/+2
| | | | | | iommureg.h (which already began to bitrot) and iommuvar.h from the sun4v source and adjust some of the source which is shared between sparc64 and sun4v as appropriate.
* Rototill the sparc64 nexus(4) (actually this brings in the code themarius2007-03-072-87/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sun4v nexus(4) in turn is based on): o Change nexus(4) to manage the resources of its children so the respective device drivers don't need to figure them out of OFW themselves. o Change nexus(4) to provide the ofw_bus KOBJ interface instead of using IVARs for supplying the OFW node and the subset of standard properties of its children. Together with the previous change this also allows to fully take advantage of newbus in that drivers like fhc(4), which attach on multiple parent busses, no longer require different bus front-ends as obtaining the OFW node and properties as well as resource allocation works the same for all supported busses. As such this change also is part 4/4 of allowing creator(4) to work in USIII-based machines as it allows this driver to attach on both nexus(4) and upa(4). On the other hand removing these IVARs breaks API compatibility with the powerpc nexus(4) but which isn't that bad as a) sparc64 currently doesn't share any device driver hanging off of nexus(4) with powerpc and b) they were no longer compatible regarding OFW-related extensions at the pci(4) level since quite some time. o Provide bus_get_dma_tag methods in nexus(4) and its children in order to handle DMA tags in a hierarchical way and get rid of the sparc64_root_dma_tag kludge. Together with the previous two items this changes also allows to completely get rid of the nexus(4) IVAR interface. It also includes: - pushing the constraints previously specified by the nexus_dmatag down into the DMA tags of psycho(4) and sbus(4) as it's their IOMMUs which induce these restrictions (and nothing at the nexus(4) or anything that would warrant specifying them there), - fixing some obviously wrong constraints of the psycho(4) and sbus(4) DMA tags, which happened to not actually be used with the sparc64_root_dma_tag kludge in place and therefore didn't cause problems so far, - replacing magic constants for constraints with macros as far as it is obvious as to where they come from. This doesn't include taking advantage of the newbus way to get the parent DMA tags implemented by this change in order to divorce the IOTSBs of the PCI and SBus IOMMUs or for implementing the workaround for the DMA sync bug in Sabre (and Tomatillo) bridges, yet, though. o Get rid of the notion that nexus(4) (mostly) reflects an UPA bus by replacing ofw_upa.h and with ofw_nexus.h (which was repo-copied from ofw_upa.h) and renaming its content, which actually applies to all of Fireplane/Safari, JBus and UPA (in the host bus case), as appropriate. o Just use M_DEVBUF instead of a separate M_NEXUS malloc type for allocating the device info for the children of nexus(4). This is done in order to not need to export M_NEXUS when deriving drivers for subordinate busses from the nexus(4) class. o Use the DEFINE_CLASS_0() macro to declare the nexus(4) driver so we can derive subclasses from it. o Const'ify the nexus_excl_name and nexus_excl_type arrays as well as add 'associations' and 'rsc', which are pseudo-devices without resources and therefore of no real interest for nexus(4), to the former. o Let the nexus(4) device memory rman manage the entire 64-bit address space instead of just the UPA_MEMSTART to UPA_MEMEND subregion as Fireplane/Safari- and JBus-based machines use multiple ranges, which can't be as easily divided as in the case of UPA (limiting the address space only served for sanity checking anyway). o Use M_WAITOK instead of M_NOWAIT when allocating the device info for children of nexus(4) in order to give one less opportunity for adding devices to nexus(4) to fail. o While adapting the drivers affected by the above nexus(4) changes, change them to take advantage of rman_get_rid() instead of caching the RIDs assigned to allocated resources, now that the RIDs of resources are correctly set. o In iommu(4) and nexus(4) replace hard-coded functions names, which actually became outdated in several places, in panic strings and status massages with __func__. [1] o Use driver_filter_t in prototypes where appropriate. o Add my copyright to creator(4), fhc(4), nexus(4), psycho(4) and sbus(4) as I changed considerable amounts of these drivers as well as added a bunch of new features, workarounds for silicon bugs etc. o Fix some white space nits. Due to lack of access to Exx00 hardware, these changes, i.e. central(4) and fhc(4), couldn't be runtime tested on such a machine. Exx00 are currently reported to panic before trying to attach nexus(4) anyway though. PR: 76052 [1] Approved by: re (kensmith)
* o break newbus api: add a new argument of type driver_filter_t topiso2007-02-231-29/+58
| | | | | | | | | | | | | bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
* Remove the compat shims for the ISA old-stlye in{b,w,l}()/out{b,w,l}()marius2007-01-182-42/+0
| | | | | | | | | | | | | | | | and friends along with all hacks required to implement them. None of the drivers currently built (as part of GENERIC, LINT or modules) on sparc64 or sun4v and none of those we might want to use there in future uses them, AFAICT there actually never was a driver hooked up to the sparc64 or sun4v build that correctly used these functions (and it looks like that due to a bug read{b,w,l}()/write{b,w,l}() and the other functions working on a memory handle never actually worked on sun4v). All they ever were good for on sparc64 and sun4v was erroneously dragging in dependencies on isa(4) in drivers like f.e. dpt(4), si(4) and syscons(4) in source files that supposedly were bus-neutral and hiding issues with drivers like f.e. ng_bt3c(4) that used these functions with busses other than isa(4) and therefore couldn't work on these platforms.
* o Changes to psycho_attach(): [1]marius2007-01-082-64/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Clear the PCI AFSR and status error bits as previous errors still might be indicated. - Set up the PCI control and diagnostic registers according to the capabilities, workarounds, etc of/for specific revisions of the supported bridges. This includes no longer setting Hummingbird-/ Sabre-specific bits in the PCI control register but preserving what the firmware has initialized them to like OpenSolaris does. Previously we were setting these bits according to the example in the Sabre documentation, which I doubt is appropriate for all Sabre based designs and especially not for Hummingbirds. This also includes not enabling bus parking unless the firmware tells us to. - Set the PCI latency timer register as this isn't always done by the firmware. o Remove a redundant argument from psycho_set_intr() and in this function check the return value of bus_setup_intr(). [2] o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't allocate memory for the interrupt wrapper stub and EINVAL instead of 0 if it can't find the interrupt vector in the interrupt map. o Add a workaround for a bug of the Sabre-APB-combination where it doesn't drain DMA write data for devices behind additional PCI-PCI bridges underneath the APB PCI-PCI bridge. This workaround (do things necessary in order to achieve a manual drain when coherency is required) is currently implemented in psycho_setup_intr() and psycho_intr_stub() (for easy MFC'ing) and therefore is only applied for interrupt handlers. This should be moved to psycho(4)-specific bus_dma_tag_create() and bus_dmamap_sync() methods, respectively, once this driver is converted to make use of BUS_GET_DMA_TAG(), so the workaround is also applied for polling(4) callbacks. [3] o Fix some minor style issues. Info from: OpenSolaris [1] Info from: Linux, OpenBSD, OpenSolaris [3] Suggested by: Coverity Prevent (CID 682) [2] MFC after: 1 month
* In ofw_pcibus_attach() skip dupe PCI devices reported by themarius2007-01-081-0/+2
| | | | | | | | | | | | | | | | | | firmware (mainly 'pmu' and its 'lomp' dupe found in a couple of later USII{e,i}-based machines) by checking whether a device with the same triple of bus number, slot and function already has been added. This is the simple yet effective approach introduced in OpenBSD some time ago, but which has the flaw that it assumes that the device and its dupe(s) found in the OFW device tree are equal or at least the one encountered first is in some way the more important one (this is the case with 'pmu' and 'lomp'; the 'pmu' node has couple of properties and children while the 'lomp' one misses most of these). If there's ever a device/dupe pair where we don't encounter the more important node first, we'll probably need to introduce a quirk list in order to add the desired device but prevent its dupe(s) from being added. MFC after: 1 week
* The T2000 has multiple PCI domains requiring bus allocation to be done ↵kmacy2006-10-122-0/+11
| | | | | | | | differently. This pulls in changes by jmg from perforce and makes them sun4v only for now. Approved by: scottl (acting as backup for mentor rwatson)
* kernel clean up to make the sun4v kernel buildkmacy2006-10-091-2/+8
| | | | | Reviewed by: jmg Approved by: rwatson (mentor)
* Set the rid for any resource obtained from rman_reserve_resource.imp2006-04-201-1/+1
| | | | Reviewed by: wollman, jmg (as were the other commits fixing this problem)
* - Register the generic implementations for the device shutdown, suspendmarius2006-01-261-0/+3
| | | | | | | | | | | | | | and resume methods so these events propagate through the device driver hierarchy. - In dma(4) enable the chaining of the DMA engine interrupt handler for the LANCE devices via a dma_setup_intr(). This was commented out before as I was unsure whether I'd use it but this is probably cleaner than fiddling with the DMA engine interrupt in the LANCE driver directly. - In ebus_setup_dinfo() free 'intrs' instead of 'reg' twice in case setting up a child fails due to routing one of its interrupts fails. [1] Found by: Coverity Prevent [1] MFC after: 3 days
* Make the ACPI and OpenFirmware PCI bus drivers subclasses of the genericjhb2006-01-201-35/+3
| | | | PCI bus driver.
* - Make pcib_devclass private to sys/dev/pci/pci_pci.c and change all thejhb2006-01-062-10/+5
| | | | | | | various pcib drivers to use their own private devclass_t variables for their modules. - Use the DEFINE_CLASS_0() macro to declare drivers for the various pcib drivers while I'm here.
* Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is usedjhb2005-12-201-0/+1
| | | | | | | to search for a specific extended capability. If the specified capability is found for the given device, then the function returns success and optionally returns the offset of that capability. If the capability is not found, the function returns an error.
* Fix a bug introduced in rev. 1.5; for retrieving the device_t of themarius2005-12-121-2/+2
| | | | parent bridge of a PCI-PCI bridge we need two device_get_parent().
* - Move the declaration of struct upa_ranges and the UPA_RANGE_* macrosmarius2005-12-032-16/+34
| | | | | | | | | | | | from sys/sparc64/include/ofw_upa.h to sys/sparc64/pci/ofw_pci.h and rename them to struct ofw_pci_ranges and OFW_PCI_RANGE_* respectively. This ranges struct only applies to host-PCI bridges but no to other bridges found on UPA. At the same time it applies to all host-PCI bridges regardless of whether the interconnection bus is Fireplane/ Safari, JBus or UPA. - While here rename the PCI_CS_* macros in sys/sparc64/pci/ofw_pci.h to OFW_PCI_CS_* in order to be consistent and change this header to use uintXX_t instead of u_intXX_t.
* - Adhere style(9) (don't use function calls in initializers).marius2005-12-031-3/+5
| | | | - Use FBSDID.
* - Adhere style(9) (don't use function calls in initializers, use uintXX_tmarius2005-12-034-25/+35
| | | | | instead of u_intXX_t). - Use FBSDID.
* - Register the PCI bus error interrupt handler according to which half ofmarius2005-12-031-26/+36
| | | | | | | | | | | | | | | | | | the bridge (PCI bus A or B) we are attaching to rather than registering both handlers at once when attaching to the first half we encounter. This is a bit cleaner as it corresponds to which PCI bus error interrupt actually is assigned to the respective half by the OFW and allows to collapse both PCI bus error interrupt handlers into one function easily. - Use the actual RID of the respective interrupt resource as index into sc_irq_res and also use it when allocating the resource. For now this is a bit cleaner and will be mandatory later on. - According to OpenSolaris the spare hardware interrupt is used as the over-temperature interrupt in systems with Psycho bridges. Unlike as with the SBus-based workstations I didn't manage to trigger it when covering the fan outlets of an U60 but better be safe than sorry and register a handler anyway. MFC after: 1 month
* - Improve the comment regarding the workaround for the E250 interrupt mapmarius2005-12-032-17/+31
| | | | | | | | | bug by explaining what the problem is and how the workaround works. - Fix some cosmetics nits, mainly properly terminate sentences in comments, which I missed when backporting the style changes to psycho(4) in psycho.c rev. 1.54 due to lack of corresponding code. - The "USIIe version of the Sabre bridge" actually is termed "Hummingbird"; name it as such in comments and messages.
* - Add a workaround (change the interrupt map mask to compare the fullmarius2005-11-222-29/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | INO) for incorrect interrupt map entries on E250 machines. These incorrect entries caused the INO of the on-board HME to be also assigned to the second on-board NS16550 and to the on-board printer port controller. Further down the road caused hme(4) to fail to attach to the on-board HME in FreeBSD 5 and 6 as INTR_FAST and non-INTR_FAST handlers can't share the same IRQ there (it's unknown what whould happen in -CURRENT now that INTR_FAST and non-INTR_FAST handlers can share an IRQ but I'd expect funny problems with uart(4)). - Make sure there are exactly 4 PCI ranges instead of just checking that the bridge has a 'ranges' property in the OFW device tree at all. Besides the fact that currently the 64bit memory range isn't used by this driver it we can't really work with less than 4 ranges and don't have memory for more than 4 bus handles for the ranges in the softc. - Remove sc_range and sc_nrange from softc; for the bridges supported by this driver we no longer need to know the ranges besides the bus handles obtained from them once this driver is attached. That way we also can free the memory allocated for sc_range during attach again. - Remove sc_dvmabase from the softc and pass it to psycho_iommu_init() via an additional argument as we no longer need to know the DVMA base in this driver once the IOMMU is initialized. - Remove sc_dmatag from the softc, there isn't much sense in keeping the nexus dma tag around locally. PR: 88279 [1] Info from: OpenSolaris [1] Tested by: kensmith [1] MFC after: 1 month
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