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path: root/sys/sparc64/include/smp.h
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* Revert the part of r239864 which removed obtaining the SMP mutex aroundmarius2013-01-231-18/+2
* - Unlike cache invalidation and TLB demapping IPIs, reading registers frommarius2012-08-291-9/+25
* Don't include curcpu in the mask which is used as the IPI cookie as wemarius2011-06-151-12/+16
* The ita_mask should include curcpu but the cpuset passed to cpu_ipi_selected()marius2011-05-111-3/+3
* Add sparc64 support.attilio2011-05-061-18/+29
* Refactor timer management code with priority to one-shot operation mode.mav2010-09-131-1/+0
* Update various places that store or manipulate CPU masks to use cpumask_tjhb2010-08-111-7/+7
* - As it is not possible for sched_bind(9) to context switch withmarius2010-08-081-0/+33
* - Introduce a cpu_ipi_single() function pointer in order to send IPIsmarius2010-08-081-6/+5
* Add a new ipi_cpu() function to the MI IPI API that can be used to send anjhb2010-08-061-0/+11
* Adapt sparc64 and sun4v timer code for the new event timers infrastructure.mav2010-07-291-0/+2
* - Pin the IPI cache and TLB demap functions in order to prevent migrationmarius2010-07-041-8/+24
* Some machines can not only consist of CPUs running at different speedsmarius2010-02-201-1/+1
* * Completely Remove the option STOP_NMI from the kernel. This optionattilio2009-08-131-0/+1
* - Newer firmware versions no longer provide SUNW,stop-self so justmarius2008-09-181-6/+38
* - USIII-based machines can consist of CPUs running at differentmarius2008-09-031-3/+5
* - Add support for IPI_PREEMPT. [1]marius2008-04-091-0/+1
* - Add support for sending IPIs with USIII and greater sun4u CPUs.marius2007-06-161-5/+10
* - Staticize cpu_ipi_send() and cpu_mp_unleash() as these aren'tmarius2007-05-201-1/+8
* Include machine/pcb.hto turn extern struct pcb stoppcbs[]; constructkan2007-05-191-0/+1
* Add stoppcbs[] arrays on Alpha and sparc64 and have each CPU save itsjhb2005-11-031-0/+2
* Declare as volatile the memory location referenced by a pointer rather thanalc2005-03-061-1/+1
* We seem to have occasions where sending an IPI takes significantlykensmith2004-09-291-1/+1
* Use vm_paddr_t for physical addresses.jake2003-04-081-5/+5
* - Remove unused cache flushing routines. These will not necessary workjake2003-03-191-10/+10
* - Add a spin lock to single thread cache invalidation and tlb flush ipis,jake2002-12-221-6/+12
* Remove the tlb argument to tlb_page_demap (itlb or dtlb), in order to betterjake2002-07-261-4/+2
* When sending cache flushing IPIs, don't try to IPI the triggering CPUtmm2002-07-121-4/+4
* Remove test code.jake2002-06-081-1/+0
* Add SMP aware cache flushing functions, which operate on a single physicaljake2002-05-201-0/+50
* Make IPI_WAIT use a bit mask of the cpus that a pmap is active on and onlyjake2002-03-131-18/+12
* Implement delivery of tlb shootdown ipis. This is currently more fine grainedjake2002-03-071-24/+37
* Add support for starting secondary cpus in kernel, as opposed to relyingjake2002-03-041-10/+18
* Include intr_machdep.h only for !LOCORE.jake2002-02-231-2/+2
* Add extern to avoid sloppy common style declarations.jake2002-01-161-2/+2
* Add initial smp support. This gets as far as allowing the secondaryjake2002-01-081-0/+156
* The author isn't a [UC] Regents. Correct the copyright language.obrien2001-08-091-2/+2
* Add skeleton machine dependent headers and c files for a port of freebsdjake2001-07-311-0/+32
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