FreeBSD-src - Raptor Engineering's fork of pfsense FreeBSD src with pfSense changes

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix a bug in the data access error recorvery. Before re-enabling the data	jake	2003-11-11	1	-0/+9
\| \| \| \| \| \| \| \| \| \| \| \|	cache after a data access error we must discard all cache lines. When disabled existing cache lines are not invalidated by stores to memory, so we risk reading stale data that was cached before the data access error if we don't flush them. This is especially fatal when the memory involved is the active part of the kernel or user stack. For good measure we also flush the instruction cache. This fixes random crashes when the X server probes the PCI bus through /dev/pci.
*	Avoid exposing declarations for kernel variables to userland.	jake	2003-07-17	1	-0/+4
\| \| \| \|	PR: 54528
*	Use vm_paddr_t for physical addresses.	jake	2003-04-08	1	-6/+6
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*	- Remove unused cache flushing routines. These will not necessary work	jake	2003-03-19	1	-57/+19
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	on future UltraSPARC cpus for which the data cache is not direct mapped. - Move UltraSPARC I and II (spitfire, blackbird, sapphire, sabre) specific functions to spitfire.c, and add cheetah.c for UltraSPARC III specific functions. Initially just cache flushing, but there are a few other functions that will need to move here. - Add an ipi handler for data cache flushing on UltraSPARC III. - Use function pointers to select the right cache flushing functions based on cpu_impl. With this it is possible to boot single user from an mfs root on UltraSPARC III systems, including spinning up secondary processors. There is currently no support for the host to pci bridge, and no documentation for it is publically available. Thanks to Oleg Derevenetz for providing access to a system with UltraSPARC III+ cpus.
*	Add SMP aware cache flushing functions, which operate on a single physical	jake	2002-05-20	1	-15/+38
\| \| \| \| \|	page. These send IPIs if necessary in order to keep the caches in sync on all cpus.
*	Remove __P.	alfred	2002-03-21	1	-9/+9
\| \| \| \| \| \|	profile.h and bus.h were excluded because there is currently WIP. Reviewed by: tmm
*	Use stxa_sync() when accessing the diagnostic registers to invalidate	tmm	2002-02-13	1	-1/+2
\| \| \| \| \|	caches; this is needed to avoid undefined behaviour. Clean up a bit.
*	Prototype dcache_inval_phys.	jake	2001-12-29	1	-0/+1
\| \| \| \|	Submitted by: tmm
*	Add cache handling code for sparc64.	tmm	2001-11-09	1	-0/+126