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* Add the implementation of atomic_swap_32().br2016-02-171-0/+13
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* Use better form representing 32 x 128-bit floating-point registers.br2016-02-171-1/+1
| | | | Suggested by: kib
* There is no need to pre save tp in cpu_fork().br2016-02-171-6/+0
| | | | Discussed with: jhb
* Add the implementation of savectx().br2016-02-171-4/+23
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* Use callee-saved registers to pass args through fork_trampoline().br2016-02-172-17/+9
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* Use __uint64_t type for floating point registersbr2016-02-121-1/+1
| | | | | | as compiler don't know about __uint128_t yet. Discussed with: theraven, kib
* o Move non-generic kernel configuration out from GENERIC.br2016-02-113-3/+52
| | | | | | | | | | o Add kernel configuration for QEMU. Both SPIKE and QEMU kernel configs are temporary (until we will be able to obtain DTB from loader). Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Stop device enumeration when we see first empty slot.br2016-02-111-3/+2
| | | | | | | | This fixes operation in QEMU and saves some booting time as well. Pointed out by: Sagar Karandikar <skarandikar@berkeley.edu> Sponsored by: DARPA, AFRL Sponsored by: HEIF5
* Include sys/_task.h into uma_int.h, so that taskqueue.h isn't aglebius2016-02-092-2/+0
| | | | | | requirement for uma_int.h. Suggested by: jhb
* Access pcpup using gp register.br2016-02-043-16/+6
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* Reuse gp register for pcpu pointer.br2016-02-046-23/+38
| | | | | | | | | | | gp (global pointer) is used by compiler in userland only, so re-use it for pcpup in kernel, save it on stack on switching out to userland and load back on return to kernel. Discussed with: jhb, andrew, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D5178
* Fix build.br2016-02-041-0/+1
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* Fix build.glebius2016-02-041-0/+1
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* Welcome the RISC-V 64-bit kernel.br2016-01-2936-0/+9929
| | | | | | | | | | | | | | | | | | | | | | | | This is the final step required allowing to compile and to run RISC-V kernel and userland from HEAD. RISC-V is a completely open ISA that is freely available to academia and industry. Thanks to all the people involved! Special thanks to Andrew Turner, David Chisnall, Ed Maste, Konstantin Belousov, John Baldwin and Arun Thomas for their help. Thanks to Robert Watson for organizing this project. This project sponsored by UK Higher Education Innovation Fund (HEIF5) and DARPA CTSRD project at the University of Cambridge Computer Laboratory. FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv Reviewed by: andrew, emaste, kib Relnotes: Yes Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4982
* Correct RISC-V exception types.br2016-01-181-4/+6
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* Import RISC-V machine headers. This is a minimal set required to compilebr2015-12-1757-0/+4616
kernel and userland. Reviewed by: andrew, imp, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4554
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