summaryrefslogtreecommitdiffstats
path: root/sys/powerpc
Commit message (Collapse)AuthorAgeFilesLines
* Add preliminary support for binding interrupts to CPUs:jhb2008-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add a new intr_event method ie_assign_cpu() that is invoked when the MI code wishes to bind an interrupt source to an individual CPU. The MD code may reject the binding with an error. If an assign_cpu function is not provided, then the kernel assumes the platform does not support binding interrupts to CPUs and fails all requests to do so. - Bind ithreads to CPUs on their next execution loop once an interrupt event is bound to a CPU. Only shared ithreads are bound. We currently leave private ithreads for drivers using filters + ithreads in the INTR_FILTER case unbound. - A new intr_event_bind() routine is used to bind an interrupt event to a CPU. - Implement binding on amd64 and i386 by way of the existing pic_assign_cpu PIC method. - For x86, provide a 'intr_bind(IRQ, cpu)' wrapper routine that looks up an interrupt source and binds its interrupt event to the specified CPU. MI code can currently (ab)use this by doing: intr_bind(rman_get_start(irq_res), cpu); however, I plan to add a truly MI interface (probably a bus_bind_intr(9)) where the implementation in the x86 nexus(4) driver would end up calling intr_bind() internally. Requested by: kmacy, gallatin, jeff Tested on: {amd64, i386} x {regular, INTR_FILTER}
* Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on whatraj2008-03-124-1/+37
| | | | | | | | | | | | might be currently programmed into the registers. Underlying firmware (U-Boot) would typically program MAC address into the first unit only, and others are left uninitialized. It is now possible to retrieve and program MAC address for all units properly, provided they were passed on in the bootinfo metadata. Reviewed by: imp, marcel Approved by: cognet (mentor)
* Remove kernel support for M:N threading.jeff2008-03-125-15/+2
| | | | | | | | While the KSE project was quite successful in bringing threading to FreeBSD, the M:N approach taken by the kse library was never developed to its full potential. Backwards compatibility will be provided via libmap.conf for dynamically linked binaries and static binaries will be broken.
* In intr_lookup(), when adding an IRQ to powerpc_intrs[], alsomarcel2008-03-111-7/+10
| | | | | | | set a default name. If the IRQ is added as a consequence of configurating the IRQ without there ever being a handler assigned to it, we will not have a name. This breaks the fragile intrcnt/intrnames logic.
* Don't use in32() and out32() when writing to the CCSRBAR. Themarcel2008-03-091-9/+26
| | | | | | in*() and out*() primitives should not be used, other than by ISA drivers. In this case they were used for memory-mapped I/O and were not even used in the spirit of the primitives.
* Enable the D-cache and I-cache when not already enabled.marcel2008-03-081-3/+28
| | | | | | | | | It so happens that U-Boot disables the D-cache when booting an ELF image, so this change makes sure we run with the D-cache enabled from now on. It shows too... While here, remove the duplicate definition of the hw.model sysctl.
* For AIM, have cpu_idle() set MSR_POW when the powerpc_pow_enabledmarcel2008-03-074-11/+16
| | | | | | variable is set. On my Mac Mini this puts the CPU in NAP mode when the kernel is idle and, any technical or environmental reasons aside, avoids that I have to listen to the fan all day :-)
* Add support for the BUS_CONFIG_INTR() method to the platform and tomarcel2008-03-079-42/+136
| | | | | openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4 are active-low.
* Add a catch-all for PCPU_MD_FIELDS. While we expect this to bemarcel2008-03-061-0/+7
| | | | | | | | | used in the kernel only (by virtue of checking for _KERNEL), ports like lsof (part of gtop) cheat. It sets _KERNEL, but does not set either AIM or E500. As such, PCPU_MD_FIELDS didn't get defined and the build broke. The catch-all is to define PCPU_MD_FIELDS with a dummy integer when at the end of line we ended up without a definition for it.
* o We don't have to keep track of the PIC, nor do we have to make suremarcel2008-03-051-28/+39
| | | | | | | it's probed first. The PowerPC platform code deals with everything. As such, probe devices in order of their location in the memory map. o Refactor the ocpbus_alloc_resource for readability and make sure we set the RID in the resource as per the new convention.
* o Various fixes related to PCI Express:marcel2008-03-051-37/+65
| | | | | | | | | | | | | | | | | | | | | | | | | - Even for the PCI Express host controller we need to use bus 0 for configuration space accesses to devices directly on the host controller's bus. - Pass the maximum number of slots to pci_ocp_init() because the caller knows how many slots the bus has. Previously a PCI or PCI-X bus underneath a PCI Express host controller would not be enumerated properly. o Pull the interrupt routing logic out of pci_ocp_init() and into its own function. The logic is not quite right and is expected to be a bit more complex. o Fix/add support for PCI domains. The PCI domain is the unit number as per other PCI host controller drivers. As such, we can use logical bus numbers again and don't have to guarantee globally unique bus numbers. Remove pci_ocp_busnr. Return the highest bus number ito the caller of pci_ocp_init() now that we don't have a global variable anymore. o BAR programming fixes: - Non-type0 headers have at most 1 BAR, not 0. - First write ~0 to the BAR in question and then read back its size. Obtained from: Juniper Networks (mostly)
* Also comment-out options MPC85XX. We don't define CCSRBAR_* without E500.marcel2008-03-041-1/+1
|
* Comment-out cpu E500. We can't yet build it with AIM at the same time.marcel2008-03-041-1/+1
|
* Add the pic_ipi method. While here, eliminate the unused openpic_ocpbus_softcmarcel2008-03-041-9/+4
| | | | struct.
* Import the omitted gdb_machdep.c for PowerPC kernel.raj2008-03-031-2/+57
| | | | | Approved by: cognet (mentor) MFp4: e500
* Connect MPC85XX to the PowerPC build.raj2008-03-032-0/+74
| | | | | | | | | | | | | | | | | The kernel config file is KERNCONF=MPC85XX, so the usual procedure applies: 1. make buildworld TARGET_ARCH=powerpc 2. make buildkernel TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 KERNCONF=MPC85XX This default config uses kernel-level FPU emulation. For the soft-float world approach: 1. make buildworld TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 2. disable FPU_EMU option in sys/powerpc/conf/MPC85XX 3. make buildkernel TARGET_ARCH=powerpc TARGET_CPUTYPE=e500 KERNCONF=MPC85XX Approved by: cognet (mentor) MFp4: e500
* Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.raj2008-03-0321-3/+9456
| | | | | | | | | | | | | | | | | | | | | | | | | | The PQ3 is a high performance integrated communications processing system based on the e500 core, which is an embedded RISC processor that implements the 32-bit Book E definition of the PowerPC architecture. For details refer to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E This port was tested and successfully run on the following members of the PQ3 family: MPC8533, MPC8541, MPC8548, MPC8555. The following major integrated peripherals are supported: * On-chip peripherals bus * OpenPIC interrupt controller * UART * Ethernet (TSEC) * Host/PCI bridge * QUICC engine (SCC functionality) This commit brings the main functionality and will be followed by individual drivers that are logically separate from this base. Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.raj2008-03-0310-139/+730
| | | | | | Approved by: cognet (mentor) Obtained from: Juniper, Semihalf MFp4: e500
* Unify and generalize PowerPC headers, adjust AIM code accordingly.raj2008-03-0212-105/+240
| | | | | | | | | | | | | | | | | | | | Rework of this area is a pre-requirement for importing e500 support (and other PowerPC core variations in the future). Mainly the following headers are refactored so that we can cover for low-level differences between various machines within PowerPC architecture: <machine/pcpu.h> <machine/pcb.h> <machine/kdb.h> <machine/hid.h> <machine/frame.h> Areas which use the above are adjusted and cleaned up. Credits for this rework go to marcel@ Approved by: cognet (mentor) MFp4: e500
* - Remove the old smp cpu topology specification with a new, more flexiblejeff2008-03-021-0/+7
| | | | | | | | | | | | | | | | | tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia
* Avoid hardcoding the kernel link address in the linker script.marcel2008-02-272-0/+7
| | | | | Use KERNBASE instead. While here, move the text sections forward to the beginning of the text segment.
* Teach PowerPC CPU identification routines to recognize e500 cores. Fix styleraj2008-02-253-93/+117
| | | | | | | issues in this area. Approved by: cognet (mentor) MFp4: e500
* Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPCraj2008-02-241-1/+5
| | | | | | | | | variations (e500 currently), this provides a gcc-level FPU emulation and is an alternative approach to the recently introduced kernel-level emulation (FPU_EMU). Approved by: cognet (mentor) MFp4: e500
* Don't define DEBUG. No debugging required.marcel2008-02-241-2/+0
| | | | Pointy hat: marcel
* Resolve warnings exposed by LINT.marcel2008-02-245-26/+5
| | | | | o Put prototypes in a single header only. o Fix printf format specifiers.
* Add FPU_EMU.marcel2008-02-231-0/+2
|
* Add a floating-point emulator so that a single userland or single ABImarcel2008-02-2313-0/+3880
| | | | | | | | | | can run on processors that don't have a FPU. This is typically the case for Book E processors. While a tuned system will probably want to use soft-float (or use a processor that has a FPU if the usage is FP intensive enough), allowing hard-float on FPU-less systems gives great portability and flexibility. Obtained from: NetBSD
* Define the bootinfo structure for FreeBSD. It is not used onmarcel2008-02-232-73/+56
| | | | AIM, but it's used for BookE.
* Enable option WITNESS_SKIPSPIN by default.marcel2008-02-161-0/+1
|
* Remove SMP left-overs from NetBSD.marcel2008-02-122-12/+3
|
* There's no need to suppress option GDB.marcel2008-02-121-1/+0
|
* Add PIC support for IPIs. When registering an interrupt handler,marcel2008-02-129-59/+143
| | | | | | the PIC also informs the platform at which IRQ level it can start assigning IPIs, since this can depend on the number of IRQs supported for external interrupts.
* One of my powerbooks has this chip in it..julian2008-01-261-0/+1
| | | | | | Confirmed by looking at netbsd.. they have also added this. checked by grehen MFC After: 3 days
* Add COMPAT_FREEBSD7 and enable it in configs that have COMPAT_FREEBSD6.jhb2008-01-071-0/+1
|
* Add an access type parameter to pmap_enter(). It will be used to implementalc2008-01-031-2/+2
| | | | | | | superpage promotion. Correct a style error in kmem_malloc(): pmap_enter()'s last parameter is a Boolean.
* Add configuration knobs for the superpage reservation system. Initially,alc2007-12-271-0/+7
| | | | the reservation will only be enabled on amd64.
* Add a new 'why' argument to kdb_enter(), and a set of constants to userwatson2007-12-252-2/+3
| | | | | | | | | for that argument. This will allow DDB to detect the broad category of reason why the debugger has been entered, which it can use for the purposes of deciding which DDB script to run. Assign approximate why values to all current consumers of the kdb_enter() interface.
* Apply missing s/rv/res/g in previous commit.marcel2007-12-214-4/+4
|
* MFamd64/ia64/i386: Only set the rman bus tags and handles injhb2007-12-204-8/+4
| | | | | | | bus_activate_resource() methods instead of splitting it up between bus_alloc_resource() and bus_activate_resource(). Glanced at by: marcel
* Redefine bus_space_tag_t on PowerPC from a 32-bit integral tomarcel2007-12-199-651/+1146
| | | | | | | | | | | | | | | | | | | | | | a pointer to struct bus_space. The structure contains function pointers that do the actual bus space access. The reason for this change is that previously all bus space accesses were little endian (i.e. had an explicit byte-swap for multi-byte accesses), because all busses on Macs are little endian. The upcoming support for Book E, and in particular the E500 core, requires support for big-endian busses because all embedded peripherals are in the native byte-order. With this change, there's no distinction between I/O port space and memory mapped I/O. PowerPC doesn't have I/O port space. Busses assign tags based on the byte-order only. For that purpose, two global structures exist (bs_be_tag and bs_le_tag), of which the address can be taken to get a valid tag. Obtained from: Juniper, Semihalf
* Rename OEA to AIM. The former means nothing as it applies to allmarcel2007-12-163-7/+3
| | | | | | | | | | | | processors (it's the PowerPC Operating Environment Architecture). AIM designates the processors made by the Apple-IBM-Motorola alliance and those we typically support. While here, remove the NetBSD option IPKDB. It's not an option used by us. Also, PPC_HAVE_FPU is not used by us either. Remove that too. Obtained from: Juniper, Semihalf
* This file was repocopied to src/sys/powerpc/aim, where it willmarcel2007-12-1415-7483/+0
| | | | live on -- an afterlife.
* Forced commit to record that this file was repocopied frommarcel2007-12-142-2/+2
| | | | src/sys/powerpc/powerpc and modified for its new location.
* Remove unused file.marcel2007-12-141-110/+0
|
* Add stubs to unbreak LINT.jkoshy2007-12-071-0/+4
|
* Break out stack(9) from ddb(4):rwatson2007-12-024-38/+135
| | | | | | | | | | | | | | | | | | | | - Introduce per-architecture stack_machdep.c to hold stack_save(9). - Introduce per-architecture machine/stack.h to capture any common definitions required between db_trace.c and stack_machdep.c. - Add new kernel option "options STACK"; we will build in stack(9) if it is defined, or also if "options DDB" is defined to provide compatibility with existing users of stack(9). Add new stack_save_td(9) function, which allows the capture of a stacktrace of another thread rather than the current thread, which the existing stack_save(9) was limited to. It requires that the thread be neither swapped out nor running, which is the responsibility of the consumer to enforce. Update stack(9) man page. Build tested: amd64, arm, i386, ia64, powerpc, sparc64, sun4v Runtime tested: amd64 (rwatson), arm (cognet), i386 (rwatson)
* Define atomic_readandclear_ptr.jasone2007-11-271-0/+1
|
* Implement the _long functions using u_long rather than trying tojb2007-11-261-5/+43
| | | | | | cast as uint32_t which is defined as unsigned int. gcc doesn't want to consider that there might not be much difference between an int and a long on a 32 bit architecture.
* Extend critical section coverage in the low-level interrupt handlers toscottl2007-11-211-1/+1
| | | | | | | | | | | | | | | | | | include the ithread scheduling step. Without this, a preemption might occur in between the interrupt getting masked and the ithread getting scheduled. Since the interrupt handler runs in the context of curthread, the scheudler might see it as having a such a low priority on a busy system that it doesn't get to run for a _long_ time, leaving the interrupt stranded in a disabled state. The only way that the preemption can happen is by a fast/filter handler triggering a schduling event earlier in the handler, so this problem can only happen for cases where an interrupt is being shared by both a fast/filter handler and an ithread handler. Unfortunately, it seems to be common for this sharing to happen with network and USB devices, for example. This fixes many of the mysterious TCP session timeouts and NIC watchdogs that were being reported. Many thanks to Sam Lefler for getting to the bottom of this problem. Reviewed by: jhb, jeff, silby
* Define atomic_cmpset_acq_long and atomic_cmpset_rel_long so thatjb2007-11-191-2/+4
| | | | | they use casts rather than just assuming that the compiler will DTRT without complaining.
OpenPOWER on IntegriCloud