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* Add a new ipi_cpu() function to the MI IPI API that can be used to send anjhb2010-08-062-0/+9
| | | | | | | | | | | | IPI to a specific CPU by its cpuid. Replace calls to ipi_selected() that constructed a mask for a single CPU with calls to ipi_cpu() instead. This will matter more in the future when we transition from cpumask_t to cpuset_t for CPU masks in which case building a CPU mask is more expensive. Submitted by: peter, sbruno Reviewed by: rookie Obtained from: Yahoo! (x86) MFC after: 1 month
* Improve hash coverage for kernel page table entries by modifying the kernelnwhitehorn2010-07-313-16/+10
| | | | | ESID -> VSID map function. This makes ZFS run stably on PowerPC under heavy loads (repeated simultaneous SVN checkouts and updates).
* Add support for the IBM Full-System Simulator (Mambo). This code has beennwhitehorn2010-07-319-0/+825
| | | | developed against the 970 and Cell simulators.
* Add MALLOC_DEBUG_MAXZONES=8 to powerpc64 GENERIC configuration file.mdf2010-07-301-0/+1
| | | | | Requested by: nwhitehorn Approved by: zml (mentor)
* Add MALLOC_DEBUG_MAXZONES debug malloc(9) option to use multiple umamdf2010-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | zones for each malloc bucket size. The purpose is to isolate different malloc types into hash classes, so that any buffer overruns or use-after-free will usually only affect memory from malloc types in that hash class. This is purely a debugging tool; by varying the hash function and tracking which hash class was corrupted, the intersection of the hash classes from each instance will point to a single malloc type that is being misused. At this point inspection or memguard(9) can be used to catch the offending code. Add MALLOC_DEBUG_MAXZONES=8 to -current GENERIC configuration files. The suggestion to have this on by default came from Kostik Belousov on -arch. This code is based on work by Ron Steinke at Isilon Systems. Reviewed by: -arch (mostly silence) Reviewed by: zml Approved by: zml (mentor)
* Very rough first cut at NUMA support for the physical page allocator. Forjhb2010-07-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | now it uses a very dumb first-touch allocation policy. This will change in the future. - Each architecture indicates the maximum number of supported memory domains via a new VM_NDOMAIN parameter in <machine/vmparam.h>. - Each cpu now has a PCPU_GET(domain) member to indicate the memory domain a CPU belongs to. Domain values are dense and numbered from 0. - When a platform supports multiple domains, the default freelist (VM_FREELIST_DEFAULT) is split up into N freelists, one for each domain. The MD code is required to populate an array of mem_affinity structures. Each entry in the array defines a range of memory (start and end) and a domain for the range. Multiple entries may be present for a single domain. The list is terminated by an entry where all fields are zero. This array of structures is used to split up phys_avail[] regions that fall in VM_FREELIST_DEFAULT into per-domain freelists. - Each memory domain has a separate lookup-array of freelists that is used when fulfulling a physical memory allocation. Right now the per-domain freelists are listed in a round-robin order for each domain. In the future a table such as the ACPI SLIT table may be used to order the per-domain lookup lists based on the penalty for each memory domain relative to a specific domain. The lookup lists may be examined via a new vm.phys.lookup_lists sysctl. - The first-touch policy is implemented by using PCPU_GET(domain) to pick a lookup list when allocating memory. Reviewed by: alc
* When compat32 binary asks for the value of hw.machine_arch, report thekib2010-07-221-0/+5
| | | | | | | | | | | name of 32bit sibling architecture instead of the host one. Do the same for hw.machine on amd64. Add a safety belt debug.adaptive_machine_arch sysctl, to turn the substitution off. Reviewed by: jhb, nwhitehorn MFC after: 2 weeks
* Eliminate FDT_IMMR_VA define.raj2010-07-192-9/+1
| | | | | This removes platform dependencies from <machine>/fdt.h for the benfit of portability.
* Remove obsolete code that sets SHMMAXPGS to a tiny value by defaultnwhitehorn2010-07-131-7/+0
| | | | on PowerPC.
* Add GENERIC kernel config for powerpc64.nwhitehorn2010-07-131-0/+182
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* MFppc64:nwhitehorn2010-07-1371-1019/+5497
| | | | | | | Kernel sources for 64-bit PowerPC, along with build-system changes to keep 32-bit kernels compiling (build system changes for 64-bit kernels are coming later). Existing 32-bit PowerPC kernel configurations must be updated after this change to specify their architecture.
* Fix printf specifier to allow 32/64 bit builds.grehan2010-07-121-1/+1
| | | | Obtained from: projects/ppc64
* Unify ABI-related bits of the Book-E and AIM machdep routinesnwhitehorn2010-07-126-1026/+685
| | | | | | | | (exec_setregs, etc.) in order to simplify the addition of 64-bit support, and possible future extension of the Book-E code to handle hard floating point and Altivec. MFC after: 1 month
* MFppc64:nwhitehorn2010-07-121-3/+31
| | | | | Provide ELF definitions for 64-bit PowerPC. This unbreaks the powerpc loader build.
* Convert Freescale PowerPC platforms to FDT convention.raj2010-07-1124-2220/+1834
| | | | | | | | | | | | | | | | | | | | | | | | | The following systems are affected: - MPC8555CDS - MPC8572DS This overhaul covers the following major changes: - All integrated peripherals drivers for Freescale MPC85XX SoC, which are currently in the FreeBSD source tree are reworked and adjusted so they derive config data out of the device tree blob (instead of hard coded / tabelarized values). - This includes: LBC, PCI / PCI-Express, I2C, DS1553, OpenPIC, TSEC, SEC, QUICC, UART, CFI. - Thanks to the common FDT infrastrucutre (fdtbus, simplebus) we retire ocpbus(4) driver, which was based on hard-coded config data. Note that world for these platforms has to be built WITH_FDT. Reviewed by: imp Sponsored by: The FreeBSD Foundation
* The number after 2 is 3, not 4.nwhitehorn2010-07-091-1/+1
| | | | MFC after: 3 days
* Remove an unnecessary include of opt_psim.h, which is not present onnwhitehorn2010-07-091-1/+0
| | | | powerpc64.
* MFppc64:nwhitehorn2010-07-091-3/+3
| | | | | Minor 64-bit-cleanliness upgrades and support for platform detection on subtly-broken OF implementations like in the Mambo simulator.
* MFppc64:nwhitehorn2010-07-091-7/+7
| | | | | Use longs instead of ints as the native word type in bcopy(). This will expand nicely on 64-bit systems.
* MFppc64:nwhitehorn2010-07-091-3/+3
| | | | | Check if devices are direct-mapped individually instead of just checking the value of hw_direct_map.
* Replace the existing PowerPC busdma implementation with the one fromnwhitehorn2010-07-083-211/+834
| | | | | amd64 (with slight modifications). This provides support for bounce buffers, which are required on systems with RAM above 4 GB.
* Make ofw_syscons work on 64-bit systems.nwhitehorn2010-07-081-3/+3
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* Fix several bugs in the real-mode Open Firmware implementation and providenwhitehorn2010-07-081-157/+325
| | | | | | a virtual-mode version for use on 64-bit systems, which have 32-bit firmware implementations and require similar constraints on addressing to the real-mode implementation.
* Change the argument type to OF_call_method to take an array of cell_tnwhitehorn2010-07-081-4/+3
| | | | | instead of unsigned longs to prepare for platforms where they are not the same.
* It does not actually make sense to provide an IPI facility on non-rootnwhitehorn2010-07-061-4/+3
| | | | PICs, so replace cpuid logic with an assert.
* Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.nwhitehorn2010-07-061-7/+14
| | | | | | | | | Because slave PICs send all interrupts to their CPU 0 output line (which is routed to a pin on the master PIC), changes to per-CPU register banks like EOI on the slave PIC must be accessed for CPU 0, instead of the CPU actually processing the interrupt. Submitted by: Andreas Tobler
* Move the EOI logic when starting ithreads into intr_machdep instead ofnwhitehorn2010-07-064-18/+25
| | | | | relying on it as a side effect of PIC_MASK() in the PIC drivers, and add an inmplementation of assign_cpu() for the kernel interrupt layer.
* Add a missing conditional. We should not bind the PIC interrupt unlessnwhitehorn2010-07-031-1/+2
| | | | | | the interrupt's PIC (a) exists and (b) is the root PIC. Reported by: Andreas Tobler
* Remove the unneeded header <machine/intr.h>.marcel2010-07-0211-90/+0
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* MFia64:marcel2010-07-011-1/+1
| | | | | When compiling with profiling, we define PROF for userspace and GPROF for the kernel.
* Move prototypes for kern_sigtimedwait() and kern_sigprocmask() tojhb2010-06-302-0/+2
| | | | <sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
* Fix profiling (part 1):marcel2010-06-292-2/+2
| | | | | | o Functions are 4-byte aligned for Book-E. o We get compiled with -DPROF and not -DGPROF if profiling is enabled.
* Assign PCI intline values for ISA interrupts using the new INTR_VEC()marcel2010-06-241-3/+3
| | | | macro.
* Remove debugging printf() -- that is, I assume it was for debugging :-)marcel2010-06-241-2/+0
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* Pass the device_t of the AT PIC driver to atpic_intr() so thatmarcel2010-06-241-5/+2
| | | | | we don't have to use a global variable. Pass a NULL frame pointer to the dispatch function just like openpic(4).
* With openpic(4) using active-low as the default polarity, reconfiguremarcel2010-06-231-2/+9
| | | | | | | | | | the internal interrupt sources as active-high. The internal interrupt sources are disabled when programmed as active-low. Note that the internal interrupts have no sense bit like the external interrupts. We program them as edge-triggered to make sure we write a 0 value to a reserved register. It does not in any way say anything about the sense of internal interrupt.
* Configure interrupts on SMP systems to be distributed among all onlinenwhitehorn2010-06-239-3/+110
| | | | | | CPUs by default, and provide a functional version of BUS_BIND_INTR(). While here, fix some potential concurrency problems in the interrupt handling code.
* In the attach method, refactor to take into account thatmarcel2010-06-231-3/+10
| | | | | BUS_GET_RESOURCE_LIST() can return a NULL pointer -- and will for MPC85xx kernels.
* Temporarily disable instruction relocation while setting up the kernel'snwhitehorn2010-06-201-1/+6
| | | | | | | | IBAT entry in early boot in order to prevent possible faults from races between the instruction cache and the MMU. PR: powerpc/148003 MFC after: 3 days
* Missed commit in r209310: the IRQ number in INTR_VEC() should havenwhitehorn2010-06-181-1/+1
| | | | | | parantheses around it to allow arithmetic expressions to be passed. Submitted by: Andreas Tobler
* Add MSI support for PCI devices attached to the CPC925 and CPC945 bridgesnwhitehorn2010-06-182-3/+165
| | | | found in Apple and IBM G5 systems.
* Add support for the Keywest I2C controller in Apple uninorth northbridges.nwhitehorn2010-06-181-2/+7
| | | | | | Although the Keywest registers have only 1 byte of content, they are secretly 4-byte registers, which became apparent from them moving on the big-endian Uninorth version of the controller.
* Change the default interrupt polarity on PowerPC systems from high to low.nwhitehorn2010-06-183-12/+24
| | | | | | On Apple systems at least, all the level interrupts are wired active low. Before this change, our PIC programming only worked because Apple hardware ignores the interrupt polarity bit on all interrupts except IRQ 0.
* Provide for multiple, cascaded PICs on PowerPC systems, and extend thenwhitehorn2010-06-1826-107/+288
| | | | | | OFW interrupt map interface to also return the device's interrupt parent. MFC after: 8.1-RELEASE
* Modify the console mouse pointer drawing routine to use single-byte writesnwhitehorn2010-06-151-17/+4
| | | | | | | | | instead of 4-byte ones. Because the mouse pointer can start part way through a character cell, 4-byte memory operations are not necessarily aligned, triggering a fatal alignment exception when the console pointer was moved on PowerPC G5 systems. MFC after: 3 days
* Make SMP work on MPC7400-based Apple desktops like the PowerMac3,3.nwhitehorn2010-06-122-10/+42
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* Relax one of the new assertions in pmap_enter() a little. Specifically,alc2010-06-113-3/+6
| | | | | | allow pmap_enter() to be performed on an unmanaged page that doesn't have VPO_BUSY set. Having VPO_BUSY set really only matters for managed pages. (See, for example, pmap_remove_write().)
* Reduce the scope of the page queues lock and the number ofalc2010-06-103-80/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PG_REFERENCED changes in vm_pageout_object_deactivate_pages(). Simplify this function's inner loop using TAILQ_FOREACH(), and shorten some of its overly long lines. Update a stale comment. Assert that PG_REFERENCED may be cleared only if the object containing the page is locked. Add a comment documenting this. Assert that a caller to vm_page_requeue() holds the page queues lock, and assert that the page is on a page queue. Push down the page queues lock into pmap_ts_referenced() and pmap_page_exists_quick(). (As of now, there are no longer any pmap functions that expect to be called with the page queues lock held.) Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever be passed an unmanaged page. Assert this rather than returning "0" and "FALSE" respectively. ARM: Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH(). Push down the page queues lock inside of pmap_clearbit(), simplifying pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write(). Additionally, this allows for avoiding the acquisition of the page queues lock in some cases. PowerPC/AIM: moea*_page_exits_quick() and moea*_page_wired_mappings() will never be called before pmap initialization is complete. Therefore, the check for moea_initialized can be eliminated. Push down the page queues lock inside of moea*_clear_bit(), simplifying moea*_clear_modify() and moea*_clear_reference(). The last parameter to moea*_clear_bit() is never used. Eliminate it. PowerPC/BookE: Simplify mmu_booke_page_exists_quick()'s control flow. Reviewed by: kib@
* Add Open Firmware PNP info strings to GPIOs and Uninorth cells.nwhitehorn2010-06-062-0/+4
| | | | Submitted by: Andreas Tobler
* Correct a harmless typo introduced when copying code from mmu_oea64.nwhitehorn2010-06-051-1/+1
| | | | | Submitted by: alc MFC after: 8.1-RELEASE
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