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* Don't check the device ID. Instead, check the class, subclass andmarcel2010-01-291-28/+13
| | | | | | | | | | | | | programming I/F. New SoC designs have different device IDs, but don't need special treatment. Consequently, we fail to probe and attach for no other reason than not having added the device ID to the code. Bank on Freescale's sense of backward compatibility and assume that if we find a host controller, we know how work with it. This fixes detection of the PCI Express host controllers on Freescale's QorIQ family of processors (P1, P2 and P4).
* Move the examples for the 'hints' and 'env' keywords from various GENERICjhb2010-01-191-3/+0
| | | | | | kernel configs into NOTES. Reviewed by: imp
* Add INCLUDE_CONFIG_FILE in GENERIC on all non-embedded platforms.imp2010-01-101-0/+1
| | | | | | # This is the resolution of removing it from DEFAULTS... MFC after: 5 days
* In sys/<arch>/conf/Makefile set TARGET to <arch>. That allowsbz2010-01-081-0/+2
| | | | | | | | | | | | | | | | sys/conf/makeLINT.mk to only do certain things for certain architectures. Note that neither arm nor mips have the Makefile there, thus essentially not (yet) supporting LINT. This would enable them do add special treatment to sys/conf/makeLINT.mk as well chosing one of the many configurations as LINT. This is a hack of doing this and keeping it in a separate commit will allow us to more easily identify and back it out. Discussed on/with: arch, jhb (as part of the LINT-VIMAGE thread) MFC after: 1 month
* Remove extraneous semicolons, no functional changes.mbr2010-01-073-8/+8
| | | | | Submitted by: Marc Balmer <marc@msys.ch> MFC after: 1 week
* Revert 200594. This file isn't intended for these sorts of things.imp2010-01-041-7/+0
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* Add vlan(4) to all GENERIC kernels.brooks2010-01-031-0/+1
| | | | MFC after: 1 week
* Update d_mmap() to accept vm_ooffset_t and vm_memattr_t.rnoland2009-12-292-3/+4
| | | | | | | | | | | | | This replaces d_mmap() with the d_mmap2() implementation and also changes the type of offset to vm_ooffset_t. Purge d_mmap2(). All driver modules will need to be rebuilt since D_VERSION is also bumped. Reviewed by: jhb@ MFC after: Not in this lifetime...
* Remove a warning in DELAY about large delays. In kern_shutdown.cmarcel2009-12-191-8/+1
| | | | we use excessive delays quite habitually.
* Add INCLUDE_CONFIG_FILE, and a note in comments about how to alsodougb2009-12-161-0/+7
| | | | include the comments with CONFIGARGS
* Unbreak build.nwhitehorn2009-12-061-1/+1
| | | | Pointy hat to: me
* MFp4:mav2009-12-064-57/+37
| | | | | | | | | | | | | | | | | | Introduce ATA_CAM kernel option, turning ata(4) controller drivers into cam(4) interface modules. When enabled, this options deprecates all ata(4) peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers (ada, cd, ...) and interfaces to be natively used instead. As side effect of this, ata(4) mode setting code was completely rewritten to make controller API more strict and permit above change. While doing this, SATA revision was separated from PATA mode. It allows DMA-incapable SATA devices to operate and makes hw.ata.atapi_dma tunable work again. Also allow ata(4) controller drivers (except some specific or broken ones) to handle larger data transfers. Previous constraint of 64K was artificial and is not really required by PCI ATA BM specification or hardware. Submitted by: nwitehorn (powerpc part)
* The first argument of dcbz interprets r0 as a literal zero, not the second.nwhitehorn2009-12-031-1/+1
| | | | | | This worked before by accident. MFC after: 1 week
* Bump limits on PowerPC. This allows large executables like parts of LLVMnwhitehorn2009-12-021-5/+5
| | | | | | | | to function. Reviewed by: grehan Obtained from: NetBSD MFC after: 2 weeks
* Add atp(4) to powerpc GENERIC. Most late-generation Apple PowerPC laptopsnwhitehorn2009-11-291-0/+1
| | | | have trackpads that do not work at all without this driver.
* Add a CPU features framework on PowerPC and simplify CPU setup a littlenwhitehorn2009-11-286-99/+131
| | | | | | | | | | more. This provides three new sysctls to user space: hw.cpu_features - A bitmask of available CPU features hw.floatingpoint - Whether or not there is hardware FP support hw.altivec - Whether or not Altivec is available PR: powerpc/139154 MFC after: 10 days
* Simplify the invocation of vm_fault(). Specifically, eliminate the flagalc2009-11-272-5/+2
| | | | | | | VM_FAULT_DIRTY. The information provided by this flag can be trivially inferred by vm_fault(). Discussed with: kib
* Garbage collect some code that was never compiled in to handle Altivecnwhitehorn2009-11-221-6/+0
| | | | during traps. It predates actual Altivec support and was never used.
* Always allocate PCI/ISA interrupts as shareable so that sharedmarcel2009-11-201-0/+1
| | | | interrupts don't cause driver attach failures.
* Fix cpuid output on E500 core.raj2009-11-191-0/+2
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* Provide a real fix to the too-many-translations problem when bootingnwhitehorn2009-11-121-56/+62
| | | | | | | | | | | | from CD on 64-bit hardware to replace existing band-aids. This occurred when the preloaded mdroot required too many mappings for the static buffer. Since we only use the translations buffer once, allocate a dynamic buffer on the stack. This early in the boot process, the call chain is quite short and we can be assured of having sufficient stack space. Reviewed by: grehan
* Extract the code that records syscall results in the frame into MDkib2009-11-104-73/+113
| | | | | | | | | | | function cpu_set_syscall_retval(). Suggested by: marcel Reviewed by: marcel, davidxu PowerPC, ARM, ia64 changes: marcel Sparc64 tested and reviewed by: marius, also sunv reviewed MIPS tested by: gonzo MFC after: 1 month
* Spell sz correctly.nwhitehorn2009-11-091-1/+1
| | | | Pointed out by: jmallett
* Increase the size of the OFW translations buffer to handle G5 systemsnwhitehorn2009-11-091-1/+4
| | | | | | | | that use many translation regions in firmware, and add bounds checking to prevent buffer overflows in case even the new value is exceeded. Reported by: Jacob Lambert MFC after: 3 days
* Unbreak E500 builds. The inline assembly for the 970 CPUsmarcel2009-11-061-1/+6
| | | | is invalid when compiling for BookE.
* Unbreak cpu_switch(). The register allocator in my brain is clearlynwhitehorn2009-10-311-4/+6
| | | | | broken. Also, Altivec context switching worked before only by accident, but should work now by design.
* Remove an unnecessary sync that crept in the last commit.nwhitehorn2009-10-311-1/+0
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* Fix a race in casuword() exposed by csup. casuword() non-atomically readnwhitehorn2009-10-311-2/+13
| | | | | | the current value of its argument before atomically replacing it, which could occasionally return the wrong value on an SMP system. This resulted in user mutex operations hanging when using threaded applications.
* Loop on blocked threads when using ULE scheduler, removing annwhitehorn2009-10-311-9/+21
| | | | XXX MP comment.
* Garbage collect set_user_sr(), which is declared static inline andnwhitehorn2009-10-311-9/+0
| | | | never called.
* Make procstat -k work on PowerPC by avoiding mistakenly using signednwhitehorn2009-10-301-2/+2
| | | | | compares with a low address (0x1000) and a high address (the KVA kernel stack).
* Turn off Altivec data-stream prefetching before going into power-savenwhitehorn2009-10-291-3/+21
| | | | mode on those CPUs that need it.
* In r197963, a race with thread being selected for signal deliverykib2009-10-272-14/+2
| | | | | | | | | | | | | while in kernel mode, and later changing signal mask to block the signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls. Use kern_sigprocmask() instead of direct manipulation of td_sigmask to reschedule newly blocked signals, closing the race. Reviewed by: davidxu Tested by: pho MFC after: 1 month
* Turn on NAP mode on G5 systems, and refactor the HID0 setup code a little.nwhitehorn2009-10-242-89/+160
| | | | | This makes my G5 Xserve sound slightly less like it is filled with howling banshees.
* Allow Heathrow-based machines to boot a kernel containing option SMPnwhitehorn2009-10-241-1/+7
| | | | without panicing.
* Remove debugging printf that snuck in here.nwhitehorn2009-10-231-1/+0
| | | | Pointy hat to: me
* Add some more paranoia to setting HID registers, and update the AIMnwhitehorn2009-10-233-12/+27
| | | | | | | clock routines to work better with SMP. This makes SMP work fully and stably on an Xserve G5. Obtained from: Book-E (clock bits)
* Do not map the trap vectors into the kernel's address space. They arenwhitehorn2009-10-232-6/+13
| | | | | | | | only used in real mode and keeping them mapped only serves to make NULL a valid address, which results in silent NULL pointer deferences. Suggested by: Patrick Kerharo Obtained from: projects/ppc64
* Add SMP support on U3-based G5 systems. This does not yet work perfectly:nwhitehorn2009-10-239-103/+214
| | | | | | | | | | at least on my Xserve, getting the decrementer and timebase on APs to tick requires setting up a clock chip over I2C, which is not yet done. While here, correct the 64-bit tlbie function to set the CPU to 64-bit mode correctly. Hardware donated by: grehan
* o Introduce vm_sync_icache() for making the I-cache coherent withmarcel2009-10-217-71/+117
| | | | | | | | | | | | | | | | | | | | | the memory or D-cache, depending on the semantics of the platform. vm_sync_icache() is basically a wrapper around pmap_sync_icache(), that translates the vm_map_t argumument to pmap_t. o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc it replaces the pmap_page_executable() function, added to solve the I-cache problem in uiomove_fromphys(). o In proc_rwmem() call vm_sync_icache() when writing to a page that has execute permissions. This assures that when breakpoints are written, the I-cache will be coherent and the process will actually hit the breakpoint. o This also fixes the Book-E PMAP implementation that was missing necessary locking while trying to deal with the I-cache coherency in pmap_enter() (read: mmu_booke_enter_locked). The key property of this change is that the I-cache is made coherent *after* writes have been done. Doing it in the PMAP layer when adding or changing a mapping means that the I-cache is made coherent *before* any writes happen. The difference is key when the I-cache prefetches.
* Don't assume that physical addresses are identity mapped. This allowsnwhitehorn2009-10-181-1/+8
| | | | | the second processor on G5 systems to start. Note that SMP is still non-functional on these systems because of IPI delivery problems.
* Correct another typo. Actually save the condition register insteadnwhitehorn2009-10-111-1/+1
| | | | of overwriting r12 by mistake.
* Correct a typo here and actually save DSISR instead of overwriting it.nwhitehorn2009-10-111-1/+1
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* Define architectural load bases for PIE binaries. Addresses were selectedkib2009-10-101-0/+2
| | | | | | | | | | by looking at the bases used for non-relocatable executables by gnu ld(1), and adjusting it slightly. Discussed with: bz Reviewed by: kan Tested by: bz (i386, amd64), bsam (linux) MFC after: some time
* Make sure that the primary native brandinfo always gets addedbz2009-10-031-1/+1
| | | | | | | | | | | | | first and the native ia32 compat as middle (before other things). o(ld)brandinfo as well as third party like linux, kfreebsd, etc. stays on SI_ORDER_ANY coming last. The reason for this is only to make sure that even in case we would overflow the MAX_BRANDS sized array, the native FreeBSD brandinfo would still be there and the system would be operational. Reviewed by: kib MFC after: 1 month
* Add a new sysctl for reporting all of the supported page sizes.alc2009-09-181-0/+2
| | | | | Reviewed by: jhb MFC after: 3 weeks
* Add a few SCSI controllers to GENERIC that can be found on Powermacs.nwhitehorn2009-09-101-0/+11
| | | | | | | | | This allows installation onto SCSI disks as shipped, for example, with the Powermac G3. PR: powerpc/138543 Obtained from: sparc64 MFC after: 3 days
* Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating anphk2009-09-082-18/+57
| | | | | architecture specific include file containing the _ALIGN* stuff which <sys/socket.h> needs.
* Remove some debugging (KTR_VERBOSE) that crept into ppc GENERIC long agonwhitehorn2009-09-081-4/+0
| | | | | | and is present on no other architectures by default. MFC after: 4 days
* * Completely Remove the option STOP_NMI from the kernel. This optionattilio2009-08-132-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | has proven to have a good effect when entering KDB by using a NMI, but it completely violates all the good rules about interrupts disabled while holding a spinlock in other occasions. This can be the cause of deadlocks on events where a normal IPI_STOP is expected. * Adds an new IPI called IPI_STOP_HARD on all the supported architectures. This IPI is responsible for sending a stop message among CPUs using a privileged channel when disponible. In other cases it just does match a normal IPI_STOP. Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64 architectures, while on the other has a normal IPI_STOP effect. It is responsibility of maintainers to eventually implement an hard stop when necessary and possible. * Use the new IPI facility in order to implement a new userend SMP kernel function called stop_cpus_hard(). That is specular to stop_cpu() but it does use the privileged channel for the stopping facility. * Let KDB use the newly introduced function stop_cpus_hard() and leave stop_cpus() for all the other cases * Disable interrupts on CPU0 when starting the process of APs suspension. * Style cleanup and comments adding This patch should fix the reboot/shutdown deadlocks many users are constantly reporting on mailing lists. Please don't forget to update your config file with the STOP_NMI option removal Reviewed by: jhb Tested by: pho, bz, rink Approved by: re (kib)
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